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pdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý×÷ 0 øpwmpclkÙ(ãdefault8 pdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý×÷ 0 øpwmpclkÙ)ãdefault8 pdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý× ÷ 0 øpwmpclkÙ*ãdefault8 pdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý×0÷ 0 øpwmpclkÙ+ãdefault8 pdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdóýÙpower-controller!,rockchip,rk3568-power-controllerC £power-domain@7ó÷W,Cpower-domain@8ó÷ÌÍ W-./Cpower-domain@9ó ÷ÚÛÜ W012Cpower-domain@10ó ÷ñòW345678Cpower-domain@11ó ÷íW9Cpower-domain@13÷ó W:Cpower-domain@14ó÷ W;<=Cpower-domain@15ó÷ W>?@ABCDECgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostóýæ@$�()' ^jobmmugpu÷øgpubusþF%pokaynG£œvideo-codec@fdea0400,rockchip,rk3568-vpuóýê �‹^vdpu÷îï øaclkhclkzH% iommu@fdea0800,rockchip,rk3568-iommuóýê@ �Š øaclkiface÷îï% �£Hrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaóýë€ �Z÷óôõøaclkhclksclkD&$% Žcoreaxiahb% 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øcoreahbDmpokayi2s@fe400000,rockchip,rk3568-i2s-tdmóþ@ �42=ABFÏqFÏq÷?C9ømclk_txmclk_rxhclkfµtxDPQ Žtx-mrx-mn spokay£ i2s@fe410000,rockchip,rk3568-i2s-tdmóþA �52EIBFÏqFÏq÷GK:ømclk_txmclk_rxhclkffµrxtxDRS Žtx-mrx-mn ãdefault0Ùghijklmnopqrs pdisabledi2s@fe420000,rockchip,rk3568-i2s-tdmóþB �62MBFÏq÷OO;ømclk_txmclk_rxhclkffµtxrxDTŽtx-mn ãdefaultÙstuvs pdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmóþC �7÷SW<ømclk_txmclk_rxhclkffµtxrxDUV Žtx-mrx-mn s pdisabledpdm@fe440000,rockchip,rk3568-pdmóþD �L÷ZYøpdm_clkpdm_hclkf µrxÙwxyz{|ãdefaultDXŽpdm-ms pdisabledspdif@fe460000,rockchip,rk3568-spdifóþF �f ømclkhclk÷_\fµtxãdefaultÙ}s pdisableddma-controller@fe530000,arm,pl330arm,primecellóþS@� ¿÷  øapb_pclkÖ£&dma-controller@fe550000,arm,pl330arm,primecellóþU@�¿÷  øapb_pclkÖ£fi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþZ �/÷HG øi2cpclkÙ~ãdefault  pdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ[ �0÷JI øi2cpclkÙãdefault  pdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ\ �1÷LK øi2cpclkÙ€ãdefault  pdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ] �2÷NM øi2cpclkÙ�ãdefault  pdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ^ �3÷PO øi2cpclkÙ‚ãdefault pokayrtc@51,haoyu,hym8563óQ#� Ærtcic_32koutãdefaultÙƒÃwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtóþ` �•÷ øtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spióþa �g÷RQøspiclkapb_pclk&&µtxrxãdefault Ù„…†  pdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spióþb �h÷TSøspiclkapb_pclk&&µtxrxãdefault Ù‡ˆ‰  pdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spióþc �i÷VUøspiclkapb_pclk&&µtxrxãdefault ÙŠ‹Œ  pdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spióþd �j÷XWøspiclkapb_pclk&&µtxrxãdefault Ù�Ž�  pdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartóþe �u÷øbaudclkapb_pclk&&Ù�ãdefault!. pdisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartóþf �v÷# øbaudclkapb_pclk&&Ù‘ãdefault!.pokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartóþg �w÷'$øbaudclkapb_pclk&&Ù’ãdefault!. pdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartóþh �x÷+(øbaudclkapb_pclk&& Ù“ãdefault!. pdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartóþi �y÷/,øbaudclkapb_pclk& & Ù”ãdefault!. pdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþj �z÷30øbaudclkapb_pclk& & Ù•ãdefault!. pdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþk �{÷74øbaudclkapb_pclk&&Ù–ãdefault!. pdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþl �|÷;8øbaudclkapb_pclk&&Ù—ãdefault!. pdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþm �}÷?<øbaudclkapb_pclk&&Ù˜ãdefault!. pdisabledthermal-zonescpu-thermalád÷è ™tripscpu_alert0 p !Ðîpassive£šcpu_alert1 $ø !Ðîpassivecpu_crit s !Ð îcriticalcooling-mapsmap0 ,š0 1 ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermalá÷è ™tripsgpu-threshold p !Ðîpassivegpu-target $ø !Ðîpassive£›gpu-crit s !Ð îcriticalcooling-mapsmap0 ,› 1œÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcóþq �s2Bf@ ®`÷øtsadcapb_pclkD�‚×n  @sãdefaultsleepÙ� Wž apokay w Ž£™saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcóþr �]÷øsaradcapb_pclkD€ Žsaradc-apb ©pokay »Ÿpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn÷ZY øpwmpclkÙ ãdefault8 pdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn÷ZY øpwmpclkÙ¡ãdefault8 pdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn ÷ZY øpwmpclkÙ¢ãdefault8 pdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn0÷ZY øpwmpclkÙ£ãdefault8 pdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo÷]\ øpwmpclkÙ¤ãdefault8 pdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo÷]\ øpwmpclkÙ¥ãdefault8 pdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo ÷]\ øpwmpclkÙ¦ãdefault8 pdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo0÷]\ øpwmpclkÙ§ãdefault8 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosno-sdiono-mmcbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfdata-lanesvpcie3v3-supplystdout-pathenable-active-highstartup-delay-usgpiodebounce-intervallabellinux,codecolorfunctionlinux,default-trigger