Ð þíÛÔ8ÏØ( üÏ  ,radxa,rock-3crockchip,rk35667Radxa ROCK 3Caliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe310000ì/mmc@fe2b0000ñ/mmc@fe2c0000cpus cpu@0öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@100öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@200öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@300öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² l3-cache,cacheºÆ@M@_²opp-table-0,operating-points-v2Ô²opp-408000000ßQ– æ »  » Œ0ôœ@opp-600000000ß#ÃF æ »  » Œ0opp-816000000ß0£, æ »  » Œ0opp-1104000000ßAÍ´ æ »  » Œ0opp-1416000000ßTfr æ »  » Œ0opp-1608000000ß_Ø" æà˜à˜Œ0opp-1800000000ßkIÒ æ��Œ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc‚" protocol@14(²opp-table-1,operating-points-v2²Dopp-200000000ß ëÂ æ øP øPB@opp-300000000ßá£ æ øP øPB@opp-400000000ßׄ æ øP øPB@opp-600000000ß#ÃF æ »  » B@opp-700000000ß)¹' æ~ð~ðB@opp-800000000ß/¯ æB@B@B@hdmi-sound,simple-audio-card5HDMILi2seokaysimple-audio-card,codec†simple-audio-card,cpu† pmu,arm,cortex-a55-pmu0�äåæç› psci ,arm,psci-1.0#smctimer,arm,armv8-timer0�   ®xin24m ,fixed-clockÅn6Õxin24m(²xin32k ,fixed-clockÅ€Õxin32kèòdefault(sram@10f000 ,mmio-sramð ðsram@0,arm,scmi-shmem²sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@›œ�satapmaliverxoob �_ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€ ¡¢satapmaliverxoob �` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ �©¦§¥ref_clksuspend_clkbus_clkBhost Jutmi_wide4S”Zokay usb2-phys zhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ �ª©ª¨ref_clksuspend_clkbus_clkBhost usb2-phyusb3-phy Jutmi_wide4S•Zokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF � ˆ�®ýA¸(òusb@fd800000 ,generic-ehciý€ �‚½¾¼usbokayusb@fd840000 ,generic-ohciý„ �ƒ½¾¼usbokayusb@fd880000 ,generic-ehciýˆ �…¿À¼usbokayusb@fd8c0000 ,generic-ohciýŒ �†¿À¼usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý²_io-domains&,rockchip,rk3568-pmu-io-voltage-domainokayÒàîü &4Bsyscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsyscon²°syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƲ syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȲ±syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɲ²syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€²³syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€²¶clock-controller@fdd00000,rockchip,rk3568-pmucruýÐ(P²clock-controller@fdd20000,rockchip,rk3568-cruýÒxin24m(P] m€G†Œ ë‚™ ²i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ �.- i2cpclkè!òdefault okayregulator@1c ,tcs,tcs4525¦Ãvdd_cpuÒæø 5Œ0(ü="²regulator-state-memHpmic@20,rockchip,rk809 #�Õrk808-clkout1rk808-clkout2òdefaultè$%ay&…&‘&�&©&µ&Á&Í&Ù&å(²ÂregulatorsDCDC_REG1 Ãvdd_logicÒæóø¡ ™p(qregulator-state-memH » DCDC_REG2Ãvdd_gpuÒæóø¡ ™p(q²Eregulator-state-memH » DCDC_REG3Ãvcc_ddrÒæóregulator-state-mem&DCDC_REG4Ãvdd_npuóø¡ ™p(qregulator-state-memHDCDC_REG5Ãvcc_1v8Òæøw@w@²regulator-state-memHLDO_REG1Ãvdda0v9_imageø »  » ²[regulator-state-memHLDO_REG2 Ãvdda_0v9Òæø »  » regulator-state-memHLDO_REG3 Ãvdda0v9_pmuÒæø »  » regulator-state-mem& » LDO_REG4 Ãvccio_acodecÒæø2Z 2Z ²regulator-state-memHLDO_REG5 Ãvccio_sdøw@2Z ²regulator-state-memHLDO_REG6 Ãvcc3v3_pmuÒæø2Z 2Z ²regulator-state-mem& 2Z LDO_REG7 Ãvcca_1v8Òæøw@w@²£regulator-state-memHLDO_REG8 Ãvcca1v8_pmuÒæøw@w@²regulator-state-mem& w@LDO_REG9Ãvcca1v8_imageøw@w@²\regulator-state-memHSWITCH_REG1Ãvcc_3v3Òæ²regulator-state-memHSWITCH_REG2 Ãvcc3v3_sdregulator-state-memHeeprom@50,belling,bl24c16aatmel,24c16P>Gserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ �t ,baudclkapb_pclkR''è(òdefaultWd disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè)òdefaultn disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè*òdefaultn disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 pwmpclkè+òdefaultn disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0 0 pwmpclkè,òdefaultn disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllery ²power-domain@7�-ypower-domain@8ÌÍ �./0ypower-domain@9 ÚÛÜ �123ypower-domain@10 ñò�456789ypower-domain@11 í�:ypower-domain@13 �;ypower-domain@14 �<=>ypower-domain@15�?@ABCygpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$�()' ”jobmmugpugpubus *D4okay¤E² video-codec@fdea0400,rockchip,rk3568-vpuýê �‹”vdpuîï aclkhclk°F4 iommu@fdea0800,rockchip,rk3568-iommuýê@ �Š aclkifaceîï4 ·²Frga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ �ZóôõaclkhclksclkS&$% Äcoreaxiahb4 video-codec@fdee0000,rockchip,rk3568-vepuýî �@ýþ aclkhclk°G4 iommu@fdee0800,rockchip,rk3568-iommuýî@ �?ýþ aclkiface4 ·²Gmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ �d ÁÂŽ�biuciuciu-driveciu-sampleÐÛðÑ€SëÄreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ� ”macirqeth_wake_irq@†‰‰ÇÃĉÈWstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refSì Ästmmaceth™ éHù IJ0okay]‰† ‚‡K9inputFL Qrgmii-idZòdefaultèMNOPQRmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22eN u†  ‡S²Lstmmac-axi-config“�­²Hrx-queues-config½²Iqueue0tx-queues-configÓ²Jqueue0vop@fe040000 þ0þ@évopgamma-lut �”(ÝÞßàá%aclkhclkdclk_vp0dclk_vp1dclk_vp2°T4 ™ okay,rockchip,rk3566-vop]ßà‚ports ²port@0 endpoint@2óU²]port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? �”ÝÞ aclkiface·4 okay²Tdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �DpclkèdphyV4 ÄapbS™  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �EpclkédphyW4 ÄapbS™  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  �-(æç“(Úiahbisfrcecrefòdefault èXYZ4 W™ okay[$\²ports port@0endpointó]²Uport@1endpointó^²Àqos@fe128000,rockchip,rk3568-qossysconþ€ ²-qos@fe138080,rockchip,rk3568-qossysconþ€€ ²<qos@fe138100,rockchip,rk3568-qossysconþ� ²=qos@fe138180,rockchip,rk3568-qossysconþ�€ ²>qos@fe148000,rockchip,rk3568-qossysconþ€ ².qos@fe148080,rockchip,rk3568-qossysconþ€€ ²/qos@fe148100,rockchip,rk3568-qossysconþ� ²0qos@fe150000,rockchip,rk3568-qossysconþ ²:qos@fe158000,rockchip,rk3568-qossysconþ€ ²4qos@fe158100,rockchip,rk3568-qossysconþ� ²5qos@fe158180,rockchip,rk3568-qossysconþ�€ ²6qos@fe158200,rockchip,rk3568-qossysconþ‚ ²7qos@fe158280,rockchip,rk3568-qossysconþ‚€ ²8qos@fe158300,rockchip,rk3568-qossysconþƒ ²9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ²?qos@fe190280,rockchip,rk3568-qossysconþ€ ²@qos@fe190300,rockchip,rk3568-qossysconþ ²Aqos@fe190380,rockchip,rk3568-qossysconþ€ ²Bqos@fe190400,rockchip,rk3568-qossysconþ ²Cqos@fe198000,rockchip,rk3568-qossysconþ€ ²;qos@fe1a8000,rockchip,rk3568-qossysconþ€ ²1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ²2qos@fe1a8100,rockchip,rk3568-qossysconþ� ²3dfi@fe230000,rockchip,rk3568-dfiþ# � 4_pcie@fe260000,rockchip,rk3568-pcie0À@þ&ôédbiapbconfig<�KJIHG”syspmcmsglegacyerrA(�‚ƒ„…$aclk_mstaclk_slvaclk_dbipclkauxöpci�K`^````l}Œ›ª² pcie-phy4Tôôô ô à@S¡Äpipe okayòdefaultèa ‡b ¼clegacy-interrupt-controller�ˆ �H²`mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ �b °±Š‹biuciuciu-driveciu-sampleÐÛðÑ€SÔÄresetokayÌÖçòdefaultèdefgòÿ& mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ �c ²³Œ�biuciuciu-driveciu-sampleÐÛðÑ€SÖÄresetokayÌÖ  % ;h Fòdefault èijk Tÿ& spi@fe300000 ,rockchip,sfcþ0@ �exvclk_sfchclk_sfcèlòdefaultokay flash@0,jedec,spi-nor b2ê t …Gmmc@fe310000,rockchip,rk3568-dwcmshcþ1 �]{}m ëÂn6(|zy{}corebusaxiblocktimerokayÌÛ ë – Fòdefaultèmnopÿ rng@fe388000,rockchip,rk3568-rngþ8€@po coreahbSm disabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ �4]=AmFÏqFÏq?C9mclk_txmclk_rxhclkRq ¥txSPQ Ätx-mrx-m™ okay² i2s@fe410000,rockchip,rk3568-i2s-tdmþA �5]EImFÏqFÏqGK:mclk_txmclk_rxhclkRqq ¥rxtxSRS Ätx-mrx-m™ òdefaultèrstuokay ¯i2s@fe420000,rockchip,rk3568-i2s-tdmþB �6]MmFÏqOO;mclk_txmclk_rxhclkRqq ¥txrxSTÄtx-m™ òdefaultèvwxy disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC �7SW<mclk_txmclk_rxhclkRqq ¥txrxSUV Ätx-mrx-m™  disabledpdm@fe440000,rockchip,rk3568-pdmþD �LZYpdm_clkpdm_hclkRq  ¥rxèz{|}~òdefaultSXÄpdm-m disabledspdif@fe460000,rockchip,rk3568-spdifþF �f mclkhclk_\Rq ¥txòdefaultè€ disableddma-controller@fe530000,arm,pl330arm,primecellþS@�  Ê  apb_pclk á²'dma-controller@fe550000,arm,pl330arm,primecellþU@� Ê  apb_pclk á²qi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ �/HG i2cpclkè�òdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ �0JI i2cpclkè‚òdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ �1LK i2cpclkèƒòdefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] �2NM i2cpclkè„òdefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ �3PO i2cpclkè…òdefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` �• tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa �gRQspiclkapb_pclkR'' ¥txrxòdefault 膇ˆ  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb �hTSspiclkapb_pclkR'' ¥txrxòdefault 艊‹  disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc �iVUspiclkapb_pclkR'' ¥txrxòdefault èŒ�Ž  disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd �jXWspiclkapb_pclkR'' ¥txrxòdefault è��‘  disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe �ubaudclkapb_pclkR'' è’“”òdefaultWdokayserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf �v# baudclkapb_pclkR''è•òdefaultWdokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg �w'$baudclkapb_pclkR''è–òdefaultWd disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh �x+(baudclkapb_pclkR'' è—òdefaultWd disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi �y/,baudclkapb_pclkR' ' è˜òdefaultWd disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj �z30baudclkapb_pclkR' ' è™òdefaultWd disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk �{74baudclkapb_pclkR''èšòdefaultWd disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl �|;8baudclkapb_pclkR''è›òdefaultWd disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm �}?<baudclkapb_pclkR''èœòdefaultWd disabledthermal-zonescpu-thermal ìd è �tripscpu_alert0 p ,Ðýpassive²žcpu_alert1 $ø ,Ðýpassivecpu_crit s ,Ð ýcriticalcooling-mapsmap0 7ž0 < ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal ì è �tripsgpu-threshold p ,Ðýpassivegpu-target $ø ,Ðýpassive²Ÿgpu-crit s ,Ð ýcriticalcooling-mapsmap0 7Ÿ < ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq �s]mf@ ®`tsadcapb_pclkS�‚×™  Ksòdefaultsleepè¡ b¢ lokay ‚ ™²�saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr �]saradcapb_pclkS€ Äsaradc-apb ´okay Æ£pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¤òdefaultn disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¥òdefaultn disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY pwmpclkè¦òdefaultn disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0ZY pwmpclkè§òdefaultn disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè¨òdefaultn disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè©òdefaultn disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ pwmpclkèªòdefaultn disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0]\ pwmpclkè«òdefaultn disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè¬òdefaultn disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè­òdefaultn disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ pwmpclkè®òdefaultn disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0`_ pwmpclkè¯òdefaultn disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ"} refapbpipe]"mõáSÇÄphy Ò° ä± úokay²phy@fe840000,rockchip,rk3568-naneng-combphyþ„%~ refapbpipe]%mõáSÉÄphy Ò° ä² úokay²phy@fe870000,rockchip,rk3568-csi-dphyþ‡ypclk úSºÄapb™  disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… refpclkz ú4 ÄapbS» disabled²Vmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† refpclk{ ú4 ÄapbS¼ disabled²Wusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠphyclkÕclk_usbphy0_480m �‡ ³(okay²host-port úokayZ´²otg-port úokayZµ²usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹phyclkÕclk_usbphy1_480m �ˆ ¶(okayhost-port úokayZ´²otg-port úokayZ´²pinctrl,rockchip,rk3568-pinctrl™ 4_ ²·gpio@fdd60000,rockchip,gpio-bankýÖ �!.   %·  1ˆ�²#gpio@fe740000,rockchip,gpio-bankþt �"cd  %·  1ˆ�²bgpio@fe750000,rockchip,gpio-bankþu �#ef  %·@  1ˆ�gpio@fe760000,rockchip,gpio-bankþv �$gh  %·`  1ˆ�²Sgpio@fe770000,rockchip,gpio-bankþw �%ij  %·€  1ˆ�pcfg-pull-up =²ºpcfg-pull-none J²¸pcfg-pull-none-drv-level-1 J W²¼pcfg-pull-none-drv-level-2 J W²»pcfg-pull-none-drv-level-3 J W²¿pcfg-pull-up-drv-level-1 = W²¾pcfg-pull-up-drv-level-2 = W²¹pcfg-pull-none-smt J f²½acodecaudiopwmbt656bt1120camvcc_cam_en {¸²Ècan0can1can2cifclk32kclk32k-out0 {¸²cpuebcedpdpemmcemmc-bus8€ { ¹ ¹¹¹¹¹¹¹²memmc-clk {¹²nemmc-cmd {¹²oemmc-datastrobe {¸²peth0eth1flashfspifspi-pins` {¸¸¸¸¸¸²lgmac0gmac1gmac1m1-miim {¸¸²Mgmac1m1-clkinout {¸²Rgmac1m1-rx-bus20 {¸¸ ¸²Ogmac1m1-tx-bus20 {»»¸²Ngmac1m1-rgmii-clk {¸¼²Pgmac1m1-rgmii-bus@ {¸¸»»²Qgpuhdmitxhdmitxm0-cec {¸²Zhdmitx-scl {¸²Xhdmitx-sda {¸²Yi2c0i2c0-xfer { ½ ½²!i2c1i2c1-xfer { ½ ½²�i2c2i2c2m0-xfer { ½½²‚i2c3i2c3m0-xfer {½½²ƒi2c4i2c4m0-xfer { ½ ½²„i2c5i2c5m0-xfer { ½ ½²…i2s1i2s1m0-lrcktx {¸²si2s1m0-mclk {¸²%i2s1m0-sclktx {¸²ri2s1m0-sdi0 { ¸²ti2s1m0-sdo0 {¸²ui2s2i2s2m0-lrcktx {¸²wi2s2m0-sclktx {¸²vi2s2m0-sdi {¸²xi2s2m0-sdo {¸²yi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk {¸²zpdmm0-clk1 {¸²{pdmm0-sdi0 { ¸²|pdmm0-sdi1 { ¸²}pdmm0-sdi2 { ¸²~pdmm0-sdi3 {¸²pmicpmic-int-l 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-suspend-microvoltregulator-on-in-suspendpagesizevcc-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr50vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104spi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathfunctioncolorlinux,default-triggerpost-power-on-delay-mspower-off-delay-usenable-active-highgpio