Ð þíÜÞ8Ѐ( ^ÐH =,xunlong,orangepi-3b-v2.1xunlong,orangepi-3brockchip,rk35667Xunlong Orange Pi 3B v2.1aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe310000ì/mmc@fe2b0000ñ/mmc@fe2c0000cpus cpu@0öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@100öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@200öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@300öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² l3-cache,cacheºÆ@M@_²opp-table-0,operating-points-v2Ô²opp-408000000ßQ– æ »  » Œ0ôœ@opp-600000000ß#ÃF æ »  » Œ0opp-816000000ß0£, æ »  » Œ0opp-1104000000ßAÍ´ æ »  » Œ0opp-1416000000ßTfr æ »  » Œ0opp-1608000000ß_Ø" æà˜à˜Œ0opp-1800000000ßkIÒ æ��Œ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc‚" protocol@14(²opp-table-1,operating-points-v2²Copp-200000000ß ëÂ æ øP øPB@opp-300000000ßá£ æ øP øPB@opp-400000000ßׄ æ øP øPB@opp-600000000ß#ÃF æ »  » B@opp-700000000ß)¹' æ~ð~ðB@opp-800000000ß/¯ æB@B@B@hdmi-sound,simple-audio-card5HDMILi2seokaysimple-audio-card,codec†simple-audio-card,cpu† pmu,arm,cortex-a55-pmu0�äåæç› psci ,arm,psci-1.0#smctimer,arm,armv8-timer0�   ®xin24m ,fixed-clockÅn6Õxin24m(²xin32k ,fixed-clockÅ€Õxin32kèòdefault(sram@10f000 ,mmio-sramð ðsram@0,arm,scmi-shmem²sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@›œ�satapmaliverxoob �_ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€ ¡¢satapmaliverxoob �` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ �©¦§¥ref_clksuspend_clkbus_clkBhost Jutmi_wide4S”Zokay usb2-phys zhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ �ª©ª¨ref_clksuspend_clkbus_clkBhost usb2-phyusb3-phy Jutmi_wide4S•Zokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF � ˆ�®ýA¸(òusb@fd800000 ,generic-ehciý€ �‚½¾¼usbokayusb@fd840000 ,generic-ohciý„ �ƒ½¾¼usbokayusb@fd880000 ,generic-ehciýˆ �…¿À¼usbokayusb@fd8c0000 ,generic-ohciýŒ �†¿À¼usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý²]io-domains&,rockchip,rk3568-pmu-io-voltage-domainokayÒàîü &4Bsyscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsyscon²´syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƲ syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȲµsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɲ¶syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€²·syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€²ºclock-controller@fdd00000,rockchip,rk3568-pmucruýÐ(P²clock-controller@fdd20000,rockchip,rk3568-cruýÒxin24m(P] m€G†Œ ë‚™ ²i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ �.- i2cpclkè!òdefault okaypmic@20,rockchip,rk809 ]H‚–(HmclkÕrk809-clkout1rk809-clkout2"�òdefaultè#$¦·ÏÝ%é%õ%% %%%%1%=%²”regulatorsDCDC_REG1 Ivdd_logicXl~•¡ ­™pÅqregulator-state-memÚDCDC_REG2Ivdd_gpuXl~•¡ ­™pÅq²Dregulator-state-memÚDCDC_REG3Ivcc_ddrXl~regulator-state-memóDCDC_REG4Ivdd_npu~•¡ ­™pÅqregulator-state-memÚDCDC_REG5Ivcc_1v8Xl•w@­w@²regulator-state-memÚLDO_REG1Ivdda0v9_image• » ­ » ²Yregulator-state-memÚLDO_REG2 Ivdda_0v9Xl• » ­ » regulator-state-memÚLDO_REG3 Ivdda0v9_pmuXl• » ­ » regulator-state-memó » LDO_REG4 Ivccio_acodecXl•2Z ­2Z ²regulator-state-memÚLDO_REG5 Ivccio_sdXl•w@­2Z ²regulator-state-memÚLDO_REG6 Ivcc3v3_pmuXl•2Z ­2Z ²regulator-state-memó 2Z LDO_REG7 Ivcca_1v8Xl•w@­w@²§regulator-state-memÚLDO_REG8 Ivcca1v8_pmuXl•w@­w@regulator-state-memó w@LDO_REG9Ivcca1v8_image•w@­w@²Zregulator-state-memÚSWITCH_REG1Ivcc_3v3Xl²regulator-state-memÚSWITCH_REG2 Ivcc3v3_sdXl²eregulator-state-memÚregulator@40,silergy,syr827@'Ivdd_cpuXl• ª0­O€ÅüD%²regulator-state-memÚserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ �t ,baudclkapb_pclkO&&è'òdefaultTa disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè(òdefaultk disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè)òdefaultk disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 pwmpclkè*òdefaultk disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0 0 pwmpclkè+òdefaultk disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerv ²power-domain@7Š,vpower-domain@8ÌÍ Š-./vpower-domain@9 ÚÛÜ Š012vpower-domain@10 ñòŠ345678vpower-domain@11 íŠ9vpower-domain@13 Š:vpower-domain@14 Š;<=vpower-domain@15Š>?@ABvgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$�()' ‘jobmmugpugpubus *C4okay¡D²¤video-codec@fdea0400,rockchip,rk3568-vpuýê �‹‘vdpuîï aclkhclk­E4 iommu@fdea0800,rockchip,rk3568-iommuýê@ �Š aclkifaceîï4 ´²Erga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ �ZóôõaclkhclksclkS&$% Ácoreaxiahb4 video-codec@fdee0000,rockchip,rk3568-vepuýî �@ýþ aclkhclk­F4 iommu@fdee0800,rockchip,rk3568-iommuýî@ �?ýþ aclkiface4 ´²Fmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ �d ÁÂŽ�biuciuciu-driveciu-sampleÍØðÑ€SëÁreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ� ‘macirqeth_wake_irq@†‰‰ÇÃĉÈWstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refSì Ástmmaceth™ æGöHI-okay]‰†‚‡Å6input Crgmii-idLòdefaultèJKLMNOWPmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22bN rÃP „Q²Pstmmac-axi-config�šª²Grx-queues-configº²Hqueue0tx-queues-configвIqueue0vop@fe040000 þ0þ@ævopgamma-lut �”(ÝÞßàá%aclkhclkdclk_vp0dclk_vp1dclk_vp2­R4 ™ okay,rockchip,rk3566-vop]ßà‚ports ²port@0 endpoint@2ðS²[port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? �”ÝÞ aclkiface´4 okay²Rdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �DpclkèdphyT4 ÁapbS™  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �EpclkédphyU4 ÁapbS™  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  �-(æç“(Úiahbisfrcecrefòdefault èVWX4 T™ ¦okayYZ²ports port@0endpointð[²Sport@1endpointð\²Åqos@fe128000,rockchip,rk3568-qossysconþ€ ²,qos@fe138080,rockchip,rk3568-qossysconþ€€ ²;qos@fe138100,rockchip,rk3568-qossysconþ� ²<qos@fe138180,rockchip,rk3568-qossysconþ�€ ²=qos@fe148000,rockchip,rk3568-qossysconþ€ ²-qos@fe148080,rockchip,rk3568-qossysconþ€€ ².qos@fe148100,rockchip,rk3568-qossysconþ� ²/qos@fe150000,rockchip,rk3568-qossysconþ ²9qos@fe158000,rockchip,rk3568-qossysconþ€ ²3qos@fe158100,rockchip,rk3568-qossysconþ� ²4qos@fe158180,rockchip,rk3568-qossysconþ�€ ²5qos@fe158200,rockchip,rk3568-qossysconþ‚ ²6qos@fe158280,rockchip,rk3568-qossysconþ‚€ ²7qos@fe158300,rockchip,rk3568-qossysconþƒ ²8qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ²>qos@fe190280,rockchip,rk3568-qossysconþ€ ²?qos@fe190300,rockchip,rk3568-qossysconþ ²@qos@fe190380,rockchip,rk3568-qossysconþ€ ²Aqos@fe190400,rockchip,rk3568-qossysconþ ²Bqos@fe198000,rockchip,rk3568-qossysconþ€ ²:qos@fe1a8000,rockchip,rk3568-qossysconþ€ ²0qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ²1qos@fe1a8100,rockchip,rk3568-qossysconþ� ²2dfi@fe230000,rockchip,rk3568-dfiþ# �  ]pcie@fe260000,rockchip,rk3568-pcie0À@þ&ôædbiapbconfig<�KJIHG‘syspmcmsglegacyerr-(�‚ƒ„…$aclk_mstaclk_slvaclk_dbipclkauxöpci�7`J^^^^Xix‡–ž pcie-phy4Tôôô ô à@S¡Ápipe okayòdefaultè_ „"¨`legacy-interrupt-controller�ˆ �H²^mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ �b °±Š‹biuciuciu-driveciu-sampleÍØðÑ€SÔÁresetokay¸ÂÓòdefaultèabcdÞeêmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ �c ²³Œ�biuciuciu-driveciu-sampleÍØðÑ€SÖÁresetokay¸Â÷  f % , 2òdefault èghi @Þê wifi@1%,brcm,bcm43456-fmacbrcm,bcm4329-fmac"� ‘host-wakeòdefaultèjspi@fe300000 ,rockchip,sfcþ0@ �exvclk_sfchclk_sfcèkòdefaultokay flash@0,jedec,spi-nor N2ê ` qmmc@fe310000,rockchip,rk3568-dwcmshcþ1 �]{}m ëÂn6(|zy{}corebusaxiblocktimerokay¸ ‚Ø ë ” 2òdefaultèlmnoÞêrng@fe388000,rockchip,rk3568-rngþ8€@po coreahbSm disabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ �4]=AmFÏqFÏq?C9mclk_txmclk_rxhclkOp £txSPQ Átx-mrx-m™ ¦okay² i2s@fe410000,rockchip,rk3568-i2s-tdmþA �5]EImFÏqFÏqGK:mclk_txmclk_rxhclkOpp £rxtxSRS Átx-mrx-m™ òdefaultèqrst¦okay ­²Ìi2s@fe420000,rockchip,rk3568-i2s-tdmþB �6]MmFÏqOO;mclk_txmclk_rxhclkOpp £txrxSTÁtx-m™ òdefaultèuvwx¦ disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC �7SW<mclk_txmclk_rxhclkOpp £txrxSUV Átx-mrx-m™ ¦ disabledpdm@fe440000,rockchip,rk3568-pdmþD �LZYpdm_clkpdm_hclkOp  £rxèyz{|}~òdefaultSXÁpdm-m¦ disabledspdif@fe460000,rockchip,rk3568-spdifþF �f mclkhclk_\Op £txòdefaultè¦ disableddma-controller@fe530000,arm,pl330arm,primecellþS@�  È  apb_pclk ß²&dma-controller@fe550000,arm,pl330arm,primecellþU@� È  apb_pclk ß²pi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ �/HG i2cpclkè€òdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ �0JI i2cpclkè�òdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ �1LK i2cpclkè‚òdefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] �2NM i2cpclkèƒòdefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ �3PO i2cpclkè„òdefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` �• tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa �gRQspiclkapb_pclkO&& £txrxòdefault è…†‡  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb �hTSspiclkapb_pclkO&& £txrxòdefault 舉Š  disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc �iVUspiclkapb_pclkO&& £txrxòdefault 苌�  disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd �jXWspiclkapb_pclkO&& £txrxòdefault èŽ��  disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe �ubaudclkapb_pclkO&& è‘’“òdefaultTaokay êbluetooth,brcm,bcm4345c5”lpo•� ‘host-wakeup ú• •òdefault è–—˜  )serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf �v# baudclkapb_pclkO&&è™òdefaultTaokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg �w'$baudclkapb_pclkO&&èšòdefaultTa disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh �x+(baudclkapb_pclkO&& è›òdefaultTa disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi �y/,baudclkapb_pclkO& & èœòdefaultTa disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj �z30baudclkapb_pclkO& & è�òdefaultTa disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk �{74baudclkapb_pclkO&&èžòdefaultTa disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl �|;8baudclkapb_pclkO&&èŸòdefaultTa disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm �}?<baudclkapb_pclkO&&è òdefaultTa disabledthermal-zonescpu-thermal 6d Lè Z¡tripscpu_alert0 jp vÐýpassive²¢cpu_alert1 j$ø vÐýpassivecpu_crit js vÐ ýcriticalcooling-mapsmap0 �¢0 † ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal 6 Lè Z¡tripsgpu-threshold jp vÐýpassivegpu-target j$ø vÐýpassive²£gpu-crit js vÐ ýcriticalcooling-mapsmap0 �£ †¤ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq �s]mf@ ®`tsadcapb_pclkS�‚×™  •sòdefaultsleepè¥ ¬¦ ¶okay Ì ã²¡saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr �]saradcapb_pclkS€ Ásaradc-apb þokay §pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¨òdefaultk disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè©òdefaultk disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY pwmpclkèªòdefaultk disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0ZY pwmpclkè«òdefaultk disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè¬òdefaultk disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè­òdefaultk disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ pwmpclkè®òdefaultk disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0]\ pwmpclkè¯òdefaultk disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè°òdefaultk disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè±òdefaultk disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ pwmpclkè²òdefaultk disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0`_ pwmpclkè³òdefaultk disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ"} refapbpipe]"mõáSÇÁphy ´ .µ Dokay²phy@fe840000,rockchip,rk3568-naneng-combphyþ„%~ refapbpipe]%mõáSÉÁphy ´ .¶ Dokay²phy@fe870000,rockchip,rk3568-csi-dphyþ‡ypclk DSºÁapb™  disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… refpclkz D4 ÁapbS» disabled²Tmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† refpclk{ D4 ÁapbS¼ disabled²Uusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠphyclkÕclk_usbphy0_480m �‡ O·(okay²host-port DokayL¸²otg-port DokayL¹²usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹phyclkÕclk_usbphy1_480m �ˆ Oº(okayhost-port DokayL¸²otg-port DokayL¸²pinctrl,rockchip,rk3568-pinctrl™  ] ²»gpio@fdd60000,rockchip,gpio-bankýÖ �!.  _ o»  {ˆ�²"gpio@fe740000,rockchip,gpio-bankþt �"cd _ o»  {ˆ�gpio@fe750000,rockchip,gpio-bankþu �#ef _ o»@  {ˆ�²•gpio@fe760000,rockchip,gpio-bankþv �$gh _ o»`  {ˆ�gpio@fe770000,rockchip,gpio-bankþw �%ij _ o»€  {ˆ�²Qpcfg-pull-up ‡²¾pcfg-pull-down ”²Äpcfg-pull-none £²¼pcfg-pull-none-drv-level-1 £ °²Àpcfg-pull-none-drv-level-2 £ °²¿pcfg-pull-none-drv-level-3 £ °²Ãpcfg-pull-up-drv-level-1 ‡ °²Âpcfg-pull-up-drv-level-2 ‡ °²½pcfg-pull-none-smt £ ¿²Áacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 Ô¼²cpuebcedpdpemmcemmc-bus8€ Ô ½ ½½½½½½½²lemmc-clk Ô½²memmc-cmd Ô½²nemmc-datastrobe Ô¼²oeth0eth1flashfspifspi-pins` Ô¼¼¼¼¼¼²kgmac0gmac1gmac1m0-miim Ô¼¼²Jgmac1m0-clkinout Ô¼²Ogmac1m0-rx-bus20 Ô ¼ ¼ ¼²Lgmac1m0-tx-bus20 Ô ¿¿¼²Kgmac1m0-rgmii-clk Ô¼À²Mgmac1m0-rgmii-bus@ Ô¼¼¿¿²Ngpuhdmitxhdmitxm0-cec Ô¼²Xhdmitx-scl Ô¼²Vhdmitx-sda Ô¼²Wi2c0i2c0-xfer Ô Á Á²!i2c1i2c1-xfer Ô Á Á²€i2c2i2c2m0-xfer Ô ÁÁ²�i2c3i2c3m0-xfer ÔÁÁ²‚i2c4i2c4m0-xfer Ô Á Á²ƒi2c5i2c5m0-xfer Ô Á Á²„i2s1i2s1m0-lrcktx Ô¼²ri2s1m0-mclk Ô¼²$i2s1m0-sclktx Ô¼²qi2s1m0-sdi0 Ô ¼²si2s1m0-sdo0 Ô¼²ti2s2i2s2m0-lrcktx Ô¼²vi2s2m0-sclktx Ô¼²ui2s2m0-sdi Ô¼²wi2s2m0-sdo Ô¼²xi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Ô¼²ypdmm0-clk1 Ô¼²zpdmm0-sdi0 Ô ¼²{pdmm0-sdi1 Ô ¼²|pdmm0-sdi2 Ô ¼²}pdmm0-sdi3 Ô¼²~pmicpmic-int-l Ô¾²#pmupwm0pwm0m0-pins Ô¼²(pwm1pwm1m0-pins Ô¼²)pwm2pwm2m0-pins Ô¼²*pwm3pwm3-pins Ô¼²+pwm4pwm4-pins Ô¼²¨pwm5pwm5-pins Ô¼²©pwm6pwm6-pins Ô¼²ªpwm7pwm7-pins Ô¼²«pwm8pwm8m0-pins Ô ¼²¬pwm9pwm9m0-pins Ô ¼²­pwm10pwm10m0-pins Ô ¼²®pwm11pwm11m0-pins Ô¼²¯pwm12pwm12m0-pins Ô¼²°pwm13pwm13m0-pins Ô¼²±pwm14pwm14m0-pins Ô¼²²pwm15pwm15m0-pins Ô¼²³refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ Ô½½½½²asdmmc0-clk Ô½²bsdmmc0-cmd Ô½²csdmmc0-det Ô¾²dsdmmc1sdmmc1-bus4@ Ô½½½½²gsdmmc1-clk Ô½²hsdmmc1-cmd Ô½²isdmmc2spdifspdifm0-tx Ô¼²spi0spi0m0-pins0 Ô ¼¼¼²‡spi0m0-cs0 Ô¼²…spi0m0-cs1 Ô¼²†spi1spi1m0-pins0 Ô ¼¼¼²Šspi1m0-cs0 Ô¼²ˆspi1m0-cs1 Ô¼²‰spi2spi2m0-pins0 Ô¼¼¼²�spi2m0-cs0 Ô¼²‹spi2m0-cs1 Ô¼²Œspi3spi3m0-pins0 Ô ¼¼ ¼²�spi3m0-cs0 Ô¼²Žspi3m0-cs1 Ô¼²�tsadctsadc-shutorg Ô¼²¥tsadc-pin Ô¼²¦uart0uart0-xfer Ô¾¾²'uart1uart1m0-xfer Ô ¾ ¾²‘uart1m0-ctsn Ô¼²’uart1m0-rtsn Ô ¼²“uart2uart2m0-xfer Ô¾¾²™uart3uart3m0-xfer Ô¾¾²šuart4uart4m0-xfer Ô¾¾²›uart5uart5m0-xfer Ô¾¾²œuart6uart6m0-xfer Ô¾¾²�uart7uart7m0-xfer Ô¾¾²žuart8uart8m0-xfer Ô¾¾²Ÿuart9uart9m0-xfer Ô¾¾² vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2bluetoothbt-reg-on-h Ô¼²–bt-wake-host-h ÔIJ—host-wake-bt-h Ô¼²˜ledswork-led Ô¼²Æpciepcie20-pins0 Ô¼¼ ¼²_pcie20-pwren Ô¼²Çusbusb-host-pwren-h Ô¼²Éusb-otg-pwren-h Ô¼²Êwifiwifi-reg-on-h Ô¼²Ëwifi-wake-host-h ÔIJjchosen âserial2:1500000n8hdmi-con,hdmi-connectorýaportendpointðŲ\leds ,gpio-ledsòdefaultèÆled-0 î ôon heartbeat Š" heartbeatregulator-3v3-vcc-pcie30,regulator-fixed ! Š"òdefaultèÇIvcc3v3_pcie30•2Z ­2Z D%²`regulator-3v3-vcc-sys,regulator-fixed Ivcc3v3_sysXl•2Z ­2Z DȲ%regulator-5v0-vcc-sys,regulator-fixed Ivcc5v0_sysXl•LK@­LK@²Èregulator-5v0-vcc-usb-host,regulator-fixed ! Š"òdefaultèÉIvcc5v0_usb_host•LK@­LK@DȲ¸regulator-5v0-vcc-usb-otg,regulator-fixed ! Š"òdefaultèÊIvcc5v0_usb_otg•LK@­LK@DȲ¹sdio-pwrseq,mmc-pwrseq-simple” ext_clockòdefaultèË 4È KLK@ „"²fsound,simple-audio-cardLi2s 5Analog RK809esimple-audio-card,cpu†Ìsimple-audio-card,codec†”regulator-1v8-vccio-phy,regulator-fixed Ivccio_phy1Xl­w@•w@² interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio6-supplyvccio7-supplyvccio5-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-supplyphy-handlereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplybus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr104spi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthcap-mmc-highspeedmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathcolordefault-statefunctionlinux,default-triggerenable-active-highpost-power-on-delay-mspower-off-delay-us