Ð þíÙ$8̨( |Ìp ",lckfb,tspi-rk3566rockchip,rk35667LCKFB Taishan Pi RK3566aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/mmc@fe2b0000â/mmc@fe310000ç/mmc@fe2c0000cpus cpu@0ìcpu,arm,cortex-a55øüpsci 4€A@S€`€m@€Œ�¨ cpu@100ìcpu,arm,cortex-a55øpsci 4€A@S€`€m@€Œ�¨ cpu@200ìcpu,arm,cortex-a55øpsci 4€A@S€`€m@€Œ�¨ cpu@300ìcpu,arm,cortex-a55øpsci 4€A@S€`€m@€Œ�¨ l3-cache,cache°¼6C@U¨opp-table-0,operating-points-v2ʨopp-408000000ÕQ– Ü »  » Œ0êœ@opp-600000000Õ#ÃF Ü »  » Œ0opp-816000000Õ0£, Ü »  » Œ0ûopp-1104000000ÕAÍ´ Ü »  » Œ0opp-1416000000ÕTfr Ü »  » Œ0opp-1608000000Õ_Ø" Üà˜à˜Œ0opp-1800000000ÕkIÒ Ü��Œ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc ‚ protocol@14ø¨opp-table-1,operating-points-v2¨Copp-200000000Õ ëÂ Ü øP øPB@opp-300000000Õá£ Ü øP øPB@opp-400000000Õׄ Ü øP øPB@opp-600000000Õ#ÃF Ü »  » B@opp-700000000Õ)¹' Ü~ð~ðB@opp-800000000Õ/¯ ÜB@B@B@hdmi-sound,simple-audio-card+HDMIBi2s[uokaysimple-audio-card,codec|simple-audio-card,cpu| pmu,arm,cortex-a55-pmu0†äåæç‘ psci ,arm,psci-1.0smctimer,arm,armv8-timer0†   ¤xin24m ,fixed-clock»n6Ëxin24m¨xin32k ,fixed-clock»€Ëxin32kÞèdefaultsram@10f000 ,mmio-sramøð öðsram@0,arm,scmi-shmemø¨sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciøü@ü›œ�ýsatapmaliverxoob †_  sata-phy* udisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciøü€ü ¡¢ýsatapmaliverxoob †`  sata-phy* udisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3øüÀ@ †©ü¦§¥ýref_clksuspend_clkbus_clk8otg @utmi_wide*I”Puokay  usb2-phyi phigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3øý@ †ªü©ª¨ýref_clksuspend_clkbus_clk8host  usb2-phyusb3-phy @utmi_wide*I•Puokayinterrupt-controller@fd400000 ,arm,gic-v3 øý@ýF † ~“¤ýA®(¹¨usb@fd800000 ,generic-ehciøý€ †‚ü½¾¼ usbuokayusb@fd840000 ,generic-ohciøý„ †ƒü½¾¼ usbuokayusb@fd880000 ,generic-ehciøýˆ †…ü¿À¼ usbuokayusb@fd8c0000 ,generic-ohciøýŒ ††ü¿À¼ usbuokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdøý¨Uio-domains&,rockchip,rk3568-pmu-io-voltage-domainuokayÈÖäò*8reboot-mode,syscon-reboot-modeFMRBÃYRBÃeRBÃsRBà syscon@fdc50000øýÅ ,rockchip,rk3566-pipe-grfsyscon¨«syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdøýƨsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconøýȨ¬syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconøýɨ­syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconøýÊ€¨®syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconøýÊ€€¨¯clock-controller@fdd00000,rockchip,rk3568-pmucruøýЃ¨clock-controller@fdd20000,rockchip,rk3568-cruøýÒüýxin24mƒ�  €G†Œ ëµ̨i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cøýÔ †.ü- ýi2cpclkÞ èdefault uokayregulator@1c ,tcs,tcs4525øÙövdd_cpu+ 5CŒ0[üp!¨regulator-state-mem{pmic@20,rockchip,rk809ø �Hµ–Ërk808-clkout1rk808-clkout2ýmclküH"†èdefaultÞ#$”µÆÔ%à%ì%ø%%%%(%4%¨ŒregulatorsDCDC_REG1 övdd_logic+¡ C™p[q@regulator-state-mem{DCDC_REG2övdd_gpu+¡ C™p[q@¨Dregulator-state-mem{DCDC_REG3övcc_ddr@regulator-state-memWDCDC_REG4övdd_npu+¡ C™p[q@regulator-state-mem{LDO_REG1övdda0v9_image+ » C » ¨Qregulator-state-mem{LDO_REG2 övdda_0v9+ » C » regulator-state-mem{LDO_REG3 övdda0v9_pmu+ » C » regulator-state-memWo » LDO_REG4 övccio_acodec+2Z C2Z ¨regulator-state-mem{LDO_REG5 övccio_sd+w@C2Z ¨regulator-state-mem{LDO_REG6 övcc3v3_pmu+2Z C2Z ¨regulator-state-memWo2Z LDO_REG7 övcca_1v8+w@Cw@¨žregulator-state-mem{LDO_REG8 övcca1v8_pmu+w@Cw@regulator-state-memWow@LDO_REG9övcca1v8_image+w@Cw@¨Rregulator-state-mem{DCDC_REG5övcc_1v8+w@Cw@¨regulator-state-mem{SWITCH_REG1övcc_3v3¨regulator-state-mem{SWITCH_REG2 övcc3v3_sd¨[regulator-state-mem{codec‹serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartøýÕ †tü ,ýbaudclkapb_pclk¨&&Þ'èdefault­º udisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×ü 0 ýpwmpclkÞ(èdefaultÄ udisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×ü 0 ýpwmpclkÞ)èdefaultÄ udisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý× ü 0 ýpwmpclkÞ*èdefaultÄ udisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×0ü 0 ýpwmpclkÞ+èdefaultÄ udisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdøýÙpower-controller!,rockchip,rk3568-power-controllerÏ ¨power-domain@7øüã,Ïpower-domain@8øüÌÍ ã-./Ïpower-domain@9ø üÚÛÜ ã012Ïpower-domain@10ø üñòã345678Ïpower-domain@11ø üíã9Ïpower-domain@13üø ã:Ïpower-domain@14øü ã;<=Ïpower-domain@15øüã>?@ABÏgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostøýæ@$†()' êjobmmugpuüýgpubus C*uokayúD¨›video-codec@fdea0400,rockchip,rk3568-vpuøýê †‹êvdpuüîï ýaclkhclkE* iommu@fdea0800,rockchip,rk3568-iommuøýê@ †Š ýaclkifaceüîï*  ¨Erga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaøýë€ †ZüóôõýaclkhclksclkI&$% coreaxiahb* video-codec@fdee0000,rockchip,rk3568-vepuøýî †@üýþ ýaclkhclkF* iommu@fdee0800,rockchip,rk3568-iommuøýî@ †?üýþ ýaclkiface*  ¨Fmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ@ †d üÁÂŽ�ýbiuciuciu-driveciu-sample&1ðÑ€Iëreset udisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aøþ† êmacirqeth_wake_irq@ü†‰‰ÇÃĉÈWýstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refIì stmmacethÌ?GO`HsI† udisabledmdio,snps,dwmac-mdio stmmac-axi-config�™©¨Grx-queues-config¹¨Hqueue0tx-queues-configϨIqueue0vop@fe040000 øþ0þ@åvopgamma-lut †”(üÝÞßàá%ýaclkhclkdclk_vp0dclk_vp1dclk_vp2J* Ìuokay,rockchip,rk3566-vop�ßàµports ¨port@0ø endpoint@2øïK¨Sport@1ø port@2ø iommu@fe043e00,rockchip,rk3568-iommu øþ>þ? †”üÝÞ ýaclkiface * uokay¨Jdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ †Dýpclküèdphy L* apbIÌ udisabledports port@0øport@1ødsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ †Eýpclküédphy M* apbIÌ udisabledports port@0øport@1øhdmi@fe0a0000,rockchip,rk3568-dw-hdmiøþ  †-(üæç“(Úýiahbisfrcecrefèdefault ÞNOP* ­ÌµuokayÿQR¨ports port@0øendpointïS¨Kport@1øendpointïT¨¼qos@fe128000,rockchip,rk3568-qossysconøþ€ ¨,qos@fe138080,rockchip,rk3568-qossysconøþ€€ ¨;qos@fe138100,rockchip,rk3568-qossysconøþ� ¨<qos@fe138180,rockchip,rk3568-qossysconøþ�€ ¨=qos@fe148000,rockchip,rk3568-qossysconøþ€ ¨-qos@fe148080,rockchip,rk3568-qossysconøþ€€ ¨.qos@fe148100,rockchip,rk3568-qossysconøþ� ¨/qos@fe150000,rockchip,rk3568-qossysconøþ ¨9qos@fe158000,rockchip,rk3568-qossysconøþ€ ¨3qos@fe158100,rockchip,rk3568-qossysconøþ� ¨4qos@fe158180,rockchip,rk3568-qossysconøþ�€ ¨5qos@fe158200,rockchip,rk3568-qossysconøþ‚ ¨6qos@fe158280,rockchip,rk3568-qossysconøþ‚€ ¨7qos@fe158300,rockchip,rk3568-qossysconøþƒ ¨8qos@fe180000,rockchip,rk3568-qossysconøþ qos@fe190000,rockchip,rk3568-qossysconøþ ¨>qos@fe190280,rockchip,rk3568-qossysconøþ€ ¨?qos@fe190300,rockchip,rk3568-qossysconøþ ¨@qos@fe190380,rockchip,rk3568-qossysconøþ€ ¨Aqos@fe190400,rockchip,rk3568-qossysconøþ ¨Bqos@fe198000,rockchip,rk3568-qossysconøþ€ ¨:qos@fe1a8000,rockchip,rk3568-qossysconøþ€ ¨0qos@fe1a8080,rockchip,rk3568-qossysconøþ€€ ¨1qos@fe1a8100,rockchip,rk3568-qossysconøþ� ¨2dfi@fe230000,rockchip,rk3568-dfiøþ# † Upcie@fe260000,rockchip,rk3568-pcie0øÀ@þ&ôådbiapbconfig<†KJIHGêsyspmcmsglegacyerr,(ü�‚ƒ„…$ýaclk_mstaclk_slvaclk_dbipclkauxìpci“6`IVVVVWhw†•�  pcie-phy*Töôôô ô à@I¡pipe  udisabledlegacy-interrupt-controller“~ †H¨Vmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ+@ †b ü°±Š‹ýbiuciuciu-driveciu-sample&1ðÑ€IÔresetuokay§±ÃÔèdefaultÞWXYZßí[ùmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ,@ †c ü²³Œ�ýbiuciuciu-driveciu-sample&1ðÑ€IÖresetuokay§Ã Ô  )\ 4èdefault Þ]^_ßí%ù wifi@1,brcm,bcm4329-fmacø`†  êhost-wakeèdefaultÞaspi@fe300000 ,rockchip,sfcøþ0@ †eüxvýclk_sfchclk_sfcÞbèdefault udisabledmmc@fe310000,rockchip,rk3568-dwcmshcøþ1 †�{}  ëÂn6(ü|zy{}ýcorebusaxiblocktimeruokay§1 ë 4èdefaultÞcdefgíùrng@fe388000,rockchip,rk3568-rngøþ8€@üpo ýcoreahbIm udisabledi2s@fe400000,rockchip,rk3568-i2s-tdmøþ@ †4�=A FÏqFÏqü?C9ýmclk_txmclk_rxhclk¨h BtxIPQ tx-mrx-m̵uokay¨ i2s@fe410000,rockchip,rk3568-i2s-tdmøþA †5�EI FÏqFÏqüGK:ýmclk_txmclk_rxhclk¨hh BrxtxIRS tx-mrx-mÌèdefaultÞijklµuokay L¨Åi2s@fe420000,rockchip,rk3568-i2s-tdmøþB †6�M FÏqüOO;ýmclk_txmclk_rxhclk¨hh BtxrxITtx-mÌèdefaultÞmnopµuokay Li2s@fe430000,rockchip,rk3568-i2s-tdmøþC †7üSW<ýmclk_txmclk_rxhclk¨hh BtxrxIUV tx-mrx-m̵ udisabledpdm@fe440000,rockchip,rk3568-pdmøþD †LüZYýpdm_clkpdm_hclk¨h  BrxÞqrstuvèdefaultIXpdm-mµ udisabledspdif@fe460000,rockchip,rk3568-spdiføþF †f ýmclkhclkü_\¨h BtxèdefaultÞwµ udisableddma-controller@fe530000,arm,pl330arm,primecelløþS@†  gü  ýapb_pclk ~¨&dma-controller@fe550000,arm,pl330arm,primecelløþU@† gü  ýapb_pclk ~¨hi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþZ †/üHG ýi2cpclkÞxèdefault uokayi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ[ †0üJI ýi2cpclkÞyèdefault  udisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ\ †1üLK ýi2cpclkÞzèdefault  udisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ] †2üNM ýi2cpclkÞ{èdefault uokayi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ^ †3üPO ýi2cpclkÞ|èdefault  udisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtøþ` †•ü ýtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiøþa †güRQýspiclkapb_pclk¨&& Btxrxèdefault Þ}~  udisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiøþb †hüTSýspiclkapb_pclk¨&& Btxrxèdefault Þ€�‚  udisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiøþc †iüVUýspiclkapb_pclk¨&& Btxrxèdefault Þƒ„…  udisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiøþd †jüXWýspiclkapb_pclk¨&& Btxrxèdefault Þ†‡ˆ  udisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartøþe †uüýbaudclkapb_pclk¨&& Þ‰Š‹èdefault­ºuokay ‰bluetooth,brcm,bcm43430a1-btüŒýlpo ™ã`èdefault Þ�Ž� £` ²% ¾serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartøþf †vü# ýbaudclkapb_pclk¨&&Þ�èdefault­ºuokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartøþg †wü'$ýbaudclkapb_pclk¨&&Þ‘èdefault­º udisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartøþh †xü+(ýbaudclkapb_pclk¨&& Þ’èdefault­º udisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartøþi †yü/,ýbaudclkapb_pclk¨& & Þ“èdefault­º udisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþj †zü30ýbaudclkapb_pclk¨& & Þ”èdefault­º udisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþk †{ü74ýbaudclkapb_pclk¨&&Þ•èdefault­º udisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþl †|ü;8ýbaudclkapb_pclk¨&&Þ–èdefault­º udisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþm †}ü?<ýbaudclkapb_pclk¨&&Þ—èdefault­º udisabledthermal-zonescpu-thermal Ëd áè ï˜tripscpu_alert0 ÿp Ðópassive¨™cpu_alert1 ÿ$ø Ðópassivecpu_crit ÿs Ð ócriticalcooling-mapsmap0 ™0  ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal Ë áè ï˜tripsgpu-threshold ÿp Ðópassivegpu-target ÿ$ø Ðópassive¨šgpu-crit ÿs Ð ócriticalcooling-mapsmap0 š ›ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcøþq †s� f@ ®`üýtsadcapb_pclkI�‚×Ì *sèdefaultsleepÞœ A� Kuokay a x¨˜saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcøþr †]üýsaradcapb_pclkI€ saradc-apb “uokay ¥ž¨»pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY ýpwmpclkÞŸèdefaultÄ udisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY ýpwmpclkÞ èdefaultÄ udisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn üZY ýpwmpclkÞ¡èdefaultÄ udisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn0üZY ýpwmpclkÞ¢èdefaultÄ udisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ ýpwmpclkÞ£èdefaultÄ udisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ ýpwmpclkÞ¤èdefaultÄ udisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo ü]\ ýpwmpclkÞ¥èdefaultÄ udisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo0ü]\ ýpwmpclkÞ¦èdefaultÄ udisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ ýpwmpclkÞ§èdefaultÄ udisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ ýpwmpclkÞ¨èdefaultÄ udisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp ü`_ ýpwmpclkÞ©èdefaultÄ udisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp0ü`_ ýpwmpclkÞªèdefaultÄ udisabledphy@fe830000,rockchip,rk3568-naneng-combphyøþƒü"} ýrefapbpipe�" õáIÇphy ±« ì Ùuokay¨phy@fe840000,rockchip,rk3568-naneng-combphyøþ„ü%~ ýrefapbpipe�% õáIÉphy ±« í Ùuokay¨phy@fe870000,rockchip,rk3568-csi-dphyøþ‡üyýpclk ÙIºapbÌ udisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyøþ… ýrefpclküz Ù* apbI» udisabled¨Lmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyøþ† ýrefpclkü{ Ù* apbI¼ udisabled¨Musb2phy@fe8a0000,rockchip,rk3568-usb2phyøþŠüýphyclkËclk_usbphy0_480m †‡ ä®uokay¨host-port Ùuokay ô!¨otg-port Ùuokay ô!¨usb2phy@fe8b0000,rockchip,rk3568-usb2phyøþ‹üýphyclkËclk_usbphy1_480m †ˆ ä¯uokayhost-port Ùuokay ô°¨otg-port Ùuokay ô°¨pinctrl,rockchip,rk3568-pinctrlÌU ö¨±gpio@fdd60000,rockchip,gpio-bankøýÖ †!ü.  ÿ ±  ~“¨"gpio@fe740000,rockchip,gpio-bankøþt †"ücd ÿ ±  ~“¨½gpio@fe750000,rockchip,gpio-bankøþu †#üef ÿ ±@  ~“¨`gpio@fe760000,rockchip,gpio-bankøþv †$ügh ÿ ±`  ~“gpio@fe770000,rockchip,gpio-bankøþw †%üij ÿ ±€  ~“¨Âpcfg-pull-up '¨´pcfg-pull-down 4¨ºpcfg-pull-none C¨²pcfg-pull-none-drv-level-1 C P¨¶pcfg-pull-none-drv-level-2 C P¨µpcfg-pull-none-drv-level-3 C P¨¹pcfg-pull-up-drv-level-1 ' P¨¸pcfg-pull-up-drv-level-2 ' P¨³pcfg-pull-none-smt C _¨·acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 t²¨cpuebcedpdpemmcemmc-rstnout t²¨gemmc-bus8€ t ³ ³³³³³³³¨cemmc-clk t³¨demmc-cmd t³¨eemmc-datastrobe t²¨feth0eth1flashfspifspi-pins` t²²²²²²¨bgmac0gmac1gpuhdmitxhdmitxm0-cec t²¨Phdmitx-scl t²¨Nhdmitx-sda t²¨Oi2c0i2c0-xfer t · ·¨ i2c1i2c1-xfer t · ·¨xi2c2i2c2m0-xfer t ··¨yi2c3i2c3m0-xfer t··¨zi2c4i2c4m0-xfer t · ·¨{i2c5i2c5m0-xfer t · ·¨|i2s1i2s1m0-lrcktx t²¨ji2s1m0-mclk t²¨$i2s1m0-sclktx t²¨ii2s1m0-sdi0 t ²¨ki2s1m0-sdo0 t²¨li2s2i2s2m0-lrcktx t²¨ni2s2m0-sclktx t²¨mi2s2m0-sdi t²¨oi2s2m0-sdo t²¨pi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk t²¨qpdmm0-clk1 t²¨rpdmm0-sdi0 t ²¨spdmm0-sdi1 t ²¨tpdmm0-sdi2 t ²¨updmm0-sdi3 t²¨vpmicpmic-int t´¨#pmupwm0pwm0m0-pins t²¨(pwm1pwm1m0-pins t²¨)pwm2pwm2m0-pins t²¨*pwm3pwm3-pins t²¨+pwm4pwm4-pins t²¨Ÿpwm5pwm5-pins t²¨ pwm6pwm6-pins t²¨¡pwm7pwm7-pins t²¨¢pwm8pwm8m0-pins t ²¨£pwm9pwm9m0-pins t ²¨¤pwm10pwm10m0-pins t ²¨¥pwm11pwm11m0-pins t²¨¦pwm12pwm12m0-pins t²¨§pwm13pwm13m0-pins t²¨¨pwm14pwm14m0-pins t²¨©pwm15pwm15m0-pins t²¨ªrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ t³³³³¨Wsdmmc0-clk t³¨Xsdmmc0-cmd t³¨Ysdmmc0-det t´¨Zsdmmc1sdmmc1-bus4@ t³³³³¨]sdmmc1-clk t³¨_sdmmc1-cmd t³¨^sdmmc2spdifspdifm0-tx t²¨wspi0spi0m0-pins0 t ²²²¨spi0m0-cs0 t²¨}spi0m0-cs1 t²¨~spi1spi1m0-pins0 t ²²²¨‚spi1m0-cs0 t²¨€spi1m0-cs1 t²¨�spi2spi2m0-pins0 t²²²¨…spi2m0-cs0 t²¨ƒspi2m0-cs1 t²¨„spi3spi3m0-pins0 t ²² ²¨ˆspi3m0-cs0 t²¨†spi3m0-cs1 t²¨‡tsadctsadc-shutorg t²¨œtsadc-pin t²¨�uart0uart0-xfer t´´¨'uart1uart1m0-xfer t ´ ´¨‰uart1m0-ctsn t²¨Šuart1m0-rtsn t ²¨‹uart2uart2m0-xfer t´´¨�uart3uart3m0-xfer t´´¨‘uart4uart4m0-xfer t´´¨’uart5uart5m0-xfer t´´¨“uart6uart6m0-xfer t´´¨”uart7uart7m0-xfer t´´¨•uart8uart8m0-xfer t´´¨–uart9uart9m0-xfer t´´¨—vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2btbt-enable-h t²¨�bt-host-wake-l tº¨�bt-wake-l t²¨Žhp-detecthp-det t´sdio-pwrseqwifi-enable-h t ²¨Äwifi-host-wake-l t ²¨ausb2vcc5v0-host-en t²¨Ãchosen ‚serial2:1500000n8reserved-memory öramoops@110000,ramoopsø Ž › § ±adc-keys ,adc-keys ½» Ébuttons Úw@ ôdbutton-recovery recovery ˜ lhdmi-con,hdmi-connectoródportendpointHTleds ,gpio-ledsrgb-led-r - ¬½  status-red¨¾rgb-led-g ¬½  - status-green¨¿rgb-led-b ¬½ - status-blue¨Àmulti-led,leds-group-multicolor -  status-rgb 3indicator <¾¿Àregulator-12v0-dcin,regulator-fixed övcc12v0_dcin+·C·¨Áregulator-3v3-vcc-sys,regulator-fixed övcc3v3_sys+2Z C2Z p!¨%regulator-5v0-vcc-sys,regulator-fixed övcc5v0_sys+LK@CLK@pÁ¨!regulator-5v0-vcc-host,regulator-fixed A TÂèdefaultÞà övcc5v0_host+LK@CLK@p!¨°sdio-pwrseq,mmc-pwrseq-simpleüŒ ýext_clockèdefaultÞÄ YÈ p` ¨\sound,simple-audio-cardBi2s +Analog RK809[simple-audio-card,cpu|Åsimple-audio-card,codec|Œ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyoffsetmode-normalmode-loadermode-recoverymode-bootloader#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controller#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltrockchip,mic-in-differentialdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removabledma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsmax-speedshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathconsole-sizeftrace-sizepmsg-sizerecord-sizeio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltcolorfunctionledsenable-active-highgpiopost-power-on-delay-msreset-gpios