Ð þíg8ÿÀ(§ÿˆ8google,voltorb-sku589825google,voltorbmediatek,mt8186 +7laptopDGoogle Voltorb sku589825 boardaliasesJ/soc/ovl@14005000O/soc/ovl@14006000W/soc/rdma@14007000]/soc/rdma@1401f000c/soc/i2c@11007000h/soc/i2c@11008000m/soc/i2c@11009000r/soc/i2c@1100f000w/soc/i2c@11016000|/soc/mmc@11230000�/soc/mmc@11240000†/soc/serial@11002000ccimediatek,mt8186-cciŽ•cciintermediate¡µÁ"opp-table-ccioperating-points-v2ÉÁopp-500000000ÔÍeÛ 'ÀÁopp-560000000Ô!`ìÛ L¸Áopp-612000000Ô$zaÛ •öÁopp-682000000Ô(¦~€Û ÷žÁ opp-752000000Ô,ÒœÛ YFÁ opp-822000000Ô0þ¹€Û ºîÁ opp-875000000Ô4'pÀÛ ëÂÁ opp-927000000Ô7@åÀÛ 5Á opp-980000000Ô:i�Û ~>Áopp-1050000000Ô>•º€Û ßæÁopp-1120000000ÔBÁØÛ )$Áopp-1155000000ÔD׿ÀÛ ŠÌÁopp-1190000000ÔFíõ€Û Ô Áopp-1260000000ÔKÛ~ðÁopp-1330000000ÔOF0€Û)ÖÁopp-1400000000ÔSrNÛ¼RÁopp-table-cluster0operating-points-v2ÉÁopp-500000000ÔÍeÛ 'Àéopp-774000000Ô."M€Û L¸éopp-875000000Ô4'pÀÛ ®`éopp-975000000Ô:QÀÛ é opp-1075000000Ô@2ÀÛ q°é opp-1175000000ÔF ÀÛ ÓXé opp-1275000000ÔKþôÀÛ 5é opp-1375000000ÔQôÕÀÛ –¨é opp-1500000000ÔYh/Û ºéopp-1618000000Ô`p¸€Û Yøéopp-1666000000ÔcM$€Û » éopp-1733000000ÔgK{@ÛHéopp-1800000000ÔkIÒÛ~ðéopp-1866000000Ôo8æ€Ûùéopp-1933000000Ôs7=@ÛZªéopp-2000000000Ôw5”Û¼Réopp-table-cluster1operating-points-v2ÉÁ#opp-774000000Ô."M€Û L¸éopp-835000000Ô1ÅÀÛ •öéopp-919000000Ô6ÆÓÀÛ ÷žéopp-1002000000Ô;¹N€Û YFé opp-1085000000Ô@«É@Û ÓXé opp-1169000000ÔE­†@Û 5é opp-1308000000ÔMöÛ ßæé opp-1419000000ÔT”8ÀÛ Yøé opp-1530000000Ô[1ò€Û ìtéopp-1670000000ÔcŠ-€Û—Zéopp-1733000000ÔgK{@Ûùéopp-1796000000Ôk ÉÛséopp-1860000000ÔnÝYÛÔ¼éopp-1923000000Ôrž¦ÀÛ6déopp-1986000000Ôz0„€Ûéopp-2050000000Ôƒ!VÛécpus+cpu-mapcluster0core0÷core1÷core2÷core3÷core4÷core5÷core6÷core7÷cpu@0ûcpuarm,cortex-a55 psciw5”Ž•cpuintermediate¡)TC~V f€s@…€’€Ÿ@±€¾!ÏÞ"µÁcpu@100ûcpuarm,cortex-a55 psciw5”Ž•cpuintermediate¡)TC~V f€s@…€’€Ÿ@±€¾!ÏÞ"µÁcpu@200ûcpuarm,cortex-a55 psciw5”Ž•cpuintermediate¡)TC~V f€s@…€’€Ÿ@±€¾!ÏÞ"µÁcpu@300ûcpuarm,cortex-a55 psciw5”Ž•cpuintermediate¡)TC~V f€s@…€’€Ÿ@±€¾!ÏÞ"µÁcpu@400ûcpuarm,cortex-a55 psciw5”Ž•cpuintermediate¡)TC~V f€s@…€’€Ÿ@±€¾!ÏÞ"µÁcpu@500ûcpuarm,cortex-a55 psciw5”Ž•cpuintermediate¡)TC~V f€s@…€’€Ÿ@±€¾!ÏÞ"µÁcpu@600ûcpuarm,cortex-a76 psciz0„€Ž•cpuintermediate¡#)OCV$%fs@…’Ÿ@±¾&ÏÞ"µ'Ácpu@700ûcpuarm,cortex-a76 psciz0„€Ž•cpuintermediate¡#)OCV$%fs@…’Ÿ@±¾&ÏÞ"µ'Áidle-statesëpscicpu-retention-larm,idle-stateø 21dA@Ácpu-retention-barm,idle-stateø 21dAxÁ$cpu-off-larm,idle-stateø d1úA4Á cpu-off-barm,idle-stateø d1úAlÁ%l2-cache0cacheRhu@‡¾(^Á!l2-cache1cacheRhu@‡¾(^Á&l3-cachecacheRhu@‡^Á(fixed-factor-clock-13mfixed-factor-clocklŽ)yƒŽclk13mÁ>oscillator-26m fixed-clocklŒº€Žclk26mÁ)oscillator-32k fixed-clockl€Žclk32kopp-table-gpuoperating-points-v2Áwopp-299000000ÔÒ`ÀÛ X”¡ÿopp-332000000ÔÉëÛ ‰h¡ÿopp-366000000Ôз€Û º<¡ÿopp-400000000ÔׄÛ Ò¦¡ÿopp-434000000ÔÞP€Û z¡ÿopp-484000000ÔÙAÛ 4N¡ÿopp-535000000ÔãsÀÛ }Œ¡ÿopp-586000000Ô"í¦€Û ®`¡ÿopp-637000000Ô%÷Ù@Û ß4¡ÿopp-690000000Ô) �€Û @Ü¡ÿopp-743000000Ô,IGÀÛ Š¡ÿopp-796000000Ô/qÿÛ ë¡ÿopp-850000000Ô2©ø€Û 5¡ÿopp-900000000-3Ô5¤éÛ øP¡Ïopp-900000000-4Ô5¤éÛ Ç|¡opp-900000000-5Ô5¤éÛ –¨¡ opp-950000000-3Ô8ŸÙ€Û » ¡Ïopp-950000000-4Ô8ŸÙ€Û Yø¡opp-950000000-5Ô8ŸÙ€Û øP¡ opp-1000000000-3Ô;šÊÛ~ð¡Ïopp-1000000000-4Ô;šÊÛ ìt¡opp-1000000000-5Ô;šÊÛ Yø¡ pmu-a55arm,cortex-a55-pmu ²*pmu-a76arm,cortex-a76-pmu ²+psci arm,psci-1.0smctimerarm,armv8-timer @²   soc+ simple-bus½Áinterrupt-controller@c000000 arm,gic-v3ÈÙ ð    ² Áppi-partitionsinterrupt-partition-0%Á*interrupt-partition-1%Á+syscon@c53a000mediatek,mt8186-mcusyssyscon S lÁsyscon@10000000 mediatek,mt8186-topckgensysconlÁ-syscon@10001000#mediatek,mt8186-infracfg_aosysconl.Á/syscon@10003000mediatek,mt8186-pericfgsyscon0Áipinctrl@10005000mediatek,mt8186-pinctrl€P "$&*,°B;iocfg0iocfg_ltiocfg_lmiocfg_lbiocfg_bliocfg_rbiocfg_rteintEUa,¹ð²ºÈ ßmTPTPTPI2S0_HP_DII2S3_DP_SPKR_DOSAR_INT_ODLBT_WAKE_AP_ODLWIFI_INT_ODLDPBRDG_INT_ODLEDPBRDG_INT_ODLEC_AP_HPD_ODTCHPAD_INT_ODLTCHSCR_INT_1V8_ODLEC_AP_INT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLAP_FLASH_WP_LHP_INT_ODLPEN_EJECT_ODWCAM_PWDN_LWCAM_RST_LUCAM_SEN_ENUCAM_RST_LLTE_RESET_LLTE_SAR_DETECT_LI2S2_DP_SPK_MCKI2S2_DP_SPKR_BCKI2S2_DP_SPKR_LRCKI2S2_DP_SPKR_DI (TP)EN_PP1000_EDPBRDGEN_PP1800_EDPBRDGEN_PP3300_EDPBRDGUART_GSC_TX_AP_RXUART_AP_TX_GSC_RXUART_DBGCON_TX_ADSP_RXUART_ADSP_TX_DBGCON_RXEN_PP1000_DPBRDGTCHSCR_REPORT_DISABLEEN_PP3300_DPBRDGEN_PP1800_DPBRDGSPI_AP_CLK_ECSPI_AP_CS_EC_LSPI_AP_DO_EC_DISPI_AP_DI_EC_DOSPI_AP_CLK_GSCSPI_AP_CS_GSC_LSPI_AP_DO_GSC_DISPI_AP_DI_GSC_DOUART_DBGCON_TX_SCP_RXUART_SCP_TX_DBGCON_RXEN_PP1200_CAM_XEN_PP2800A_VCM_XEN_PP2800A_UCAM_XEN_PP2800A_WCAM_XWLAN_MODULE_RST_LEN_PP1200_UCAM_XI2S1_HP_DOI2S1_HP_BCKI2S1_HP_LRCKI2S1_HP_MCKTCHSCR_RST_1V8_LSPI_AP_CLK_ROMSPI_AP_CS_ROM_LSPI_AP_DO_ROM_DISPI_AP_DI_ROM_DONCNCEMMC_STRBEMMC_CLKEMMC_CMDEMMC_RST_LEMMC_DATA0EMMC_DATA1EMMC_DATA2EMMC_DATA3EMMC_DATA4EMMC_DATA5EMMC_DATA6EMMC_DATA7AP_KPCOL0NCNCNCTPSDIO_CLKSDIO_CMDSDIO_DATA0SDIO_DATA1SDIO_DATA2SDIO_DATA3NCNCNCNCNCNCEDPBRDG_PWRENBL_PWM_1V8EDPBRDG_RST_LMIPI_DPI_CLKMIPI_DPI_VSYNCMIPI_DPI_HSYNCMIPI_DPI_DEMIPI_DPI_D0MIPI_DPI_D1MIPI_DPI_D2MIPI_DPI_D3MIPI_DPI_D4MIPI_DPI_D5MIPI_DPI_D6MIPI_DPI_DA7MIPI_DPI_D8MIPI_DPI_D9MIPI_DPI_D10MIPI_DPI_D11PCM_BT_CLKPCM_BT_SYNCPCM_BT_DIPCM_BT_DOJTAG_TMS_TPJTAG_TCK_TPJTAG_TDI_TPJTAG_TDO_TPJTAG_TRSTN_TPCLK_24M_WCAMCLK_24M_UCAMUCAM_DET_ODLAP_I2C_EDPBRDG_SCL_1V8AP_I2C_EDPBRDG_SDA_1V8AP_I2C_TCHSCR_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_TCHPAD_SDA_1V8AP_I2C_DPBRDG_SCL_1V8AP_I2C_DPBRDG_SDA_1V8AP_I2C_WLAN_SCL_1V8AP_I2C_WLAN_SDA_1V8AP_I2C_AUD_SCL_1V8AP_I2C_AUD_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_UCAM_SDA_1V8AP_I2C_UCAM_SCL_1V8AP_I2C_UCAM_SDA_1V8AP_I2C_WCAM_SCL_1V8AP_I2C_WCAM_SDA_1V8SCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AP_EC_WARM_RST_REQAP_XHCI_INIT_DONEUSB3_HUB_RST_LEN_SPKRBEEP_ONAP_EDP_BKLTENEN_PP3300_DISP_XEN_PP3300_SDBRDG_XBT_KILL_1V8_LWIFI_KILL_1V8_LPWRAP_SPI0_CSNPWRAP_SPI0_CKPWRAP_SPI0_MOPWRAP_SPI0_MISRCLKENA0SRCLKENA1SCP_VREQ_VAOAP_RTC_CLK32KAP_PMIC_WDTRST_LAUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_CLK_MISOAUD_SYNC_MISOAUD_DAT_MISO0AUD_DAT_MISO1NCNCDPBRDG_PWRENDPBRDG_RST_LLTE_W_DISABLE_LLTE_SAR_DETECT_LEN_PP3300_LTE_XLTE_PWR_OFF_LLTE_RESET_LTPTPÁ,aud-clk-mosi-off-pinsÁ pins-clk-sync}¦§„‘aud-clk-mosi-on-pinsÁ¡pins-clk-sync}¦§aud-clk-miso-off-pinsÁ¢pins-clk-sync}ª«„‘aud-clk-miso-on-pinsÁ£pins-clk-sync}ª«aud-dat-mosi-off-pinsÁ¦pins-dat}¨©„‘aud-dat-mosi-on-pinsÁ§pins-dat}¨©aud-dat-miso-off-pinsÁ¤pins-dat}¬­„‘aud-dat-miso-on-pinsÁ¥pins-dat}¬­ µaud-gpio-i2s0-off-pinsÁ¨pins-sdata}aud-gpio-i2s0-on-pinsÁ©pins-sdata}aud-gpio-i2s-off-pinsÁªpins-clk-sdata}89:;Âaud-gpio-i2s1-on-pinsÁ«pins-clk-sdata}89:;aud-gpio-i2s2-off-pinsÁ¬pins-cmd-dat}Âaud-gpio-i2s2-on-pinsÁ­pins-clk}Íaud-gpio-i2s3-off-pinsÁ®pins-sdata}Âaud-gpio-i2s3-on-pinsÁ¯pins-sdata}Íaud-gpio-pcm-off-pinsÁ°pins-clk-sdata}stuvÂaud-gpio-pcm-on-pinsÁ±pins-clk-sdata}stuvaud-gpio-dmic-sec-pinsÁ²pins}Âbt-reset-pinsÁqpins-bt-reset}›Üdpi-sleep-pinsÁ|pins-cmd-dat@}ghijklmnopqredfcÍ Âdpi-default-pinsÁ{pins-cmd-dat@}ghijklmnopqredfcÍ cros-ec-int-pinsÁdpins-ec-ap-int-odl} „edp-panel-fixed-pinsÁŸpins-vreg-en}™Üen-pp1800-dpbrdg-pinsÁžpins-vreg-en}'Âgsc-int-pinsÁfpins-gsc-ap-int-odl}„i2c0-pinsÁHpins-bus}€µÍ„i2c1-pinsÁRpins-bus}‚�µÍ„i2c2-pinsÁUpins-bus}„ƒµÍ„i2c3-pinsÁWpins-bus}†…µÍ„i2c5-pinsÁ\pins-bus}ЉµÍ„it6505-pinsÁXpins-hpd} „èpins-int}„èpins-reset}±Âèmmc0-default-pinsÁjpins-clk}D‘fpins-cmd-dat$}GHIJKLMNE„èepins-rst}Fèemmc0-uhs-pinsÁkpins-clk}DÍ‘fpins-cmd-dat$}GHIJKLMNE„Íèepins-ds}CÍ‘fpins-rst}Fèemmc1-default-pinsÁmpins-clk}TÍ‘fpins-cmd-dat}VWXYU„Íèemmc1-uhs-pinsÁnpins-clk}TÍ‘fpins-cmd-dat}VWXYU„Íèemmc1-eint-pinsÁopins-dat1}W„èenor-default-pinsÁFpins-clk-dat }?=@Í‘pins-cs-dat }>ABÍèpen-eject-pinsÁ�pins}„µdisp-pwm-pinsÁbpins}aÜspeaker-codec-default-pinsÁ¸pins-sdb}–Âscp-default-pinsÁ?pins-scp-uart}01spi1-pinsÁcpins-bus}()*+µ„spi2-pinsÁepins-bus},-./µ„spmi-pinsÁ=pins-bus}·¸touchscreen-pinsÁSpins-irq} „èpins-reset}<Üpins-report-sw}%Âtrackpad-default-pinsÁVpins-int-n} „µwifi-enable-pinsÁºpins-wifi-enable}6wifi-wakeup-pinsÁ»pins-wifi-wakeup}„anx7625-pinsÁIpins-int} „µpins-reset}bÂpins-power-en}`Âpp1000-edpbrdg-en-pinsÁ¼pins-vreg-en}Âpp1800-edpbrdg-en-pinsÁ½pins-vreg-en}Âpp3300-edpbrdg-en-pinsÁ¾pins-vreg-en}Âsyscon@10006000)mediatek,mt8186-scpsyssysconsimple-mfd`power-controller!mediatek,mt8186-power-controller+õÁCpower-domain@0Ž-•mfg00+õ .power-domain@1/+õ 0power-domain@2õpower-domain@3õpower-domain@17Ž--$•subsys-csirx-top0subsys-csirx-top1õpower-domain@4Ž-/=•sys_ckref_ckõpower-domain@5Ž/B/?•sys_ckref_ckõpower-domain@18Ž-/->•audioadspsubsys-adsp-bus+õpower-domain@19+õpower-domain@20/õpower-domain@16/õpower-domain@60Ž-*-+1 111M•dispmdpsubsys-smi-infrasubsys-smi-commonsubsys-smi-galssubsys-smi-iommu/+õpower-domain@14Ž-)2 •vdec0larb/õpower-domain@10 8Ž---- 3-#-%6•cam0cam1cam2cam3galssubsys-cam-tmsubsys-cam-top/+õpower-domain@12 õpower-domain@11 õpower-domain@7Ž4-&•galssubsys-img-top/+õpower-domain@8õpower-domain@9 (Ž-'5555P•subsys-ipe-topsubsys-ipe-larb0subsys-ipe-larb1subsys-ipe-smisubsys-ipe-gals/õpower-domain@13 Ž-$6•venc0subsys-larb/õpower-domain@15Ž-:77%•wpe0subsys-larb-cksubsys-larb-pclk/õwatchdog@10007000mediatek,mt8186-wdt)p.AÁgsyscon@1000c000"mediatek,mt8186-apmixedsyssysconÀlÁpwrap@1000d000mediatek,mt8186-pwrapsysconÐ;pwrap²ÂŽ// •spiwrappmic mediatek,mt6366mediatek,mt6358ð Z,ÉÈcodec,mediatek,mt6366-soundmediatek,mt6358-soundn8zregulators4mediatek,mt6366-regulatormediatek,mt6358-regulator�9ž9¯9À9Ò9å9ö9 99-9A9Q9a:q;�<‘<vcore¡pp0750_dvdd_core°dpÈ 5àjõÈ)vdram1¡pp1125_emi_vdd2°*ˆÈ*ˆà0Ôõ)Á;vgpu¡ppvar_dvdd_vgpu°¡ È~ðàjõÈ=.T† Á0vproc11¡ppvar_dvdd_proc_bc_mt6366° 'ÀÈO€àjõÈ) qdisabledvproc12¡ppvar_dvdd_proc_lc° 'ÀÈO€àjõÈ)Ávs1 ¡pp2000_vs1°„€È„€à0Ôõ)Á:vs2 ¡pp1350_vs2°™pÈ™pà0Ôõ)Á<va12 ¡pp1200_va12°O€ÈO€õ)vaud28¡pp2800_vaud28°*¹€È*¹€õÁ8vaux18¡pp1840_vaux18°w@È€õvbif28¡pp2800_vbif28°*¹€È*¹€õvcn18¡pp1800_vcn18_x°w@Èw@õvcn28¡pp2800_vcn28_x°*¹€È*¹€õvefuse¡pp1800_vefuse°w@Èw@õvfe28¡pp2800_vfe28_x°*¹€È*¹€õvemc ¡pp3000_vemc°-ÆÀÈ-ÆÀõ<Álvibr¡pp2800_vibr_x°*¹€È*¹€õ<vio18¡pp1800_vio18_s3°w@Èw@õ Œ)Á]vio28¡pp2800_vio28_x°*¹€È*¹€õvm18¡pp1800_emi_vdd1°w@È€õE)vmc ¡pp3000_vmc°-ÆÀÈ-ÆÀõ<vmddr¡pm0750_emi_vmddr° ®`È q°õE)vmch ¡pp3000_vmch°-ÆÀÈ-ÆÀõ<vcn33¡pp3300_vcn33_x°2Z È2Z õvdram2¡pp0600_emi_vddq° 'ÀÈ 'Àõ ä)vrf12¡pp1200_vrf12_x°O€ÈO€õxvrf18¡pp1800_vrf18_x°w@Èw@õxvsim1¡pp1860_vsim1_x°w@Èa õvsim2¡pp2760_vsim2_x°)2àÈ*@õÁYvsram-gpu¡pp0900_dvdd_sram_gpu° øPÈ�àjõð=0T† Á.vsram-others¡pp0900_dvdd_sram_core° » È » àjõð)vsram-proc11¡pp0900_dvdd_sram_bc° øPÈàjõð)vsram-proc12¡pp0900_dvdd_sram_lc° øPÈàjõð)vusb ¡pp3070_vusb°-ÆÀÈ.Ø0õ)vxo22 ¡pp2240_vxo22°!‘ÀÈ".õx)rtc(mediatek,mt6366-rtcmediatek,mt6358-rtcspmi@10015000*mediatek,mt8186-spmimediatek,mt8195-spmi P° ;pmifspmimstŽ//-2(•pmif_sys_ckpmif_tmr_ckspmimst_clk_muxx-2ˆ-t ²íñqokayŸdefault­=+pmic@64mediatek,mt6319-regulatormediatek,mt6315-regulatorregulatorsvbuck1¡ppvar_dvdd_proc_bc_mt6319° 'ÀÈ7õ )Á'timer@10017000,mediatek,mt8186-timermediatek,mt6765-timerp²ÏŽ>mailbox@1022c000mediatek,mt8186-gce"À@Ž/•gce²ª·Áxscp@10500000mediatek,mt8186-scp P\�€ ;sramcfg²ÍŸdefault­?Ãmediatek/mt8186/scp.imgÑ@qokayÁ�cros-ec-rpmsggoogle,cros-ec-rpmsgßcros-ec-rpmsgadsp@10680000mediatek,mt8186-dsp@h €h°hð;cfgsramsecbusŽ-/->•audiodspadsp_busx-/-> ˆ)-EórxtxþABCqokayÑDEÁ³mailbox@10686100mediatek,mt8186-adsp-mbox·ha²iÁAmailbox@10687100mediatek,mt8186-adsp-mbox·hq²jÁBspi@11000000mediatek,mt8186-nor Ž-3/O/c/d•spisfaxiaxi_sx-3ˆ-P²%qokayŸdefault­F+flash@0jedec,spi-norSÀadc@11001000.mediatek,mt8186-auxadcmediatek,mt8173-auxadc%Ž/"•mainserial@11002000*mediatek,mt8186-uartmediatek,mt6577-uart ²p Ž)/ •baudbusqokayserial@11003000*mediatek,mt8186-uartmediatek,mt6577-uart0²q Ž)/ •baudbus qdisabledi2c@11007000mediatek,mt8186-i2c p ²iŽG/' •maindmay+qokayŸdefault­H€anx7625@58analogix,anx7625XŸdefault­I 7,` D,bPJ]KjLwp0Œp0ports+port@0endpoint¡M±Áport@1endpoint¡NÁQaux-buspanel edp-panel¼OÉPportendpoint¡QÁNi2c@11008000mediatek,mt8186-i2c € ²jŽG/' •maindmay+qokayŸdefault­R€Ó@touchscreen@5dgoodix,gt7375p] Z, Ÿdefault­S D,<oTí qdisabledtouchscreen@10elan,ekth6915 Z, Ÿdefault­S D,< Ti2c@11009000mediatek,mt8186-i2c � €²kŽG/' •maindmay+qokayŸdefault­UV€ÓUðtrackpad@15elan,ekth3000 Z, T$trackpad@2c hid-over-i2c,2  Z, oT$i2c@1100f000mediatek,mt8186-i2c ð €²lŽG/' •maindmay+qokayŸdefault­W† dp-bridge@5c ite,it6505\ Z,Ÿdefault­XARY^Z D,±Á¶ports+port@0endpointkðÑ€¡[Á}port@1i2c@11011000mediatek,mt8186-i2c  €€²mŽG/' •maindmay+ qdisabledi2c@11016000mediatek,mt8186-i2c ` ²bŽG/' •maindmay+qokayŸdefault­\codec@1arealtek,rt5682s Z,A|]ˆ]•]¤^²Áµi2c@1100d000mediatek,mt8186-i2c Ð ²cŽG/' •maindmay+ qdisabledi2c@11004000mediatek,mt8186-i2c @ €²nŽG/' •maindmay+ qdisabledi2c@11005000mediatek,mt8186-i2c P €€²oŽG/' •maindmay+ qdisabledspi@1100a000(mediatek,mt8186-spimediatek,mt6765-spi+ ²ŠŽ-K- /•parent-clksel-clkspi-clk qdisabledthermal-sensor@1100b000mediatek,mt8186-lvts°²cŽ/ Á/È_`$Ôlvts-calib-data-1lvts-calib-data-2åÁ“svs@1100bc00mediatek,mt8186-svs¼²ŽŽ/ •mainÈa_(Ôsvs-calibration-datat-calibration-dataÁ/ûsvs_rstpwm@1100e0002mediatek,mt8186-disp-pwmmediatek,mt8183-disp-pwmà²� Ž-/4•mainmmqokayŸdefault­bÁ›spi@11010000(mediatek,mt8186-spimediatek,mt6765-spi+²‹Ž-K- /8•parent-clksel-clkspi-clkqokayŸdefault­c ec@0google,cros-ec-spi Z, Ÿdefault­dB@i2c-tunnelgoogle,cros-ec-i2c-tunnel &+sbs-battery@bsbs,sbs-battery  8 Ltypecgoogle,cros-ec-typec+connector@0usb-c-connector aleft gdual rhost |sourceconnector@1usb-c-connector aright gdual rhost |sourcekeyboard-controllergoogle,cros-ec-keyb ‹ ›  ®D Èž­txcàá q rs}0Y1 d"#(  \V |})  Ž + ^a !%$' & + ,./-32*5 4 9    8 l j6  g i( Õ  spi@11012000(mediatek,mt8186-spimediatek,mt6765-spi+ ²‘Ž-K- /;•parent-clksel-clkspi-clkqokayŸdefault­e ê,- tpm@0 google,cr50 Z,Ÿdefault­fB@spi@11013000(mediatek,mt8186-spimediatek,mt6765-spi+0²’Ž-K- /<•parent-clksel-clkspi-clk qdisabledspi@11014000(mediatek,mt8186-spimediatek,mt6765-spi+@²tŽ-K- /J•parent-clksel-clkspi-clk qdisabledspi@11015000(mediatek,mt8186-spimediatek,mt6765-spi+P²uŽ-K- /K•parent-clksel-clkspi-clk qdisabledclock-controller@11017000mediatek,mt8186-imp_iic_wrapplÁGserial@11018000*mediatek,mt8186-uartmediatek,mt6577-uart€²ö Ž)/ •baudbus qdisabledi2c@11019000mediatek,mt8186-i2c � €²dŽG /' •maindmay+ qdisabledaudio-controller@11210000mediatek,mt8186-sound! ÄŽ/,/6---F- - --e--h-?-@-A-B-C-ƒ-„-…-†-‡-,)}•aud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_audio_inttop_mainpll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s4_m_seltop_tdm_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div4top_apll12_div_tdmtop_mux_audio_htop_clk26m_clk²© ó/ -Ág ûaudiosysqokayÁ´usb@11201000#mediatek,mt8186-mtu3mediatek,mtu3  -ÿ > ;macippc(Ž-/=/3//>$•sys_ckref_ckmcu_ckdma_ckxhci_ck²/ hC+Á$ i qokayusb@11200000'mediatek,mt8186-xhcimediatek,mtk-xhci ;mac(Ž-/=/3//>$•sys_ckref_ckmcu_ckdma_ckxhci_ck²&qokay 5Tmmc@11230000(mediatek,mt8186-mmcmediatek,mt8183-mmc #Í Ž- //U/•sourcehclksource_cgcrypto²dx- ˆqokayŸdefaultstate_uhs­j Ak K ë U c u „ “   ¦ ® ¿ Î ål ñ]mmc@11240000(mediatek,mt8186-mmcmediatek,mt8183-mmc $ÉŽ-//V•sourcehclksource_cgx-ˆ-oqokayŸdefaultstate_uhsstate_eint­m An þo msdcsdio_wakeup Ze,W+ K ë  ) 7 D$ Z g   U åT ñ] npbluetooth@2mediatek,mt7921s-bluetoothŸdefault­q D,›usb@11281000#mediatek,mt8186-mtu3mediatek,mtu3 (-ÿ(> ;macippc$Ž/B/?/7)/@$•sys_ckref_ckmcu_ckdma_ckxhci_ck²K rsC+Á$ i$qokayusb@11280000'mediatek,mt8186-xhcimediatek,mtk-xhci(;mac$Ž/B/?/7)/@$•sys_ckref_ckmcu_ckdma_ckxhci_ck²Dqokay 5tt-phy@11c80000.mediatek,mt8186-tphymediatek,generic-tphy-v2+ÁÈqokayusb-phy@0Ž)•ref yÁrusb-phy@700 Ž)•ref yÁst-phy@11ca0000.mediatek,mt8186-tphymediatek,generic-tphy-v2+ÁÊqokayusb-phy@0Ž)•ref y „Áhefuse@11cb0000%mediatek,mt8186-efusemediatek,efuseË+lvts1-calib@1ccÌÁ_lvts2-calib@2f8øÁ`calib@550PPÁagpu-speedbin@59cœ ”Ávsocinfo-data1@7a0 dsi-phy@11cc0000mediatek,mt8183-mipi-txÌŽ)l y Žmipi_tx0_pllqokayÁ~clock-controller@13000000mediatek,mt8186-mfgsyslÁugpu@13040000&mediatek,mt8186-maliarm,mali-bifrost@Žu0² jobmmugpuCC ™core0core1ÏÈv Ôspeed-bin¡w)Oqokay ¬0Á˜syscon@14000000mediatek,mt8186-mmsyssysconl.þxx ¸xÁ1mutex@14001000mediatek,mt8186-disp-mutexŽ1²' ¸x в³Csmi@14002000mediatek,mt8186-smi-common  Ž1111•apbsmigals0gals1CÁysmi@14003000mediatek,mt8186-smi-larb0Ž11•apbsmi ä õyCÁ€smi@14004000mediatek,mt8186-smi-larb@Ž11•apbsmi ä õyCÁ�ovl@140050002mediatek,mt8186-disp-ovlmediatek,mt8192-disp-ovlPŽ1²) z ¸xPCovl@140060008mediatek,mt8186-disp-ovl-2lmediatek,mt8192-disp-ovl-2l`Ž1²* z! ¸x`Crdma@140070004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdmapŽ1²+ z" ¸xpCcolor@140090006mediatek,mt8186-disp-colormediatek,mt8173-disp-color�Ž1 ²- ¸x€Cdpi@1400a000mediatek,mt8186-dpi Ž-;1 •pixelenginepllx-;ˆ-j²5C qdisabledŸdefaultsleep­{ A|portendpoint¡}Á[ccorr@1400b0006mediatek,mt8186-disp-ccorrmediatek,mt8192-disp-ccorr°Ž1². ¸x°Caal@1400c0002mediatek,mt8186-disp-aalmediatek,mt8183-disp-aalÀŽ1²0 ¸xÀCgamma@1400d0006mediatek,mt8186-disp-gammamediatek,mt8183-disp-gammaÐŽ1 ²1 ¸xÐCpostmask@1400e000<mediatek,mt8186-disp-postmaskmediatek,mt8192-disp-postmaskàŽ1 ²2 ¸xàCdither@1400f0008mediatek,mt8186-disp-dithermediatek,mt8183-disp-ditherðŽ1²3 ¸xðCdsi@14013000mediatek,mt8186-dsi0Ž11~•enginedigitalhs²7CÁ1 ~ dphyqokayportendpoint¡ÁMiommu@14016000mediatek,mt8186-iommu-mm`Ž1•bclk²98 €�‚ƒ„…†‡ˆ‰Š‹Œ�C "Ázrdma@1401f0004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdmaðŽ1²4 z  ¸xðCclock-controller@14020000mediatek,mt8186-wpesyslÁ7smi@14023000mediatek,mt8186-smi-larb0Ž77•apbsmi ä õyCÁ…clock-controller@15020000mediatek,mt8186-imgsys1lÁ4smi@1502e000mediatek,mt8186-smi-larbàŽ44•apbsmi ä  õyCÁ†clock-controller@15820000mediatek,mt8186-imgsys2‚lÁŽsmi@1582e000mediatek,mt8186-smi-larb‚àŽ4Ž•apbsmi ä  õyCÁ‡video-decoder@16000000mediatek,mt8186-vcodec-decÁ+½@ÿð z€ /�video-codec@16025000mediatek,mtk-vcodec-coreP²W` z€z�z‚zƒz„z…z†z‡zˆz‰zŠz‹ Ž-)22-U%•vdec-selvdec-soc-vdecvdecvdec-topx-)ˆ-UCsmi@1602e000mediatek,mt8186-smi-larbàŽ22•apbsmi ä õyCÁƒclock-controller@1602f000mediatek,mt8186-vdecsysðlÁ2clock-controller@17000000mediatek,mt8186-vencsyslÁ6smi@17010000mediatek,mt8186-smi-larbŽ66•apbsmi ä õyC Á„video-encoder@170200006mediatek,mt8186-vcodec-encmediatek,mt8183-vcodec-enc ²óH zàzázâzãzäzåzæzçzèŽ6 •venc_selx-$ˆ-UC  /�jpeg-encoder@17030000+mediatek,mt8186-jpgencmediatek,mtk-jpgenc²õŽ6•jpgenc zézêzëzìC clock-controller@1a000000mediatek,mt8186-camsyslÁ3smi@1a001000mediatek,mt8186-smi-larbŽ33•apbsmi ä  õyC Áˆsmi@1a002000mediatek,mt8186-smi-larb Ž33•apbsmi ä õyC Á‰smi@1a00f000mediatek,mt8186-smi-larbðŽ3�•apbsmi ä õyC ÁŠsmi@1a010000mediatek,mt8186-smi-larbŽ3‘•apbsmi ä õyC Á‹clock-controller@1a04f000mediatek,mt8186-camsys_rawaðlÁ�clock-controller@1a06f000mediatek,mt8186-camsys_rawbðlÁ‘clock-controller@1b000000mediatek,mt8186-mdpsyslÁ’smi@1b002000mediatek,mt8186-smi-larb Ž’’•apbsmi ä õyCÁ‚clock-controller@1c000000mediatek,mt8186-ipesyslÁ5smi@1c00f000mediatek,mt8186-smi-larbðŽ55•apbsmi ä õyC Á�smi@1c10f000mediatek,mt8186-smi-larbðŽ55•apbsmi ä õyC ÁŒthermal-zonescpu-little0-thermal <è J– `“tripstrip-alert0 pL |Ð?passiveÁ”trip-alert1 ps |Ð?hottrip-crit p†  | ?criticalcooling-mapsmap0 ‡”H Œÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little1-thermal <è J– `“tripstrip-alert0 pL |Ð?passiveÁ•trip-alert1 ps |Ð?hottrip-crit p†  | ?criticalcooling-mapsmap0 ‡•H Œÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little2-thermal <è J– `“tripstrip-alert0 pL |Ð?passiveÁ–trip-alert1 ps |Ð?hottrip-crit p†  | ?criticalcooling-mapsmap0 ‡–H Œÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcam-thermal <è Jú `“tripstrip-alert0 pL |Ð?passivetrip-alert1 ps |Ð?hottrip-crit p†  | ?criticalnna-thermal <è Jú `“tripstrip-alert0 pL |Ð?passivetrip-alert1 ps |Ð?hottrip-crit p†  | ?criticaladsp-thermal <è Jú `“tripstrip-alert0 pL |Ð?passivetrip-alert1 ps |Ð?hottrip-crit p†  | ?criticalgpu-thermal <è Jú `“tripstrip-alert0 pL |Ð?passiveÁ—trip-alert1 ps |Ð?hottrip-crit p†  | ?criticalcooling-mapsmap0 ‡— Œ˜ÿÿÿÿÿÿÿÿcpu-big0-thermal <è Jd `“tripstrip-alert0 pL |Ð?passiveÁ™trip-alert1 ps |Ð?hottrip-crit p†  | ?criticalcooling-mapsmap0 ‡™ Œÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-big1-thermal <è Jd `“tripstrip-alert0 pL |Ð?passiveÁštrip-alert1 ps |Ð?hottrip-crit p†  | ?criticalcooling-mapsmap0 ‡š Œÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿchosen ›serial0:115200n8memory@40000000ûmemory@backlight-lcd0pwm-backlight §›¡ ¼œ 7,˜ ¬ÿ ¾ÿ Õ@ÁPbt-sco linux,bt-scoAdmic-codec dmic-codecA î û2gpio-keys gpio-keysŸdefault­� qdisabledpen-insert-switch aPen Insert >, $  *regulator-pp1800-dpbrdg-dxregulator-fixedŸdefault­ž >,'¡pp1800_dpbrdg_dx ; N]ÁZregulator-pp3300-disp-xregulator-fixedŸdefault­Ÿ >,™¡pp3300_disp_x ; Y N^ÁOregulator-pp3300-ldo-z5regulator-fixed¡pp3300_ldo_z5) Y°2Z È2Z  Nœregulator-pp3300-s3regulator-fixed ¡pp3300_s3) Y N^ÁTregulator-pp3300-z2regulator-fixed ¡pp3300_z2) Y°2Z È2Z  NœÁ^regulator-pp4200-z2regulator-fixed ¡pp4200_z2) Y°@@È@@ NœÁ9regulator-pp5000-z2regulator-fixed ¡pp5000_z2) Y°LK@ÈLK@ NœÁ¹regulator-ppvar-sysregulator-fixed ¡ppvar_sys) YÁœreserved-memory+Ámemory@61000000shared-dma-poola kÁDmemory@60000000shared-dma-pool` kÁEmemory@50000000shared-dma-poolP  kÁ@sound.mediatek,mt8186-mt6366-rt5682s-max98360-soundCŸaud_clk_mosi_offaud_clk_mosi_onaud_clk_miso_offaud_clk_miso_onaud_dat_miso_offaud_dat_miso_onaud_dat_mosi_offaud_dat_mosi_onaud_gpio_i2s0_offaud_gpio_i2s0_onaud_gpio_i2s1_offaud_gpio_i2s1_onaud_gpio_i2s2_offaud_gpio_i2s2_onaud_gpio_i2s3_offaud_gpio_i2s3_onaud_gpio_pcm_offaud_gpio_pcm_onaud_gpio_dmic_sec­  A¡ þ¢ r£ |¤ †¥ �¦ š§ ¤¨ ®© ¸ª ë ά Ù­ ä® ï¯ ú°±²³)´I;HeadphoneHPOLHeadphoneHPORIN1PHeadset MicSpeakersSpeakerHDMI1TXhs-playback-dai-linkII2S0Si2s^cpucodectµhs-capture-dai-linkII2S1Si2s^cpucodectµspk-share-dai-linkII2S2^cpuspk-hdmi-playback-dai-linkII2S3Si2s^cpucodect¶·speaker-codecmaxim,max98360aŸdefault­¸A ~,–Á·regulator-usb-p1-vbusregulator-fixed ‹,”¡vbus1°LK@ÈLK@ ; N¹Átwifi-pwrseqmmc-pwrseq-simpleŸdefault­º�2 D,6Ápwifi-wakeup gpio-keysŸdefault­»wowlan-event aWake on WiFi >, �$regulator-pp1000-edpbrdgregulator-fixed¡pp1000_edpbrdgŸdefault­¼ ; Y ‹, N^ÁJregulator-pp1800-edpbrdg-dxregulator-fixed¡pp1800_edpbrdg_dxŸdefault­½ ; Y ‹, N]ÁKregulator-pp3300-edp-dxregulator-fixed¡pp3300_edp_dxŸdefault­¾ ; Y ‹, N^ÁL compatibleinterrupt-parent#address-cells#size-cellschassis-typemodelovl0ovl-2l0rdma0rdma1i2c0i2c1i2c2i2c3i2c5mmc0mmc1serial0clocksclock-namesoperating-points-v2proc-supplyphandleopp-sharedopp-hzopp-microvoltrequired-oppscpudevice_typeregenable-methodclock-frequencydynamic-power-coefficientcapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-divclock-multclock-output-namesopp-supported-hwinterruptsdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxinput-enablebias-pull-downinput-schmitt-enablebias-disableoutput-lowdrive-strengthoutput-highbias-pull-up#power-domain-cellsdomain-supplymediatek,infracfgmediatek,disable-extrstmediatek,reset-by-toprguinterrupts-extendedAvdd-supplymediatek,dmic-modevsys-ldo1-supplyvsys-ldo2-supplyvsys-ldo3-supplyvsys-vcore-supplyvsys-vdram1-supplyvsys-vgpu-supplyvsys-vmodem-supplyvsys-vpa-supplyvsys-vproc11-supplyvsys-vproc12-supplyvsys-vs1-supplyvsys-vs2-supplyvs1-ldo1-supplyvs2-ldo1-supplyvs2-ldo2-supplyvs2-ldo3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-allowed-modesregulator-always-onregulator-coupled-withregulator-coupled-max-spreadstatusassigned-clocksassigned-clock-parentspinctrl-namespinctrl-0#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namembox-namesmboxespower-domainsspi-max-frequency#io-channel-cellsenable-gpiosreset-gpiosvdd10-supplyvdd18-supplyvdd33-supplyanalogix,lane0-swinganalogix,lane1-swingremote-endpointdata-lanespower-supplybacklighti2c-scl-internal-delay-nsgoodix,no-reset-during-suspendvcc33-supplyvcc-supplywakeup-sourcehid-descr-addr#sound-dai-cellsovdd-supplypwr18-supplylink-frequenciesAVDD-supplyDBVDD-supplyLDO1-IN-supplyMICVDD-supplyrealtek,jd-srcresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsreset-names#pwm-cellsmediatek,pad-selectgoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countlabelpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapcs-gpiosmediatek,apmixedsysmediatek,topckgenphysmediatek,syscon-wakeupvbus-supplypinctrl-1bus-widthnon-removablecap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqeno-sdno-sdiocap-mmc-hw-reseths400-ds-delaymediatek,hs400-ds-dly3vmmc-supplyvqmmc-supplypinctrl-2interrupt-namescap-sd-highspeedsd-uhs-sdr104sd-uhs-sdr50keep-power-in-suspendcap-sdio-irqno-mmcmmc-pwrseq#phy-cellsmediatek,discthbitspower-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusphy-namesmediatek,larbs#iommu-cellsmediatek,scppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathpwmsbrightness-levelsnum-interpolated-stepsdefault-brightness-levelnum-channelswakeup-delay-mswakeup-event-actionlinux,codelinux,input-typeenable-active-highvin-supplyregulator-boot-onno-mappinctrl-3pinctrl-4pinctrl-5pinctrl-6pinctrl-7pinctrl-8pinctrl-9pinctrl-10pinctrl-11pinctrl-12pinctrl-13pinctrl-14pinctrl-15pinctrl-16pinctrl-17pinctrl-18mediatek,adspmediatek,platformaudio-routinglink-namedai-formatmediatek,clk-providersound-daisdmode-gpiosgpiopost-power-on-delay-ms