Ð þí78.¨(r.p >,Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.1 Carrier BoardH2toradex,apalis-imx8-v1.1-ixora-v1.1toradex,apalis-imx8-v1.1fsl,imx8qmaliases=/bus@5b000000/mmc@5b010000B/bus@5b000000/mmc@5b020000G/bus@5b000000/mmc@5b030000L/bus@5a000000/serial@5a060000T/bus@5a000000/serial@5a070000\/bus@5a000000/serial@5a080000d/bus@5a000000/serial@5a090000 l/vpu@2c000000/vpu-core@2d080000 v/vpu@2c000000/vpu-core@2d090000 €/vpu@2c000000/vpu-core@2d0a0000"Š/bus@5a000000/i2c@5a820000/rtc@68�/system-controller/rtccpus cpu-mapcluster0core0”core1”core2”core3”cluster1core0”core1”cpu@0˜cpu2arm,cortex-a53¤ ¨¯psci½€Ê@Üé€ö@€ & :Icpu@1˜cpu2arm,cortex-a53¤ ¨¯psci½€Ê@Üé€ö@€ & :Icpu@2˜cpu2arm,cortex-a53¤ ¨¯psci½€Ê@Üé€ö@€ & :Icpu@3˜cpu2arm,cortex-a53¤ ¨¯psci½€Ê@Üé€ö@€ & :Icpu@100˜cpu2arm,cortex-a72¤ ¨¯psci½ÀÊ@Üé€ö@ & :Icpu@101˜cpu2arm,cortex-a72¤ ¨¯psci & :Il2-cache02cacheQ]¿Ì@ÞI l2-cache12cacheQ]¿Ì@ÞI opp-table-02operating-points-v2kI opp-600000000v#ÃF} » ‹Iðopp-896000000v5gà}B@‹Iðopp-1104000000vAÍ´}Èà‹Iðopp-1200000000vG†Œ}Èà‹Iðœopp-table-12operating-points-v2kI opp-600000000v#ÃF}B@‹Iðopp-1056000000v>ñH}B@‹Iðopp-1296000000vM?d}Èà‹Iðopp-1596000000v_!}Èà‹Iðœinterrupt-controller@51a00000 2arm,gic-v3P¤Q Q° R RR¨¹ Î Ipmu2arm,armv8-pmuv3 Îpsci 2arm,psci-1.0¶smctimer2arm,armv8-timer0Î   iommu@51400000 2arm,mmu-500¤Q@ÙìŒÎ                                 I°system-controller 2fsl,imx-scu ùtx0rx0gip3$  power-controller2fsl,imx8qm-scu-pdfsl,scu-pd I%clock-controller2fsl,imx8qm-clkfsl,scu-clkIpinctrl2fsl,imx8qm-iomuxc,defaultH:IÖadc0grp0D�À`ŒÀ`‹À`ŠÀ`I adc1grp0D‰À`ˆÀ`‡À`†À`I¢cam1gpiosgrp�DC!D!l!m!n!o!p!q!r!c!j!k!Idap1gpiosgrpTDd!!X!y!�!~!^!Iesai0gpiosgrpDh!i!Ifec1grpØDÿ ¦ ¥ ô ó õ ö ÷ ø ù ú û ü ý þ § 9 M`IÂfec1-sleepgrpØDÿ ¦@¥@ô@ó@õ@ö@÷@ø@ù@ú@û@ü@ý@þ@§@9 M@IÃfec2gpiosgrp¨D  ª!©!¨!!! ! ! !!!!!!Iflexcan0grpD“!’!I¤flexcan1grpD•!”!I¦flexcan2grpD—!–!I¨gpio1grp D !gpio2grp D !gpio3grp D !Igpio4grp D!Igpio5grp D–!I›gpio6grp D—!Iœgpio7grp DŽ!IÞgpio8grp D�!IÜgpiobklongrp D2!IÛgpiokeysgrp Dep!gpiousbhocngrp Dœ!Ihdmictrlgrp DNaI×lpi2c1grpD  I”lpi2c2grpD  I™lpi2c3grpD  Ižlpspi0grp0DuLvLwLxLI‚lpspi2grp0DzL{L|L}LI†lpuart0grpD  I‰lpuart1grp0D    I‹lpuart1ctrlgrp0D!! ! !Ilpuart2grpD6 7 I�lpuart3grp0D< =   I�lvds0i2c0gpiogrp D4!Ilvds1i2c0gpiosgrpD:!;!Imipidsi0-1engrp D5!Imipidsi1gpiosgrp DE!Imlbgpiosgrp D�!Immc1cdgrp DZ!I¶mmc1cdsleepgrp DZ!Iºpciebgrp$DÉ!Ê!Ë!pciesatarefclkgrp D¢!IÙpciewifirefclkgrp D\!IØpwm0grp D IÏpwm1grp D IÑpwm2grp D IÓpwm3grp D IÕpwmbklgrp D8 qspi1agpiosgrp`D³!²!±!°!¯!®!¬!­!Iresetmocigrp D&!sai1grp0DƒÆl€ÆL‚ÆL„ÆLsata1actgrp DY!Isd1cdgrp D£!I¾sgtl5000grp DsÆLsim0gpiosgrp0D!!!!Ispdif0grpD`Æ@_Æ@touchctrlgpiosgrp0DU!VAb!fAIátouchctrlidlegrp0D‰!ˆ!‡!†!Iàusbh1activegrpDÍÏÎÿusbh1idlegrpDÍÏÎÏusb3503agrp$D'A)!*AI•usbhengrp Dš!Ißusbotg1grpD™!›!I­usdhc1grp�DÑAÒ!Ó!Ô!Õ!Ö!×!Ø!Ù!Ú!ÛAÜ!I±usdhc1-100mhzgrp�DÑ@Ò Ó Ô Õ Ö × Ø Ù Ú Û@Ü I²usdhc1-200mhzgrp�DÑ@Ò Ó Ô Õ Ö × Ø Ù Ú Û@Ü I³usdhc1gpiosgrp Dê!Iusdhc2grp4bitgrpTDÞAß!à!á!ã!ä!Ÿ!Iµusdhc2-4bit100mhzgrpTDÞ@ß à á ã ä Ÿ!I·usdhc2-4bit200mhzgrpTDÞ@ß à á ã ä Ÿ!I¸usdhc2grp8bitgrp0Dæ!ç!è!é!usdhc2-8bit100mhzgrp0Dæ ç è é usdhc2-8bit200mhzgrp0Dæ ç è é usdhc2-4bitsleepgrpTDÞaßaàaáaãaäaŸ!I¹usdhc2-8bitsleepgrp0Dæaçaèaéausdhc3grpTDìAí!î!ï!ð!ñ!¡!I½usdhc3-100mhzgrpTDìAí!î!ï!ð!ñ!¡!I¿usdhc3-200mhzgrpTDìAí!î!ï!ð!ñ!¡!IÀwifigrpD+!H!wifipdngrp DL!IÝledsixoragrp0DïañaçaèaIãuart24forceoffgrp Dí!Irtc2fsl,imx8qxp-sc-rtcocotp2fsl,imx8qm-scu-ocotp Mmac@1c4¤Ämac@1c6¤Æthermal-sensor*2fsl,imx8qxp-sc-thermalfsl,imx-sc-thermalWI thermal-zonescpu0-thermalmúƒÐ‘ tripstrip0¡¡ø­ÐŸpassiveI!trip1¡ð­Ð Ÿcriticalcooling-mapsmap0¸!0½ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu1-thermalmúƒÐ‘ tripstrip0¡¡ø­ÐŸpassiveI"trip1¡ð­Ð Ÿcriticalcooling-mapsmap0¸"½ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu0-thermalmúƒÐ‘ �tripstrip0¡¡ø­ÐŸpassivetrip1¡ð­Ð Ÿcriticalgpu1-thermalmúƒÐ‘ ”tripstrip0¡¡ø­ÐŸpassivetrip1¡ð­Ð Ÿcriticaldrc0-thermalmúƒÐ‘ tripstrip0¡¡ø­ÐŸpassivetrip1¡ð­Ð Ÿcriticalclock-dummy 2fixed-clockÌ Üclk_dummyI+clock-esai1-rx 2fixed-clockÌ Üesai1_rx_clkIIclock-esai1-rx-hf 2fixed-clockÌÜesai1_rx_hf_clkIJclock-esai1-tx 2fixed-clockÌ Üesai1_tx_clkIKclock-esai1-tx-hf 2fixed-clockÌÜesai1_tx_hf_clkILclock-hdmi-rx-mclk 2fixed-clockÌ Ühdmi-rx-mclkIBclock-mlb-clk 2fixed-clockÌÜmlb_clkIAclock-sai5-rx-bclk 2fixed-clockÌ Üsai5_rx_bclkIUclock-sai5-tx-bclk 2fixed-clockÌ Üsai5_tx_bclkclock-sai6-rx-bclk 2fixed-clockÌ Üsai6_rx_bclkIVclock-sai6-tx-bclk 2fixed-clockÌ Üsai6_tx_bclkclock-spdif1-rx 2fixed-clockÌ Üspdif1_rxclock-controller-lvds-ipg 2fixed-clockÌn6Ülvds0_ipg_clkIlclock-controller-dsi-ipg 2fixed-clockÌ' Üdsi_ipg_clkIeclock-controller-mipi-div2-pll 2fixed-clockÌ¿ÌÜmipi_pll_div2_clkclock-cm41-ipg 2fixed-clockÌÞ) Ücm41_ipg_clkI&bus@38000000 2simple-bus ï88#i2c@3b230000$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c¤;#Î ¨$$öperipg 4n6'%4 5disabledintmux@3b4000002fsl,imx-intmux¤;@`Î'¹¨¨&öipg'%5 5disabledI#clock-controller@3b6300002fsl,imx8qxp-lpcg¤;c¨4&<(Ücm41_lpcg_i2c_clkcm41_lpcg_i2c_ipg_clk'%4I$clock-audio-ipg 2fixed-clockÌ'Üaudio_ipg_clkI/clock-ext-aud-mclk0 2fixed-clockÌÜext_aud_mclk0ICclock-ext-aud-mclk1 2fixed-clockÌÜext_aud_mclk1IDclock-esai0-rx 2fixed-clockÌ Üesai0_rx_clkIEclock-esai0-rx-hf 2fixed-clockÌÜesai0_rx_hf_clkIFclock-esai0-tx 2fixed-clockÌ Üesai0_tx_clkIGclock-esai0-tx-hf 2fixed-clockÌÜesai0_tx_hf_clkIHclock-spdif0-rx 2fixed-clockÌ Üspdif0_rxIMclock-sai0-rx-bclk 2fixed-clockÌ Üsai0_rx_bclkINclock-sai0-tx-bclk 2fixed-clockÌ Üsai0_tx_bclkIOclock-sai1-rx-bclk 2fixed-clockÌ Üsai1_rx_bclkIPclock-sai1-tx-bclk 2fixed-clockÌ Üsai1_tx_bclkIQclock-sai2-rx-bclk 2fixed-clockÌ Üsai2_rx_bclkIRclock-sai3-rx-bclk 2fixed-clockÌ Üsai3_rx_bclkISclock-sai4-rx-bclk 2fixed-clockÌ Üsai4_rx_bclkITbus@59000000 2simple-bus ïYYasrc@590000002fsl,imx8qm-asrc¤Y Îtd¨''()**+++++++++++++�ömemipgasrck_0asrck_1asrck_2asrck_3asrck_4asrck_5asrck_6asrck_7asrck_8asrck_9asrck_aasrck_basrck_casrck_dasrck_easrck_fspba`J,,,,,,OrxarxbrxctxatxbtxcY@gv'%ž 5disabledesai@590100002fsl,imx8qm-esai¤Y Ι¨---+öcoreextalfsysspba J,,Orxtx'%Ÿ 5disabledspdif@590200002fsl,imx8qm-spdif¤YÎÈÊ0¨.+.+++/+++:öcorerxtx0rxtx1rxtx2rxtx3rxtx4rxtx5rxtx6rxtx7spba J,, Orxtx'%  5disabledsai@590400002fsl,imx8qm-sai¤Y Î:¨0+0++öbusmclk0mclk1mclk2mclk3Orxtx J, , '%> 5disabledsai@590500002fsl,imx8qm-sai¤Y Î<¨1+1++öbusmclk0mclk1mclk2mclk3Orxtx J,,'%? 5disabledsai@590600002fsl,imx8qm-sai¤Y Î>¨2+2++öbusmclk0mclk1mclk2mclk3OrxJ,'%@ 5disabledsai@590700002fsl,imx8qm-sai¤Y ÎC¨3+3++öbusmclk0mclk1mclk2mclk3OrxJ,'%¢ 5disableddma-controller@591f00002fsl,imx8qm-edma¤Y‡’ŸðÎvwxyz{ššÉËÍÏ;;==?DFH '%þ%ÿ%%%%«%¬%­%®%¯%°%±%²%³%´%µ%¶%·%¸%¹I,clock-controller@594000002fsl,imx8qxp-lpcg¤Y@¨//<&Üasrc0_lpcg_ipg_clkasrc0_lpcg_mem_clk'%žI'clock-controller@594100002fsl,imx8qxp-lpcg¤YA ¨*/<(Üesai0_lpcg_extal_clkesai0_lpcg_ipg_clk'%ŸI-clock-controller@594200002fsl,imx8qxp-lpcg¤YB ¨*/<%Üspdif0_lpcg_tx_clkspdif0_lpcg_gclkw'% I.clock-controller@594400002fsl,imx8qxp-lpcg¤YD ¨* /<!Üsai0_lpcg_mclksai0_lpcg_ipg_clk'%>I0clock-controller@594500002fsl,imx8qxp-lpcg¤YE ¨* /<!Üsai1_lpcg_mclksai1_lpcg_ipg_clk'%?I1clock-controller@594600002fsl,imx8qxp-lpcg¤YF ¨*/<!Üsai2_lpcg_mclksai2_lpcg_ipg_clk'%@I2clock-controller@594700002fsl,imx8qxp-lpcg¤YG ¨*/<!Üsai3_lpcg_mclksai3_lpcg_ipg_clk'%¢I3clock-controller@595800002fsl,imx8qxp-lpcg¤YX ¨/// <4Üdsp_lpcg_adb_clkdsp_lpcg_ipg_clkdsp_lpcg_core_clk'% 5disabledI4clock-controller@595900002fsl,imx8qxp-lpcg¤YY¨/<Üdsp_ram_lpcg_ipg_clk'% 5disabledI5dsp@596e80002fsl,imx8qxp-dsp¤Yn€€¨454öipgocramcore '%â%ë%%ùtxdb0txdb1rxdb0rxdb106666 5disabledasrc@598000002fsl,imx8qm-asrc¤Y€ Î|d¨77()**+++++++++++++�ömemipgasrck_0asrck_1asrck_2asrck_3asrck_4asrck_5asrck_6asrck_7asrck_8asrck_9asrck_aasrck_basrck_casrck_dasrck_easrck_fspba`J888888OrxarxbrxctxatxbtxcY@gv'%Æ 5disabledsai@598200002fsl,imx8qm-sai¤Y‚ ÎI¨9+9++öbusmclk0mclk1mclk2mclk3 J88 Orxtx'%È 5disabledI<sai@598300002fsl,imx8qm-sai¤Yƒ ÎK¨:+:++öbusmclk0mclk1mclk2mclk3J8 Otx'%É 5disabledI=amix@598400002fsl,imx8qm-audmix¤Y„¨;öipg'%ʰ<= 5disabledmqs@598500002fsl,imx8qm-mqs¤Y…¨>> ömclkcore'%Ë 5disableddma-controller@599f00002fsl,imx8qm-edma¤YŸ ‡’ ŸÀ„Î~€�‚ƒJJLX'%Ì%Í%Î%Ï%Ð%Ñ%Ò%Ó%Ô%Õ%ÖI8clock-controller@59d000002fsl,imx8qxp-lpcg¤YÐ ¨E<Üaud_rec_clk0_lpcg_clk'%EI?clock-controller@59d100002fsl,imx8qxp-lpcg¤YÑ ¨ì<Üaud_rec_clk1_lpcg_clk'%ìI@clock-controller@59d200002fsl,imx8qxp-lpcg¤YÒ ¨E<Üaud_pll_div_clk0_lpcg_clk'%EI(clock-controller@59d300002fsl,imx8qxp-lpcg¤YÓ ¨ì<Üaud_pll_div_clk1_lpcg_clk'%ìI)clock-controller@59d500002fsl,imx8qxp-lpcg¤YÕ¨*<Ümclkout0_lpcg_clk'%ïclock-controller@59d600002fsl,imx8qxp-lpcg¤YÖ¨*<Ümclkout1_lpcg_clk'%ðacm@59e000002fsl,imx8qm-acm¤Yà¨'%í%î%ï%ð%E%ì%ž%Æ%Ÿ%Ç%>%?%@%¢%£%¤%È%É% %¡%Ë|¨?@()ABCDEFGHIJKLMMNOPQRSTUVŽöaud_rec_clk0_lpcg_clkaud_rec_clk1_lpcg_clkaud_pll_div_clk0_lpcg_clkaud_pll_div_clk1_lpcg_clkmlb_clkhdmi_rx_mclkext_aud_mclk0ext_aud_mclk1esai0_rx_clkesai0_rx_hf_clkesai0_tx_clkesai0_tx_hf_clkesai1_rx_clkesai1_rx_hf_clkesai1_tx_clkesai1_tx_hf_clkspdif0_rxspdif1_rxsai0_rx_bclksai0_tx_bclksai1_rx_bclksai1_tx_bclksai2_rx_bclksai3_rx_bclksai4_rx_bclksai5_tx_bclksai6_rx_bclkI*clock-controller@59c000002fsl,imx8qxp-lpcg¤YÀ¨//<&Üasrc1_lpcg_ipg_clkasrc1_lpcg_mem_clk'%ÆI7clock-controller@59c200002fsl,imx8qxp-lpcg¤Y ¨*/<!Üsai6_lpcg_mclksai6_lpcg_ipg_clk'%ÈI9clock-controller@59c300002fsl,imx8qxp-lpcg¤Yà ¨*/<!Üsai7_lpcg_mclksai7_lpcg_ipg_clk'%ÉI:clock-controller@59c400002fsl,imx8qxp-lpcg¤YĨ/<Üamix_lpcg_ipg_clk'%ÊI;clock-controller@59c500002fsl,imx8qxp-lpcg¤YÅ ¨*/<!Ümqs0_lpcg_mclkmqs0_lpcg_ipg_clk'%ËI>sai@590800002fsl,imx8qm-sai¤Y ÎE¨W+W++öbusmclk0mclk1mclk2mclk3OrxJ, µ'%£ 5disabledsai@590900002fsl,imx8qm-sai¤Y  ÎG¨X+X++öbusmclk0mclk1mclk2mclk3OtxJ, µ'%¤ 5disabledclock-controller@594800002fsl,imx8qxp-lpcg¤YH ¨*/<!Üsai4_lpcg_mclksai4_lpcg_ipg_clk'%£ 5disabledIWclock-controller@594900002fsl,imx8qxp-lpcg¤YI ¨*/<!Üsai5_lpcg_mclksai5_lpcg_ipg_clk'%¤ 5disabledIXesai@598100002fsl,imx8qm-esai¤Y� Λ¨YYY+öcoreextalfsysspba J88Orxtx'%Ç 5disabledclock-controller@59c100002fsl,imx8qxp-lpcg¤YÁ ¨*/<(Üesai1_lpcg_extal_clkesai1_lpcg_ipg_clk'%ÇIYvpu@2c000000 ï,,¤,'%5okay2nxp,imx8qm-vpumailbox@2d0000002fsl,imx6sx-mu¤- ÎØÂ'%5okayIZmailbox@2d0200002fsl,imx6sx-mu¤- ÎÙÂ'%5okayI]mailbox@2d0400002fsl,imx6sx-mu¤- ÎÚÂ'%5okayI`vpu-core@2d080000¤-2nxp,imx8q-vpu-decoder'% ùtx0tx1rx$ZZZ5okayÎ[\vpu-core@2d090000¤- 2nxp,imx8q-vpu-encoder'% ùtx0tx1rx$]]]5okayÎ^_vpu-core@2d0a0000¤- 2nxp,imx8q-vpu-encoder'% ùtx0tx1rx$```5okayÎabbus@53000000 2simple-bus ïSSgpu@53100000 2vivante,gc¤S Î@¨�� öcoreshader��)¹'2©ø€'%�bus@56220000 2simple-busc ïV"V"interrupt-controller@56220000&2fsl,imx8qxp-irqsteerfsl,imx-irqsteer¤V" Î;¹¨¨döipg'%‰Üè Icclock-controller@562230002fsl,imx8qxp-lpcg¤V"0'%‰¨e<Ümipi0_lis_lpcg_ipg_clkIdclock-controller@5622300c2fsl,imx8qxp-lpcg¤V"0 '%ЍŠe<*Ümipi0_pwm_lpcg_clkmipi0_pwm_lpcg_ipg_clkIhclock-controller@562230142fsl,imx8qxp-lpcg¤V"0¨f<Ümipi0_i2c0_lpcg_ipg_clk'%‹Ijclock-controller@562230182fsl,imx8qxp-lpcg¤V"0¨e<Ümipi0_i2c0_lpcg_ipg_s_clk'%‹Ifclock-controller@5622301c2fsl,imx8qxp-lpcg¤V"0 ¨‹<Ümipi0_i2c0_lpcg_clk'%‹Iiclock-controller@562230242fsl,imx8qxp-lpcg¤V"0$¨g<Ümipi0_i2c1_lpcg_ipg_clk'%Œclock-controller@562230282fsl,imx8qxp-lpcg¤V"0(¨e<Ümipi0_i2c1_lpcg_ipg_s_clk'%ŒIgclock-controller@5622302c2fsl,imx8qxp-lpcg¤V"0, ¨Œ<Ümipi0_i2c1_lpcg_clk'%Œpwm@562240002fsl,imx8qxp-pwmfsl,imx27-pwm¤V"@¨hhöipgper Šn6õ'%Š 5disabledi2c@56226000#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c¤V"` Ψijöperipgin6'%‹ 5disabledbus@56240000 2simple-bus ïV$V$kclock-controller@562430002fsl,imx8qxp-lpcg¤V$0Ülvds0_lis_lpcg_ipg_clk'%�¨l<Ioclock-controller@5624300c2fsl,imx8qxp-lpcg¤V$0 AÜlvds0_pwm_lpcg_clklvds0_pwm_lpcg_ipg_clklvds0_pwm_lpcg_32k_clk'%ލ l<Imclock-controller@562430102fsl,imx8qxp-lpcg¤V$0,Ülvds0_i2c0_lpcg_clklvds0_i2c0_lpcg_ipg_clk'%�¨ l<Inpwm@562440002fsl,imx8qxp-pwmfsl,imx27-pwm¤V$@öipgper Žn6õ'%Ž 5disabled¨mmi2c@56246000$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c¤V$` Îöperipg �n6'%� 5disabled¨nninterrupt-controller@56240000%2fsl,imx8qm-irqsteerfsl,imx-irqsteer¤V$ Î9¹¨¨oöipg'% Üè Ikclock-controller@562430142fsl,imx8qxp-lpcg¤V$0¨ l<,Ülvds0_i2c1_lpcg_clklvds0_i2c1_lpcg_ipg_clk'% Ipi2c@56247000#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c¤V$pÎ ¨ppöperipg  n6'%  5disabledbus@57220000 2simple-busq ïW"W"interrupt-controller@57220000%2fsl,imx8qm-irqsteerfsl,imx-irqsteer¤W" Î<¹¨¨röipg'%�Üè Iqclock-controller@572230002fsl,imx8qxp-lpcg¤W"0¨e<Ümipi1_lis_lpcg_ipg_clk'%�Irclock-controller@5722300c2fsl,imx8qxp-lpcg¤W"0 ¨Že<*Ümipi1_pwm_lpcg_clkmipi1_pwm_lpcg_ipg_clk'%ŽIuclock-controller@5722301c2fsl,imx8qxp-lpcg¤W"0 ¨�<Ümipi1_i2c0_lpcg_clk'%�Ivclock-controller@572230142fsl,imx8qxp-lpcg¤W"0¨s<Ümipi1_i2c0_lpcg_ipg_clk'%�Iwclock-controller@572230182fsl,imx8qxp-lpcg¤W"0¨e<Ümipi1_i2c0_lpcg_ipg_s_clk'%�Isclock-controller@572230242fsl,imx8qxp-lpcg¤W"0$¨t<Ümipi1_i2c1_lpcg_ipg_clk'%�clock-controller@572230282fsl,imx8qxp-lpcg¤W"0(¨e<Ümipi1_i2c1_lpcg_ipg_s_clk'%�Itclock-controller@5722302c2fsl,imx8qxp-lpcg¤W"0, ¨�<Ümipi1_i2c1_lpcg_clk'%�pwm@572240002fsl,imx8qxp-pwmfsl,imx27-pwm¤W"@¨uuöipgper Žn6õ'%Ž 5disabledi2c@57226000#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c¤W"` Îq¨vwöperipgvn6'%� 5disabledbus@57240000 2simple-busx ïW$W$interrupt-controller@57240000%2fsl,imx8qm-irqsteerfsl,imx-irqsteer¤W$ Î:¹¨¨yöipg'%Üè Ixclock-controller@572430002fsl,imx8qxp-lpcg¤W$0¨l<Ülvds1_lis_lpcg_ipg_clk'%Iyclock-controller@5724300c2fsl,imx8qxp-lpcg¤W$0 ¨l<*Ülvds1_pwm_lpcg_clklvds1_pwm_lpcg_ipg_clk'%Izclock-controller@572430102fsl,imx8qxp-lpcg¤W$0¨l<,Ülvds1_i2c0_lpcg_clklvds1_i2c0_lpcg_ipg_clk'%I{clock-controller@572430142fsl,imx8qxp-lpcg¤W$0¨l<,Ülvds1_i2c1_lpcg_clklvds1_i2c1_lpcg_ipg_clk'%I|pwm@572440002fsl,imx8qxp-pwmfsl,imx27-pwm¤W$@¨zzöipgper n6õ'% 5disabledi2c@57246000#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c¤W$` Ψ{{öperipg n6'% 5disabledi2c@57247000#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c¤W$pÎ ¨||öperipg n6'% 5disabledclock-img-ipg 2fixed-clockÌ ë Üimg_ipg_clkIbus@58000000 2simple-bus ïXXjpegdec@58400000¤X@ Î5¨}}}} ë ëÂ'%%�%2nxp,imx8qm-jpgdecnxp,imx8qxp-jpgdec5okayjpegenc@58450000¤XE Î1¨~~~~ ë ëÂ'%%…%2nxp,imx8qm-jpgencnxp,imx8qxp-jpgenc5okayclock-controller@585d00002fsl,imx8qxp-lpcg¤X]¨<0Üimg_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clk'%I}clock-controller@585f00002fsl,imx8qxp-lpcg¤X_¨<0Üimg_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clk'%I~clock-dma-ipg 2fixed-clockÌ' Üdma_ipg_clkI‘bus@5a000000 2simple-bus ïZZspi@5a0000002fsl,imx7ulp-spi¤Z  ÎP¨€€öperipg 5“‡'%5 J��Otxrx5okay,default:‚ ƒspi@5a0100002fsl,imx7ulp-spi¤Z  ÎQ¨„„öperipg 6“‡'%6 J��Otxrx 5disabledspi@5a0200002fsl,imx7ulp-spi¤Z  ÎR¨……öperipg 7“‡'%7 J��Otxrx5okay,default:† ƒ spi@5a0300002fsl,imx7ulp-spi¤Z  ÎS¨‡‡öperipg 8“‡'%8 J��Otxrx 5disabledserial@5a060000¤Z ÎY¨ˆˆ öipgbaud 9Ä´'%9Orxtx J� � 5okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuart,default:‰serial@5a070000¤Z ÎZ¨ŠŠ öipgbaud :Ä´'%:Orxtx J��5okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuart,default:‹serial@5a080000¤Z Î[¨ŒŒ öipgbaud ;Ä´'%;Orxtx J��5okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuart,default:�serial@5a090000¤Z  Î\¨ŽŽ öipgbaud <Ä´'%<Orxtx J��5okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuart,default:�pwm@5a1900002fsl,imx8qxp-pwmfsl,imx27-pwm¤Z Ψ��öipgper ¼n6õ'%¼dma-controller@5a1f00002fsl,imx8qm-edma¤Z‡’Π¡¢£¤¥¦§²³´µ¶·¸¹º»°'%@%A%B%C%D%E%F%G%H%I%J%K%L%M%N%O%P%Q%R%S%T%UŸ5okayI�clock-controller@5a4000002fsl,imx8qxp-lpcg¤Z@¨5‘< Üspi0_lpcg_clkspi0_lpcg_ipg_clk'%5I€clock-controller@5a4100002fsl,imx8qxp-lpcg¤ZA¨6‘< Üspi1_lpcg_clkspi1_lpcg_ipg_clk'%6I„clock-controller@5a4200002fsl,imx8qxp-lpcg¤ZB¨7‘< Üspi2_lpcg_clkspi2_lpcg_ipg_clk'%7I…clock-controller@5a4300002fsl,imx8qxp-lpcg¤ZC¨8‘< Üspi3_lpcg_clkspi3_lpcg_ipg_clk'%8I‡clock-controller@5a4600002fsl,imx8qxp-lpcg¤ZF¨9‘<'Üuart0_lpcg_baud_clkuart0_lpcg_ipg_clk'%9Iˆclock-controller@5a4700002fsl,imx8qxp-lpcg¤ZG¨:‘<'Üuart1_lpcg_baud_clkuart1_lpcg_ipg_clk'%:IŠclock-controller@5a4800002fsl,imx8qxp-lpcg¤ZH¨;‘<'Üuart2_lpcg_baud_clkuart2_lpcg_ipg_clk'%;IŒclock-controller@5a4900002fsl,imx8qxp-lpcg¤ZI¨<‘<'Üuart3_lpcg_baud_clkuart3_lpcg_ipg_clk'%<IŽclock-controller@5a5900002fsl,imx8qxp-lpcg¤ZY¨¼‘<(Üadma_pwm_lpcg_clkadma_pwm_lpcg_ipg_clk'%¼I�i2c@5a800000¤Z€@  Îܨ’’öperipg `n6'%` 5disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000¤Z�@  Îݨ““öperipg an6'%a5okay#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c,default:”̆ usb-hub@82smsc,usb3503a¤,default:•  – $—/}x@ @—i2c@5a820000¤Z‚@  ÎÞ¨˜˜öperipg bn6'%b5okay#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c,default:™Ì† touch@4a2atmel,maxtouch¤JšÎ,default:›œ @š 5disabledrtc@68 2st,m41t0¤h5okayi2c@5a830000¤Zƒ@  Îߨ��öperipg cn6'%c5okay#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c,default:žÌ† adc@5a8800002nxp,imx8qxp-adcL¤Zˆ Î𨟟öperipg en6'%e5okay,default: adc@5a8900002nxp,imx8qxp-adcL¤Z‰ Îñ¨¡¡öperipg fn6'%f5okay,default:¢Iâcan@5a8d00002fsl,imx8qm-flexcan¤Z� Î먣£öipgper ibZ'%i^m5okay,default:¤can@5a8e00002fsl,imx8qm-flexcan¤ZŽ Î쨥¥öipgper jbZ'%j^m5okay,default:¦can@5a8f00002fsl,imx8qm-flexcan¤Z� Îí¨§§öipgper kbZ'%k^m 5disabled,default:¨dma-controller@5a9f00002fsl,imx8qm-edma¤ZŸ!‡’ xΨ©ª«¬­®¯°±P'%l%m%n%o%p%q%r%s%t%uclock-controller@5ac000002fsl,imx8qxp-lpcg¤ZÀ¨`‘< Üi2c0_lpcg_clki2c0_lpcg_ipg_clk'%`I’clock-controller@5ac100002fsl,imx8qxp-lpcg¤ZÁ¨a‘< Üi2c1_lpcg_clki2c1_lpcg_ipg_clk'%aI“clock-controller@5ac200002fsl,imx8qxp-lpcg¤Z¨b‘< Üi2c2_lpcg_clki2c2_lpcg_ipg_clk'%bI˜clock-controller@5ac300002fsl,imx8qxp-lpcg¤Zèc‘< Üi2c3_lpcg_clki2c3_lpcg_ipg_clk'%cI�clock-controller@5ac800002fsl,imx8qxp-lpcg¤ZȨe‘< Üadc0_lpcg_clkadc0_lpcg_ipg_clk'%eIŸclock-controller@5ac900002fsl,imx8qxp-lpcg¤Zɨf‘< Üadc1_lpcg_clkadc1_lpcg_ipg_clk'%fI¡clock-controller@5acd00002fsl,imx8qxp-lpcg¤Zͨi‘‘ <5Ücan0_lpcg_pe_clkcan0_lpcg_ipg_clkcan0_lpcg_chi_clk'%iI£clock-controller@5a4a00002fsl,imx8qxp-lpcg¤ZJ¨=‘<'Üuart4_lpcg_baud_clkuart4_lpcg_ipg_clk'%=i2c@5a840000#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c¤Z„@ ÎX¨©©öperipg dn6'%d 5disabledclock-controller@5ac400002fsl,imx8qxp-lpcg¤ZĨd‘< Üi2c4_lpcg_clki2c4_lpcg_ipg_clk'%dI©clock-controller@5ace00002fsl,imx8qxp-lpcg¤ZΨj‘‘ <5Ücan1_lpcg_pe_clkcan1_lpcg_ipg_clkcan1_lpcg_chi_clk'%jI¥clock-controller@5acf00002fsl,imx8qxp-lpcg¤ZϨk‘‘ <5Ücan2_lpcg_pe_clkcan2_lpcg_ipg_clkcan2_lpcg_chi_clk'%kI§clock-conn-axi 2fixed-clockÌÞCU Üconn_axi_clkIÉclock-conn-ahb 2fixed-clockÌ ï!ª Üconn_ahb_clkIÊclock-conn-ipg 2fixed-clockÌ÷�Õ Üconn_ipg_clkIÈclock-conn-bch 2fixed-clockÌׄ Üconn_bch_clkbus@5b000000 2simple-bus ï[[usb@5b0d0000-2fsl,imx7ulp-usbfsl,imx6ul-usbfsl,imx27-usb¤[  Î {ª†«¨¬’£·'%5okay,default:­Ë×ãû usbmisc@5b0d020082fsl,imx7ulp-usbmiscfsl,imx7d-usbmiscfsl,imx6q-usbmisc¤[ I«usbphy@5b1000002fsl,imx7ulp-usbphy¤[¨¬'%5okay&®Iªmmc@5b010000 Îè¤[¨¯¯¯ öipgahbper'%ø5okay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhc 5°€",defaultstate_100mhzstate_200mhz:±<²F³PZmmc@5b020000 Îé¤[¨´´´ öipgahbper'%ùh}5okay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhc 5°€(,defaultstate_100mhzstate_200mhzsleep:µ¶<·¶F¸¶�¹ºP —»  mmc@5b030000 Îê¤[¨¼¼¼ öipgahbper'%ú 5disabled32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhc 5°€",defaultstate_100mhzstate_200mhz:½¾<¿¾FÀ¾P —š  ethernet@5b040000¤[0Î ¨ÁÁÁ Áöipgahbenet_clk_refptpûûæ²€sY@©»'%û5okay2fsl,imx8qm-fecfsl,imx6sx-fec 5°€,defaultsleep:Â<ÃÍÞÄ érgmii-idmdio ethernet-phy@72ethernet-phy-ieee802.3-c22¤—Îò @— IÄethernet@5b050000¤[0Î ¨ÅÅÅ Åöipgahbenet_clk_refptpüüæ²€sY@©»'%ü 5disabled2fsl,imx8qm-fecfsl,imx6sx-fec 5°€usb@5b1100002fsl,imx8qm-usb3¤[ ï(¨ÆÆÆÆÆölpmbusaclkipgcore æ²€'% 5disabledusb@5b120000 2cdns,usb3¤[[[ $otgxhcidev0Î.hostperipheralotgwakeup>ÇCcdns3,usb3-phyM 5disabledusb-phy@5b1600002nxp,salvo-phy¤[¨Æösalvo_phy_clk'%d 5disabledIÇclock-controller@5b2000002fsl,imx8qxp-lpcg¤[ ¨øÈÉ <9Üsdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clk'%øI¯clock-controller@5b2100002fsl,imx8qxp-lpcg¤[!¨ùÈÉ <9Üsdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clk'%ùI´clock-controller@5b2200002fsl,imx8qxp-lpcg¤["¨úÈÉ <9Üsdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clk'%úI¼clock-controller@5b2300002fsl,imx8qxp-lpcg¤[#0¨ûûÉûÈÈ< …Üenet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clk'%ûIÁclock-controller@5b2400002fsl,imx8qxp-lpcg¤[$0¨üüÉüÈÈ< …Üenet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clk'%üIÅclock-controller@5b2700002fsl,imx8qxp-lpcg¤['¨ÊÈ<"Üusboh3_ahb_clkusboh3_phy_ipg_clk'%I¬clock-controller@5b2800002fsl,imx8qxp-lpcg¤[(<0¨ÈÈÈMÜusb3_app_clkusb3_lpm_clkusb3_ipg_clkusb3_core_pclkusb3_phy_clkusb3_aclk'%IÆclock-controller@5b2900002fsl,imx8qxp-lpcg¤[) ¨  ÉÉ<'Ügpmi_bchgpmi_iogpmi_apbgpmi_bch_apb'% IÌclock-controller@5b2900042fsl,imx8qxp-lpcg¤[)¨É< Üapbhdma_hclk'% IËdma-controller@5b810000(2fsl,imx8qxp-dma-apbhfsl,imx28-dma-apbh¤[� 0·’¨Ë'% IÍnand-controller@5b8120002fsl,imx8qxp-gpmi-nand¤[� [�@ $gpmi-nandbch  Î.bch ¨ÌÌÌÌ'ögpmi_iogpmi_apbgpmi_bchgpmi_bch_apbJÍOrx-tx'%   úð€ 5disabledclock-lsio-bus 2fixed-clockÌõá Ülsio_bus_clkIÚbus@5d000000 2simple-bus  ï]]pwm@5d0000002fsl,imx27-pwm¤]öipgper¨ÎÎ ¿n6õ Î^5okay,default:Ïpwm@5d0100002fsl,imx27-pwm¤]öipgper¨ÐÐ Àn6õ Î_5okay,default:Ñpwm@5d0200002fsl,imx27-pwm¤]öipgper¨ÒÒ Án6õ Î`5okay,default:Ópwm@5d0300002fsl,imx27-pwm¤]öipgper¨ÔÔ Ân6õ Îa5okay,default:Õgpio@5d080000¤] Έo¹¨'%Ç2fsl,imx8qm-gpiofsl,imx35-gpio0‹ÖÖÖ$ô—MXM3_279MXM3_277MXM3_135MXM3_203MXM3_201MXM3_275MXM3_110MXM3_120MXM3_1/GPIO1MXM3_3/GPIO2MXM3_124MXM3_122MXM3_5/GPIO3MXM3_7/GPIO4MXM3_4MXM3_211MXM3_209MXM3_2MXM3_136MXM3_134MXM3_6MXM3_8MXM3_112MXM3_118MXM3_114MXM3_116I–gpio@5d090000¤]  Ήo¹¨'%È2fsl,imx8qm-gpiofsl,imx35-gpio@‹Ö(Ö2 Ö?ÖH}—MXM3_286MXM3_87MXM3_99MXM3_138MXM3_140MXM3_239MXM3_281MXM3_283MXM3_126MXM3_132MXM3_173MXM3_175MXM3_123I—hdmi-ctrl-hog,default:×§°CONNECTOR_IS_HDMIºgpio@5d0a0000¤]  Ίo¹¨'%É2fsl,imx8qm-gpiofsl,imx35-gpio0‹ÖPÖUÖh ®—MXM3_198MXM3_35MXM3_164MXM3_217MXM3_215MXM3_193MXM3_194MXM3_37MXM3_271MXM3_273MXM3_195MXM3_197MXM3_177MXM3_179MXM3_181MXM3_183MXM3_185MXM3_187I»pcie-wifi-hog,default:ا °PCIE_WIFI_CLKºgpio@5d0b0000¤]  ΋o¹¨'%Ê2fsl,imx8qm-gpiofsl,imx35-gpioÀ‹ÖrÖuÖ�֌֋֊։ֈևֆ֎֒þ—MXM3_191MXM3_221MXM3_225MXM3_223MXM3_227MXM3_200MXM3_235MXM3_231MXM3_229MXM3_233MXM3_204MXM3_196MXM3_202MXM3_305MXM3_307MXM3_309MXM3_311MXM3_315MXM3_317MXM3_319MXM3_321MXM3_15/GPIO7MXM3_63MXM3_17/GPIO8MXM3_12MXM3_14MXM3_16Iƒgpio@5d0c0000¤]  ÎŒo¹¨'%Ë2fsl,imx8qm-gpiofsl,imx35-gpio`‹Ö•Ö™ÖžÖ ¥Ö¬Öƺ—MXM3_18MXM3_11/GPIO5MXM3_13/GPIO6MXM3_274MXM3_84MXM3_262MXM3_96MXM3_190MXM3_269MXM3_251MXM3_253MXM3_295MXM3_299MXM3_301MXM3_297MXM3_293MXM3_291MXM3_289MXM3_287Išpcie-sata-hog,default:Ù§ °PCIE_SATA_CLKºgpio@5d0d0000¤]  Î�o¹¨'%Ì2fsl,imx8qm-gpiofsl,imx35-gpio€‹ÖËÖÍÖÒ ÖßÖãÖæÖìÖó/—gpio5-00gpio5-01gpio5-02gpio5-03gpio5-04gpio5-05gpio5-06gpio5-07gpio5-08gpio5-09gpio5-10gpio5-11gpio5-12gpio5-13gpio5-14gpio5-15gpio5-16gpio5-17gpio5-18gpio5-19LED-5-GREENLED-5-REDgpio5-22gpio5-23gpio5-24UART24-FORCEOFFgpio5-26LED-4-GREENgpio5-28LED-4-REDgpio5-30gpio5-31Iägpio@5d0e0000¤] ÎŽo¹¨'%Í2fsl,imx8qm-gpiofsl,imx35-gpio ‹Öõ Ö  v—MXM3_261MXM3_263MXM3_259MXM3_257MXM3_255MXM3_128MXM3_130MXM3_265MXM3_249MXM3_247MXM3_245MXM3_243gpio@5d0f0000¤] Î�o¹¨'%Î2fsl,imx8qm-gpiofsl,imx35-gpiospi@5d120000 2nxp,imx8qxp-fspi¤]$fspi_basefspi_mmap Î\¨íí öfspi_enfspi'%í 5disabledmailbox@5d1b0000¤] ΰ 5disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1c0000¤] αÂ,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-muI mailbox@5d1d0000¤] β 5disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1e0000¤] γ 5disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1f0000¤] δ 5disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d200000¤]  θÂ'%Ú 5disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d210000¤]! ιÂ'%Û 5disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d280000¤]( ÎÀÂ'%â2fsl,imx8qm-mufsl,imx6sx-muI6clock-controller@5d4000002fsl,imx8qxp-lpcg¤]@4¨¿¿¿Ú¿<hÜpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clk'%¿IÎclock-controller@5d4100002fsl,imx8qxp-lpcg¤]A4¨ÀÀÀÚÀ<hÜpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clk'%ÀIÐclock-controller@5d4200002fsl,imx8qxp-lpcg¤]B4¨ÁÁÁÚÁ<hÜpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clk'%ÁIÒclock-controller@5d4300002fsl,imx8qxp-lpcg¤]C4¨ÂÂÂÚÂ<hÜpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clk'%ÂIÔclock-controller@5d4400002fsl,imx8qxp-lpcg¤]D4¨ÃÃÃÚÃ<hÜpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clk'%Ãclock-controller@5d4500002fsl,imx8qxp-lpcg¤]E4¨ÄÄÄÚÄ<hÜpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clk'%Äclock-controller@5d4600002fsl,imx8qxp-lpcg¤]F4¨ÅÅÅÚÅ<hÜpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clk'%Åclock-controller@5d4700002fsl,imx8qxp-lpcg¤]G4¨ÆÆÆÚÆ<hÜpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clk'%ÆchosenÆ/bus@5a000000/serial@5a070000backlight2pwm-backlight,default:Û Ò-?XwžËÿä ý— 5disabledgpio-fan 2gpio-fan,default:Ü ƒ ¸regulator-ext-rgmii2regulator-fixed'% 2Z 52Z MVDD_EXT_RGMII (LDO1)regulator-state-mem\regulator-module-3v32regulator-fixed2Z 52Z M+V3.3regulator-module-3v3-avdd2regulator-fixed2Z 52Z  M+V3.3_AUDIOregulator-module-wifi2regulator-fixed,default:Ý u—z�Mwifi_pwrdn_fake_regulator¡dregulator-pcie-switch2regulator-fixed,default:Þ uƒzw@5w@ Mpcie_switch¼† regulator-usb-host-vbus2regulator-fixed,default:ß ušz�LK@5LK@MVCC_USBH(2|4)regulator-usb-hsic2regulator-fixed-ÆÀ5-ÆÀMusb-hsic-dummyregulator-usb-hsic12regulator-fixed-ÆÀ5-ÆÀMusb-phy-dummyI®reserved-memory ïdecoder-boot@84000000¤„ÍI[encoder1-boot@86000000¤† ÍI^encoder2-boot@86200000¤† ÍIam4@88000000¤ˆÍrpmsg@90200000¤� Ívdevbuffer@904000002shared-dma-pool¤�@Ídecoder-rpc@92000000¤’ ÍI\dsp@92400000¤’@Íencoder1-rpc@94400000¤”@pÍI_encoder2-rpc@94b00000¤”°pÍIblinux,cma2shared-dma-poolÔÀ<áóÅ<touchscreen2toradex,vf50-touchscreenƒÎ ,idledefault:àá<¢á üââââÈ » &» /» 8» 5disabledleds 2gpio-leds,default:ãled-1AGoffUstatus^ äled-2AGoffUstatus^ äled-3AGoffUstatus^ äled-4AGoffUstatus^ ä interrupt-parent#address-cells#size-cellsmodelcompatiblemmc0mmc1mmc2serial0serial1serial2serial3vpu-core0vpu-core1vpu-core2rtc0rtc1cpudevice_typeregclocksenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2#cooling-cellsphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterrupts#global-interrupts#iommu-cellsmbox-namesmboxes#power-domain-cells#clock-cellspinctrl-namespinctrl-0fsl,pinsread-only#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceclock-frequencyclock-output-namesrangesclock-namesassigned-clocksassigned-clock-ratespower-domainsstatusclock-indicesdmasdma-namesfsl,asrc-ratefsl,asrc-widthfsl,asrc-clk-map#dma-cellsdma-channelsdma-channel-maskdaisfsl,dataline#mbox-cellsmemory-regionfsl,channelfsl,num-irqs#pwm-cellscs-gpiosconnect-gpiosinitial-modeintn-gpiosrefclk-frequencyreset-gpios#io-channel-cellsfsl,clk-sourcefsl,scu-indexfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dwordadp-disablehnp-disableover-current-active-lowpower-active-highsrp-disable#index-cellsphy-3p0-supplyiommuspinctrl-1pinctrl-2bus-widthnon-removablefsl,tuning-start-tapfsl,tuning-steppinctrl-3cd-gpiosno-1-8-vfsl,num-tx-queuesfsl,num-rx-queuesfsl,magic-packetphy-handlephy-modemicrel,led-modereset-assert-usreset-deassert-usreg-namesinterrupt-namesphysphy-namescdns,on-chip-buff-size#phy-cellsgpio-controller#gpio-cellsgpio-rangesgpio-line-namesgpio-hogline-nameoutput-highstdout-pathbrightness-levelsdefault-brightness-levelenable-gpiosgpio-fan,speed-mapregulator-max-microvoltregulator-min-microvoltregulator-nameregulator-off-in-suspendgpioenable-active-highregulator-always-onregulator-settling-time-usstartup-delay-usno-mapalloc-rangeslinux,cma-defaultreusableio-channelsvf50-ts-min-pressurexp-gpiosxm-gpiosyp-gpiosym-gpioscolordefault-statefunctionfunction-enumerator