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׌0Œ0Œ0display-subsystem,rockchip,display-subsystem disabledfirmwarescmi ,arm,scmi-smc‚ protocol@14ó £opp-table-1,operating-points-v2£Fopp-200000000Ð ëÂ × øP øPB@opp-300000000Ðá£ × øP øPB@opp-400000000Ðׄ × øP øPB@opp-600000000Ð#ÃF × »  » B@opp-700000000Ð)¹' ×~ð~ðB@opp-800000000Ð/¯ ×B@B@B@hdmi-sound,simple-audio-card-HDMIDi2s] disabledsimple-audio-card,codecwsimple-audio-card,cpuw pmu,arm,cortex-a55-pmu0�äåæçŒ psci ,arm,psci-1.0smctimer,arm,armv8-timer0�   Ÿxin24m ,fixed-clock¶n6Æxin24m £xin32k ,fixed-clock¶€Æxin32kÙãdefault sram@10f000 ,mmio-sramóð ñðsram@0,arm,scmi-shmemó£sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcióü@÷›œ�øsatapmaliverxoob �_  sata-phy%okaysata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcióü€÷ ¡¢øsatapmaliverxoob �`  sata-phy% disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3óüÀ@ �©÷¦§¥øref_clksuspend_clkbus_clk3otg ;utmi_wide%D”Kokay  usb2-phyusb3-phydusb@fd000000,rockchip,rk3568-dwc3snps,dwc3óý@ �ª÷©ª¨øref_clksuspend_clkbus_clk3host  usb2-phyusb3-phy ;utmi_wide%D•K disabledinterrupt-controller@fd400000 ,arm,gic-v3 óý@ýF � k€‘ýA›(¦£usb@fd800000 ,generic-ehcióý€ �‚÷½¾¼ usbokayusb@fd840000 ,generic-ohcióý„ �ƒ÷½¾¼ usbokayusb@fd880000 ,generic-ehcióýˆ �…÷¿À¼ usbokayusb@fd8c0000 ,generic-ohcióýŒ �†÷¿À¼ usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdóý£Sio-domains&,rockchip,rk3568-pmu-io-voltage-domainokayµÃÑßíû %syscon@fdc50000óýÅ ,rockchip,rk3568-pipe-grfsyscon£¦syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdóýÆ£ syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconóýÈ£§syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconóýÉ£©syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconóýÊ€£ªsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconóýÊ€€£¬clock-controller@fdd00000,rockchip,rk3568-pmucruóýÐ 3£clock-controller@fdd20000,rockchip,rk3568-cruóýÒ÷øxin24m 3@ P€G†Œ ëÂe| £i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cóýÔ �.÷- øi2cpclkÙ!ãdefault okayregulator@1c ,tcs,tcs4525ó‰¦vdd_cpuµÉÛ 5óŒ0 ü "£regulator-state-mem+pmic@20,rockchip,rk809ó #� ãdefaultÙ$Des%%‹%—%£%¯%»%Ç%Ó%regulatorsDCDC_REG1 ¦vdd_logicµÉßÛ¡ ó™p qregulator-state-mem+DCDC_REG2¦vdd_gpuµßÛ¡ ó™p q£Gregulator-state-mem+DCDC_REG3¦vcc_ddrµÉßregulator-state-memöDCDC_REG4¦vdd_npußÛ¡ ó™p qregulator-state-mem+DCDC_REG5¦vcc_1v8µÉÛw@ów@£regulator-state-mem+LDO_REG1¦vdda0v9_imageÛ » ó » regulator-state-mem+LDO_REG2 ¦vdda_0v9µÉÛ » ó » regulator-state-mem+LDO_REG3 ¦vdda0v9_pmuµÉÛ » ó » regulator-state-memö » LDO_REG4 ¦vccio_acodecµÛ2Z ó2Z £regulator-state-mem+LDO_REG5 ¦vccio_sdÛw@ó2Z £regulator-state-mem+LDO_REG6 ¦vcc3v3_pmuµÉÛ2Z ó2Z £regulator-state-memö2Z LDO_REG7 ¦vcca_1v8µÉÛw@ów@£™regulator-state-mem+LDO_REG8 ¦vcca1v8_pmuµÉÛw@ów@regulator-state-memöw@LDO_REG9¦vcca1v8_imageÛw@ów@regulator-state-mem+SWITCH_REG1¦vcc_3v3µÉ£regulator-state-mem+SWITCH_REG2 ¦vcc3v3_sd£[regulator-state-mem+serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartóýÕ �t÷ ,øbaudclkapb_pclk*&&Ù'ãdefault/< disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý×÷ 0 øpwmpclkÙ(ãdefaultF disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý×÷ 0 øpwmpclkÙ)ãdefaultFokay£Çpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý× ÷ 0 øpwmpclkÙ*ãdefaultFokay£Èpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóý×0÷ 0 øpwmpclkÙ+ãdefaultF disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdóýÙpower-controller!,rockchip,rk3568-power-controllerQ £power-domain@7ó÷e,Qpower-domain@8ó÷ÌÍ e-./Qpower-domain@9ó ÷ÚÛÜ e012Qpower-domain@10ó ÷ñòe345678Qpower-domain@11ó ÷íe9Qpower-domain@13÷ó e:Qpower-domain@14ó÷ e;<=Qpower-domain@15ó÷ e>?@ABCDEQgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostóýæ@$�()' ljobmmugpu÷øgpubusþF%okay|G£–video-codec@fdea0400,rockchip,rk3568-vpuóýê �‹lvdpu÷îï øaclkhclkˆH% iommu@fdea0800,rockchip,rk3568-iommuóýê@ �Š øaclkiface÷îï% �£Hrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaóýë€ �Z÷óôõøaclkhclksclkD&$% œcoreaxiahb% video-codec@fdee0000,rockchip,rk3568-vepuóýî �@÷ýþ øaclkhclkˆI% iommu@fdee0800,rockchip,rk3568-iommuóýî@ �?÷ýþ øaclkiface% �£Immc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcóþ@ �d ÷ÁÂŽ�øbiuciuciu-driveciu-sample¨³ðÑ€Dëœreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aóþ� lmacirqeth_wake_irq@÷†‰‰ÇÃĉÈWøstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refDì œstmmaceth| ÁJÑâKõL disabledmdio,snps,dwmac-mdio stmmac-axi-config+£Jrx-queues-config;£Kqueue0tx-queues-configQ£Lqueue0vop@fe040000 óþ0þ@gvopgamma-lut �”(÷ÝÞßàá%øaclkhclkdclk_vp0dclk_vp1dclk_vp2ˆM% |  disabled,rockchip,rk3568-vopports £port@0ó port@1ó port@2ó iommu@fe043e00,rockchip,rk3568-iommu óþ>þ? �”÷ÝÞ øaclkiface�%  disabled£Mdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsióþ �Døpclk÷è dphyN% œapbD|  disabledports port@0óport@1ódsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsióþ �Eøpclk÷é dphyO% œapbD|  disabledports port@0óport@1óhdmi@fe0a0000,rockchip,rk3568-dw-hdmióþ  �-(÷æç“(Úøiahbisfrcecrefãdefault ÙPQR% /| q disabled£ports port@0óport@1óqos@fe128000,rockchip,rk3568-qossysconóþ€ £,qos@fe138080,rockchip,rk3568-qossysconóþ€€ £;qos@fe138100,rockchip,rk3568-qossysconóþ� £<qos@fe138180,rockchip,rk3568-qossysconóþ�€ £=qos@fe148000,rockchip,rk3568-qossysconóþ€ £-qos@fe148080,rockchip,rk3568-qossysconóþ€€ £.qos@fe148100,rockchip,rk3568-qossysconóþ� £/qos@fe150000,rockchip,rk3568-qossysconóþ £9qos@fe158000,rockchip,rk3568-qossysconóþ€ £3qos@fe158100,rockchip,rk3568-qossysconóþ� £4qos@fe158180,rockchip,rk3568-qossysconóþ�€ £5qos@fe158200,rockchip,rk3568-qossysconóþ‚ £6qos@fe158280,rockchip,rk3568-qossysconóþ‚€ £7qos@fe158300,rockchip,rk3568-qossysconóþƒ £8qos@fe180000,rockchip,rk3568-qossysconóþ qos@fe190000,rockchip,rk3568-qossysconóþ £>qos@fe190280,rockchip,rk3568-qossysconóþ€ £Bqos@fe190300,rockchip,rk3568-qossysconóþ £Cqos@fe190380,rockchip,rk3568-qossysconóþ€ £Dqos@fe190400,rockchip,rk3568-qossysconóþ £Eqos@fe198000,rockchip,rk3568-qossysconóþ€ £:qos@fe1a8000,rockchip,rk3568-qossysconóþ€ £0qos@fe1a8080,rockchip,rk3568-qossysconóþ€€ £1qos@fe1a8100,rockchip,rk3568-qossysconóþ� £2dfi@fe230000,rockchip,rk3568-dfióþ# � ‚Spcie@fe260000,rockchip,rk3568-pcie0óÀ@þ&ôgdbiapbconfig<�KJIHGlsyspmcmsglegacyerr�(÷�‚ƒ„…$øaclk_mstaclk_slvaclk_dbipclkauxçpci€™`¬TTTTºËÚéø  pcie-phy%Tñôôô ô à@@D¡œpipe okayãdefaultÙU  V Wlegacy-interrupt-controller€k �H£Tmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcóþ+@ �b ÷°±Š‹øbiuciuciu-driveciu-sample¨³ðÑ€DÔœresetokay&0 A#Jãdefault ÙXYZUc[ommc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcóþ,@ �c ÷²³Œ�øbiuciuciu-driveciu-sample¨³ðÑ€DÖœreset disabledspi@fe300000 ,rockchip,sfcóþ0@ �e÷xvøclk_sfchclk_sfcÙ\ãdefault disabledmmc@fe310000,rockchip,rk3568-dwcmshcóþ1 �@{}P ëÂn6(÷|zy{}øcorebusaxiblocktimerokay&³ ëÂ|ãdefaultÙ]^_`corng@fe388000,rockchip,rk3568-rngóþ8€@÷po øcoreahbDmokayi2s@fe400000,rockchip,rk3568-i2s-tdmóþ@ �4@=APFÏqFÏq÷?C9ømclk_txmclk_rxhclk*aŠtxDPQ œtx-mrx-m| q disabled£ i2s@fe410000,rockchip,rk3568-i2s-tdmóþA �5@EIPFÏqFÏq÷GK:ømclk_txmclk_rxhclk*aaŠrxtxDRS œtx-mrx-m| ãdefault0Ùbcdefghijklmq disabledi2s@fe420000,rockchip,rk3568-i2s-tdmóþB �6@MPFÏq÷OO;ømclk_txmclk_rxhclk*aaŠtxrxDTœtx-m| ãdefaultÙnopqq disabledi2s@fe430000,rockchip,rk3568-i2s-tdmóþC �7÷SW<ømclk_txmclk_rxhclk*aaŠtxrxDUV œtx-mrx-m| q disabledpdm@fe440000,rockchip,rk3568-pdmóþD �L÷ZYøpdm_clkpdm_hclk*a ŠrxÙrstuvwãdefaultDXœpdm-mq disabledspdif@fe460000,rockchip,rk3568-spdifóþF �f ømclkhclk÷_\*aŠtxãdefaultÙxq disableddma-controller@fe530000,arm,pl330arm,primecellóþS@� ”÷  øapb_pclk«£&dma-controller@fe550000,arm,pl330arm,primecellóþU@�”÷  øapb_pclk«£ai2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþZ �/÷HG øi2cpclkÙyãdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ[ �0÷JI øi2cpclkÙzãdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ\ �1÷LK øi2cpclkÙ{ãdefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ] �2÷NM øi2cpclkÙ|ãdefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cóþ^ �3÷PO øi2cpclkÙ}ãdefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtóþ` �•÷ øtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spióþa �g÷RQøspiclkapb_pclk*&&Štxrxãdefault Ù~€  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spióþb �h÷TSøspiclkapb_pclk*&&Štxrxãdefault Ù�‚ƒ  disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spióþc �i÷VUøspiclkapb_pclk*&&Štxrxãdefault Ù„…†  disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spióþd �j÷XWøspiclkapb_pclk*&&Štxrxãdefault Ù‡ˆ‰  disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartóþe �u÷øbaudclkapb_pclk*&&ÙŠãdefault/< disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartóþf �v÷# øbaudclkapb_pclk*&&Ù‹ãdefault/<okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartóþg �w÷'$øbaudclkapb_pclk*&&ÙŒãdefault/< disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartóþh �x÷+(øbaudclkapb_pclk*&& Ù�ãdefault/< disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartóþi �y÷/,øbaudclkapb_pclk*& & ÙŽãdefault/< disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþj �z÷30øbaudclkapb_pclk*& & Ù�ãdefault/< disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþk �{÷74øbaudclkapb_pclk*&&Ù�ãdefault/< disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþl �|÷;8øbaudclkapb_pclk*&&Ù‘ãdefault/< disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartóþm �}÷?<øbaudclkapb_pclk*&&Ù’ãdefault/< disabledthermal-zonescpu-thermal¶dÌèÚ“tripscpu_alert0êpöÐîpassive£”cpu_alert1ê$øöÐîpassivecpu_critêsöÐ îcriticalcooling-mapsmap0 ”0  ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal¶ÌèÚ“tripsgpu-thresholdêpöÐîpassivegpu-targetê$øöÐîpassive£•gpu-critêsöÐ îcriticalcooling-mapsmap0 • –ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcóþq �s@Pf@ ®`÷øtsadcapb_pclkD�‚×|  sãdefaultsleepÙ— ,˜ 6okay L c£“saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcóþr �]÷øsaradcapb_pclkD€ œsaradc-apb ~okay �™pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn÷ZY øpwmpclkÙšãdefaultF disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn÷ZY øpwmpclkÙ›ãdefaultF disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn ÷ZY øpwmpclkÙœãdefaultF disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþn0÷ZY øpwmpclkÙ�ãdefaultF disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo÷]\ øpwmpclkÙžãdefaultF disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo÷]\ øpwmpclkÙŸãdefaultF disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo ÷]\ øpwmpclkÙ ãdefaultF disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmóþo0÷]\ øpwmpclkÙ¡ãdefaultF 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsstatusarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsphy-supplyrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfdata-lanesstdout-pathfunctioncolorlinux,default-triggermax-brightnesspwmsenable-active-highgpio