Ð þíï_8ã°( ¯ãx %,embedfire,lubancat-2rockchip,rk35687EmbedFire LubanCat 2aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe2a0000ç/ethernet@fe010000ñ/mmc@fe2b0000ö/mmc@fe310000cpus cpu@0ûcpu,arm,cortex-a55 !psci/C€P@b€o€|@Ž€›¬· cpu@100ûcpu,arm,cortex-a55!psci/C€P@b€o€|@Ž€›¬· cpu@200ûcpu,arm,cortex-a55!psci/C€P@b€o€|@Ž€›¬· cpu@300ûcpu,arm,cortex-a55!psci/C€P@b€o€|@Ž€›¬· l3-cache,cache¿ËER@d·opp-table-0,operating-points-v2Ù·opp-408000000äQ– ë »  » Œ0ùœ@opp-600000000ä#ÃF ë »  » Œ0opp-816000000ä0£, ë »  » Œ0 opp-1104000000äAÍ´ ë »  » Œ0opp-1416000000äTfr ë »  » Œ0opp-1608000000ä_Ø" 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ref_clksuspend_clkbus_clkGhost usb2-phyusb3-phy Outmi_wide9X•_„okayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF • �¢³ýA½^å!È·usb@fd800000 ,generic-ehciý€ •‚ ½¾¼usb„okayusb@fd840000 ,generic-ohciý„ •ƒ ½¾¼usb„okayusb@fd880000 ,generic-ehciýˆ •… ¿À¼usb„okayusb@fd8c0000 ,generic-ohciýŒ •† ¿À¼usb„okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý·^io-domains&,rockchip,rk3568-pmu-io-voltage-domain„okay×åó+syscon@fdc50000ýÅ ,rockchip,rk3568-pipe-grfsyscon·­syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýÆ·syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýÈ·®syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýÉ·¯syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€·°syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€·³clock-controller@fdd00000,rockchip,rk3568-pmucruýÐ-9·clock-controller@fdd20000,rockchip,rk3568-cruýÒ  xin24m-9F V€G†Œ ëÂk‚·i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ •. -  i2cpclkí ÷default „okayregulator@1c ,tcs,tcs4525�¬vdd_cpu»Ïá 5ùŒ0ü&!·regulator-state-mem1pmic@20,rockchip,rk809 "•FHk–- mclk H÷defaultí#Jk|$ˆ$”$ $¬$¸$Ä$Ð$Ü$èregulatorsDCDC_REG1 ¬vdd_logic»Ïá¡ ù™pqöregulator-state-mem1DCDC_REG2¬vdd_gpu»Ïá¡ ù™pqö·Fregulator-state-mem1DCDC_REG3¬vcc_ddr»Ïöregulator-state-mem DCDC_REG4¬vdd_npu»Ïá¡ ù™pqöregulator-state-mem1DCDC_REG5¬vcc_1v8»Ïáw@ùw@·regulator-state-mem1LDO_REG1¬vdda0v9_imageÏ»á » ù » ·Zregulator-state-mem1LDO_REG2 ¬vdda_0v9»Ïá » ù » regulator-state-mem1LDO_REG3 ¬vdda0v9_pmu»Ïá » ù » regulator-state-mem % » LDO_REG4 ¬vccio_acodec»Ïá2Z ù2Z ·regulator-state-mem1LDO_REG5 ¬vccio_sd»Ïáw@ù2Z ·regulator-state-mem1LDO_REG6 ¬vcc3v3_pmu»Ïá2Z ù2Z ·regulator-state-mem %2Z LDO_REG7 ¬vcca_1v8»Ïáw@ùw@· regulator-state-mem1LDO_REG8 ¬vcca1v8_pmu»Ïáw@ùw@regulator-state-mem %w@LDO_REG9¬vcca1v8_image»Ïáw@ùw@·[regulator-state-mem1SWITCH_REG1¬vcc_3v3»Ï·regulator-state-mem1SWITCH_REG2 ¬vcc3v3_sd»Ï·aregulator-state-mem1serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ •t  , baudclkapb_pclkA%%í&÷defaultFS „disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkí'÷default] „disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkí(÷default] „disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0  pwmpclkí)÷default] „disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0  pwmpclkí*÷default] „disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerh ·power-domain@7 |+hpower-domain@8 ÌÍ |,-.hpower-domain@9  ÚÛÜ |/01hpower-domain@10  ñò|234567hpower-domain@11  í|8hpower-domain@13  |9hpower-domain@14  |:;<hpower-domain@15  |=>?@ABCDhgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$•()' ƒjobmmugpu  gpubus/E9„okay“F·�video-codec@fdea0400,rockchip,rk3568-vpuýê •‹ƒvdpu îï  aclkhclkŸG9 iommu@fdea0800,rockchip,rk3568-iommuýê@ •Š  aclkiface îï9 ¦·Grga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ •Z óôõ aclkhclksclkX&$% ³coreaxiahb9 video-codec@fdee0000,rockchip,rk3568-vepuýî •@ ýþ  aclkhclkŸH9 iommu@fdee0800,rockchip,rk3568-iommuýî@ •? ýþ  aclkiface9 ¦·Hmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ •d  ÁÂŽ� biuciuciu-driveciu-sample¿ÊðÑ€Xë³reset „disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ• ƒmacirqeth_wake_irq@ †‰‰ÇÃĉÈW stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refXì ³stmmaceth‚ØIèùJ K„okay(rgmii1output >LN dN † F‰†k‡Å÷defaultíMNOPQy!‚‹Rmdio,snps,dwmac-mdio phy@0,ethernet-phy-ieee802.3-c22·Rstmmac-axi-config– °·Irx-queues-configÀ·Jqueue0tx-queues-configÖ·Kqueue0vop@fe040000 þ0þ@ìvopgamma-lut •”( ÝÞßàá% aclkhclkdclk_vp0dclk_vp1dclk_vp2ŸS9 ‚„okay,rockchip,rk3568-vopFßàkports ·port@0 endpoint@2öT·\port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? •” ÝÞ  aclkiface¦9 „okay·Sdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ •D pclk èdphyU9 ³apbX‚ „disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ •E pclk édphyV9 ³apbX‚ „disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  •-( æç“(Ú iahbisfrcecref÷default íWXY9 F‚k„okayZ[·ports port@0endpointö\·Tport@1endpointö]·Óqos@fe128000,rockchip,rk3568-qossysconþ€ ·+qos@fe138080,rockchip,rk3568-qossysconþ€€ ·:qos@fe138100,rockchip,rk3568-qossysconþ� ·;qos@fe138180,rockchip,rk3568-qossysconþ�€ ·<qos@fe148000,rockchip,rk3568-qossysconþ€ ·,qos@fe148080,rockchip,rk3568-qossysconþ€€ ·-qos@fe148100,rockchip,rk3568-qossysconþ� ·.qos@fe150000,rockchip,rk3568-qossysconþ ·8qos@fe158000,rockchip,rk3568-qossysconþ€ ·2qos@fe158100,rockchip,rk3568-qossysconþ� ·3qos@fe158180,rockchip,rk3568-qossysconþ�€ ·4qos@fe158200,rockchip,rk3568-qossysconþ‚ ·5qos@fe158280,rockchip,rk3568-qossysconþ‚€ ·6qos@fe158300,rockchip,rk3568-qossysconþƒ ·7qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ·=qos@fe190280,rockchip,rk3568-qossysconþ€ ·Aqos@fe190300,rockchip,rk3568-qossysconþ ·Bqos@fe190380,rockchip,rk3568-qossysconþ€ ·Cqos@fe190400,rockchip,rk3568-qossysconþ ·Dqos@fe198000,rockchip,rk3568-qossysconþ€ ·9qos@fe1a8000,rockchip,rk3568-qossysconþ€ ·/qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ·0qos@fe1a8100,rockchip,rk3568-qossysconþ� ·1dfi@fe230000,rockchip,rk3568-dfiþ# • &^pcie@fe260000,rockchip,rk3568-pcie0À@þ&ôìdbiapbconfig<•KJIHGƒsyspmcmsglegacyerr3( �‚ƒ„…$ aclk_mstaclk_slvaclk_dbipclkauxûpci¢=`P____^o~�œ¤ pcie-phy9Tôôô ô à@@X¡³pipe „okay ®Lº`legacy-interrupt-controller¢� •H·_mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ •b  °±Š‹ biuciuciu-driveciu-sample¿ÊðÑ€XÔ³reset„okayÊÒÙãõ   a +÷defaultíbcdemmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ •c  ²³Œ� biuciuciu-driveciu-sample¿ÊðÑ€XÖ³reset „disabledspi@fe300000 ,rockchip,sfcþ0@ •e xv clk_sfchclk_sfcíf÷default „disabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 •F{}| V ëÂn6 ëÂ( |zy{} corebusaxiblocktimer„okayÙÊ ë 8 G÷default íghirng@fe388000,rockchip,rk3568-rngþ8€@ po  coreahbXm„okayi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ •4F=AVFÏqFÏq ?C9 mclk_txmclk_rxhclkAj UtxXPQ ³tx-mrx-m‚k „disabled· i2s@fe410000,rockchip,rk3568-i2s-tdmþA •5FEIVFÏqFÏq GK: mclk_txmclk_rxhclkAjj UrxtxXRS ³tx-mrx-m‚÷default0íklmnopqrstuvk„okay _i2s@fe420000,rockchip,rk3568-i2s-tdmþB •6FMVFÏq OO; mclk_txmclk_rxhclkAjj UtxrxXT³tx-m‚÷defaultíwxyzk „disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC •7 SW< mclk_txmclk_rxhclkAjj UtxrxXUV ³tx-mrx-m‚k „disabledpdm@fe440000,rockchip,rk3568-pdmþD •L ZY pdm_clkpdm_hclkAj  Urxí{|}~€÷defaultXX³pdm-mk „disabledspdif@fe460000,rockchip,rk3568-spdifþF •f  mclkhclk _\Aj Utx÷defaultí�k „disableddma-controller@fe530000,arm,pl330arm,primecellþS@•  z    apb_pclk ‘·%dma-controller@fe550000,arm,pl330arm,primecellþU@• z    apb_pclk ‘·ji2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ •/ HG  i2cpclkí‚÷default  „disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ •0 JI  i2cpclkíƒ÷default  „disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ •1 LK  i2cpclkí„÷default  „disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] •2 NM  i2cpclkí…÷default  „disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ •3 PO  i2cpclkí†÷default  „disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` ••   tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa •g RQ spiclkapb_pclkA%% Utxrx÷default 퇈‰  „disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb •h TS spiclkapb_pclkA%% Utxrx÷default 튋Œ  „disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc •i VU spiclkapb_pclkA%% Utxrx÷default í�Ž�  „disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd •j XW spiclkapb_pclkA%% Utxrx÷defaultí�  „disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe •u  baudclkapb_pclkA%%í‘÷defaultFS „disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf •v #  baudclkapb_pclkA%%í’÷defaultFS„okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg •w '$ baudclkapb_pclkA%%í“÷defaultFS „disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh •x +( baudclkapb_pclkA%% í”÷defaultFS „disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi •y /, baudclkapb_pclkA% % í•÷defaultFS „disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj •z 30 baudclkapb_pclkA% % í–÷defaultFS „disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk •{ 74 baudclkapb_pclkA%%í—÷defaultFS „disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl •| ;8 baudclkapb_pclkA%%í˜÷defaultFS „disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm •} ?< baudclkapb_pclkA%%í™÷defaultFS „disabledthermal-zonescpu-thermal œd ²è Àštripscpu_alert0 Ðp ÜÐpassive·›cpu_alert1 Ð$ø ÜÐpassivecpu_crit Ðs ÜÐ criticalcooling-mapsmap0 ç›0 ì ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal œ ²è Àštripsgpu-threshold Ðp ÜÐpassivegpu-target Ð$ø ÜÐpassive·œgpu-crit Ðs ÜÐ criticalcooling-mapsmap0 çœ ì�ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq •sFVf@ ®`  tsadcapb_pclkX�‚ׂ ûs÷defaultsleepíž Ÿ „okay 2 I·šsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr •]  saradcapb_pclkX€ ³saradc-apb d„okay v pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkí¡÷default] „disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkí¢÷default] „disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  ZY  pwmpclkí£÷default] „disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY  pwmpclkí¤÷default] „disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkí¥÷default]„okaypwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkí¦÷default] „disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ]\  pwmpclkí§÷default] „disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\  pwmpclkí¨÷default] „disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkí©÷default] „disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkíª÷default] „disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  `_  pwmpclkí«÷default] „disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_  pwmpclkí¬÷default] „disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "}  refapbpipeF"VõáXdzphy ‚­ ”® ª„okay·phy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~  refapbpipeF%VõáXɳphy ‚­ ”¯ ª„okay·phy@fe870000,rockchip,rk3568-csi-dphyþ‡ y pclk ªXº³apb‚ „disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ…  refpclk z ª9 ³apbX» „disabled·Umipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ†  refpclk { ª9 ³apbX¼ „disabled·Vusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ  phyclkÚclk_usbphy0_480m •‡ µ°-„okay·host-port ª„okay ű·otg-port ª„okay Ų·usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹  phyclkÚclk_usbphy1_480m •ˆ µ³-„okayhost-port ª„okay·otg-port ª„okay Å´·pinctrl,rockchip,rk3568-pinctrl‚&^ ·µgpio@fdd60000,rockchip,gpio-bankýÖ •! .  Ð ൠ ì�¢·"gpio@fe740000,rockchip,gpio-bankþt •" cd Ð ൠ ì�¢gpio@fe750000,rockchip,gpio-bankþu •# ef Ð àµ@  ì�¢·Ãgpio@fe760000,rockchip,gpio-bankþv •$ gh Ð àµ`  ì�¢·Lgpio@fe770000,rockchip,gpio-bankþw •% ij Ð ീ  ì�¢pcfg-pull-up ø·¸pcfg-pull-none ·¶pcfg-pull-none-drv-level-1  ·ºpcfg-pull-none-drv-level-2  ·¹pcfg-pull-none-drv-level-3  ·½pcfg-pull-up-drv-level-1 ø ·¼pcfg-pull-up-drv-level-2 ø ··pcfg-pull-none-smt  !·»acodecaudiopwmbt656bt1120camcan0can0m0-pins 6 ¶ ¶·Îcan1can1m0-pins 6¶¶·Ïcan2can2m0-pins 6 ¶ ¶·Ðcifclk32kclk32k-out0 6¶·cpuebcedpdpemmcemmc-bus8€ 6 · ········gemmc-clk 6··hemmc-cmd 6··ieth0eth1flashfspifspi-pins` 6¶¶¶¶¶¶·fgmac0gmac0-miim 6¶¶·Ègmac0-rx-bus20 6¶¶¶·Êgmac0-tx-bus20 6 ¹ ¹ ¶·Égmac0-rgmii-clk 6¶º·Ëgmac0-rgmii-bus@ 6¶¶¹¹·Ìgmac1gmac1m1-miim 6¶¶·Mgmac1m1-rx-bus20 6¶¶ ¶·Ogmac1m1-tx-bus20 6¹¹¶·Ngmac1m1-rgmii-clk 6¶º·Pgmac1m1-rgmii-bus@ 6¶¶¹¹·Qgpuhdmitxhdmitxm0-cec 6¶·Yhdmitx-scl 6¶·Whdmitx-sda 6¶·Xi2c0i2c0-xfer 6 » »· i2c1i2c1-xfer 6 » »·‚i2c2i2c2m0-xfer 6 »»·ƒi2c3i2c3m0-xfer 6»»·„i2c4i2c4m0-xfer 6 » »·…i2c5i2c5m0-xfer 6 » »·†i2s1i2s1m0-lrckrx 6¶·ni2s1m0-lrcktx 6¶·mi2s1m0-sclkrx 6¶·li2s1m0-sclktx 6¶·ki2s1m0-sdi0 6 ¶·oi2s1m0-sdi1 6 ¶·pi2s1m0-sdi2 6 ¶·qi2s1m0-sdi3 6¶·ri2s1m0-sdo0 6¶·si2s1m0-sdo1 6¶·ti2s1m0-sdo2 6 ¶·ui2s1m0-sdo3 6 ¶·vi2s2i2s2m0-lrcktx 6¶·xi2s2m0-sclktx 6¶·wi2s2m0-sdi 6¶·yi2s2m0-sdo 6¶·zi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk 6¶·{pdmm0-clk1 6¶·|pdmm0-sdi0 6 ¶·}pdmm0-sdi1 6 ¶·~pdmm0-sdi2 6 ¶·pdmm0-sdi3 6¶·€pmicpmic-int 6¸·#pmupwm0pwm0m0-pins 6¶·'pwm1pwm1m0-pins 6¶·(pwm2pwm2m0-pins 6¶·)pwm3pwm3-pins 6¶·*pwm4pwm4-pins 6¶·¡pwm5pwm5-pins 6¶·¢pwm6pwm6-pins 6¶·£pwm7pwm7-pins 6¶·¤pwm8pwm8m0-pins 6 ¶·¥pwm9pwm9m0-pins 6 ¶·¦pwm10pwm10m0-pins 6 ¶·§pwm11pwm11m0-pins 6¶·¨pwm12pwm12m0-pins 6¶·©pwm13pwm13m0-pins 6¶·ªpwm14pwm14m0-pins 6¶·«pwm15pwm15m0-pins 6¶·¬refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ 6·····bsdmmc0-clk 6··csdmmc0-cmd 6··dsdmmc0-det 6¸·esdmmc1sdmmc2spdifspdifm0-tx 6¶·�spi0spi0m0-pins0 6 ¶¶¶·‰spi0m0-cs0 6¶·‡spi0m0-cs1 6¶·ˆspi1spi1m0-pins0 6 ¶¶¶·Œspi1m0-cs0 6¶·Šspi1m0-cs1 6¶·‹spi2spi2m0-pins0 6¶¶¶·�spi2m0-cs0 6¶·�spi2m0-cs1 6¶·Žspi3spi3m1-pins0 6¶¶¶·�tsadctsadc-shutorg 6¶·žtsadc-pin 6¶·Ÿuart0uart0-xfer 6¸¸·&uart1uart1m0-xfer 6 ¸ ¸·‘uart2uart2m0-xfer 6¸¸·’uart3uart3m1-xfer 6¸¸·“uart4uart4m0-xfer 6¸¸·”uart5uart5m0-xfer 6¸¸·•uart6uart6m0-xfer 6¸¸·–uart7uart7m0-xfer 6¸¸·—uart8uart8m0-xfer 6¸¸·˜uart9uart9m0-xfer 6¸¸·™vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsuser-status-led-pin 6¶·Òusbvcc5v0-usb20-host-en 6¶·×vcc5v0-usb30-host-en 6¶·Øvcc5v0-otg-vbus-en 6¶·Ùpcievcc3v3-m2-pcie-en 6¶·Õvcc3v3-mini-pcie-en 6¶·Ösata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü –—˜ satapmaliverxoob •^¾ sata-phy'9„okaysyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconýÇ·Ñqos@fe190080,rockchip,rk3568-qossysconþ€ ·>qos@fe190100,rockchip,rk3568-qossysconþ ·?qos@fe190200,rockchip,rk3568-qossysconþ ·@syscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconýË€·¿phy@fe8c0000,rockchip,rk3568-pcie3-phyþŒ ª &'w refclk_mrefclk_npclkX¾³phy D¿„okay·Ápcie@fe270000,rockchip,rk3568-pcie 3( ˆ‰Š‹Œ$ aclk_mstaclk_slvaclk_dbipclkauxûpci<• Ÿž�œƒsyspmcmsglegacyerr¢=`PÀÀÀÀ^o~�œ¤Á pcie-phy90À@@þ'òTòòò ò à@@@ìdbiapbconfigX±³pipe „disabledlegacy-interrupt-controller�¢ •�·Àpcie@fe280000,rockchip,rk3568-pcie 3( ��‘’“$ aclk_mstaclk_slvaclk_dbipclkauxûpci<•¥¤£¢¡ƒsyspmcmsglegacyerr¢=`PÂÂÂÂ^o~�œ ¤Á pcie-phy90À€@þ(ðTððð ð à@€@ìdbiapbconfigXÁ³pipe„okay ®ÃºÄlegacy-interrupt-controller�¢ •¢·Âethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ*•ƒmacirqeth_wake_irq@ ‚……¸´µ…¹W stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refX× ³stmmaceth‚ØÅèùÆ Ç„okay(rgmii1output >ÃN dN † F…‚kƒ¶÷defaultíÈÉÊËÌy"‚‹Ímdio,snps,dwmac-mdio phy@0,ethernet-phy-ieee802.3-c22·Ístmmac-axi-config– °·Årx-queues-configÀ·Æqueue0tx-queues-configÖ·Çqueue0can@fe570000,rockchip,rk3568v2-canfdþW • A@  baudpclkXUT ³coreapb÷defaultíÎ „disabledcan@fe580000,rockchip,rk3568v2-canfdþX • CB  baudpclkXWV ³coreapb÷defaultíÏ „disabledcan@fe590000,rockchip,rk3568v2-canfdþY • ED  baudpclkXYX ³coreapb÷defaultíÐ „disabledphy@fe820000,rockchip,rk3568-naneng-combphyþ‚ |  refapbpipeFVõáXųphy ‚­ ”Ñ ª„okay·¾chosen Userial2:1500000n8leds ,gpio-ledsuser-led auser_led gheartbeat }on ´"÷defaultíÒhdmi-con,hdmi-connectoraportendpointöÓ·]dc-5v-regulator,regulator-fixed¬dc_5v»ÏáLK@ùLK@·Ôvcc3v3-sys-regulator,regulator-fixed ¬vcc3v3_sys»Ïá2Z ù2Z &!·$vcc5v0-sys-regulator,regulator-fixed ¬vcc5v0_sys»ÏáLK@ùLK@&Ô·!vcc3v3-m2-pcie-regulator,regulator-fixed ¬m2_pcie_3v3 ‹á2Z ù2Z  ´"íÕ÷default ž @&!·Ävcc3v3-mini-pcie-regulator,regulator-fixed ¬minipcie_3v3 ‹á2Z ù2Z  ILíÖ÷default žˆ&!·`vcc5v0-usb20-host-regulator,regulator-fixed¬vcc5v0_usb20_host ‹ I"í×÷default·´vcc5v0-usb30-host-regulator,regulator-fixed¬vcc5v0_usb30_host ‹ I"íØ÷default·±vcc5v0-otg-vbus-regulator,regulator-fixed¬vcc5v0_otg_vbus ‹áLK@ùLK@ I"íÙ÷default·² interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controller#sound-dai-cellsvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsophy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplyno-sdiono-mmcbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removabledma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfstdout-pathlabellinux,default-triggerdefault-stateenable-active-highstartup-delay-us