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Ërk817-clkout1rk817-clkout2"†èdefaultÞ#œ´Â$Î$Ú$æ$ò$þ$ $$"%regulatorsDCDC_REG1 .vdd_logic=Qcz¡ ’™pªqregulator-state-mem¿Ø » DCDC_REG2 .vdd_gpu_npu=Qcz¡ ’™pªq¨Dregulator-state-mem¿DCDC_REG3.vcc_ddr=Qcregulator-state-memôDCDC_REG4 .vcc3v3_sys=Qcz2Z ’2Z ¨dregulator-state-memôØ2Z LDO_REG1 .vcca1v8_pmu=Qzw@’w@¨regulator-state-memôØw@LDO_REG2 .vdda_0v9=Qz » ’ » ¨Zregulator-state-mem¿LDO_REG3 .vdda0v9_pmu=Qz » ’ » regulator-state-memôØ » LDO_REG4 .vccio_acodec=Qz2Z ’2Z ¨regulator-state-mem¿LDO_REG5 .vccio_sd=Qzw@’2Z ¨regulator-state-mem¿LDO_REG6 .vcc3v3_pmu=Qz2Z ’2Z ¨regulator-state-memôØ2Z LDO_REG7 .vcc_1v8_p=Qzw@’w@¨»regulator-state-mem¿LDO_REG8 .vcc1v8_dvp=Qzw@’w@regulator-state-mem¿LDO_REG9 .vcc2v8_dvp=Qz*¹€’*¹€regulator-state-mem¿BOOST .vcc5v_midu=QzLK@’LK@¨%regulator-state-mem¿OTG_SWITCH.vbusregulator-state-mem¿regulator@40,rockchip,rk8600ø@ .vdd_cpu=Qz ß4’5°ªü)$¨regulator-state-mem¿serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartøýÕ †tü ,ýbaudclkapb_pclk4&&Þ'èdefault9F udisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×ü 0 ýpwmpclkÞ(èdefaultP udisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×ü 0 ýpwmpclkÞ)èdefaultP udisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý× ü 0 ýpwmpclkÞ*èdefaultP udisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøý×0ü 0 ýpwmpclkÞ+èdefaultP udisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdøýÙpower-controller!,rockchip,rk3568-power-controller[ ¨power-domain@7øüo,[power-domain@8øüÌÍ o-./[power-domain@9ø üÚÛÜ o012[power-domain@10ø üñòo345678[power-domain@11ø üío9[power-domain@13üø o:[power-domain@14øü o;<=[power-domain@15øüo>?@AB[gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostøýæ@$†()' vjobmmugpuüýgpubus C*uokay†D¨›video-codec@fdea0400,rockchip,rk3568-vpuøýê †‹vvdpuüîï ýaclkhclk’E* iommu@fdea0800,rockchip,rk3568-iommuøýê@ †Š ýaclkifaceüîï* ™¨Erga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaøýë€ †ZüóôõýaclkhclksclkI&$% ¦coreaxiahb* video-codec@fdee0000,rockchip,rk3568-vepuøýî †@üýþ ýaclkhclk’F* iommu@fdee0800,rockchip,rk3568-iommuøýî@ †?üýþ ýaclkiface* ™¨Fmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ@ †d üÁÂŽ�ýbiuciuciu-driveciu-sample²½ðÑ€Ië¦reset udisabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aøþ† vmacirqeth_wake_irq@ü†‰‰ÇÃĉÈWýstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refIì ¦stmmaceth� ËGÛìHÿIuokayS‰†x‡Åinput(J 3rgmii-id<èdefaultÞKLMNOPmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22øèdefaultÞQGN WÃP iR¨Jstmmac-axi-configu�¨Grx-queues-configŸ¨Hqueue0tx-queues-configµ¨Iqueue0vop@fe040000 øþ0þ@Ëvopgamma-lut †”(üÝÞßàá%ýaclkhclkdclk_vp0dclk_vp1dclk_vp2’S* � uokay,rockchip,rk3566-vopSßàxports ¨port@0ø endpoint@2øÕT¨\port@1ø port@2ø iommu@fe043e00,rockchip,rk3568-iommu øþ>þ? †”üÝÞ ýaclkiface™* uokay¨Sdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ †Dýpclküèdphy U* ¦apbI�  udisabledports port@0øport@1ødsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ †Eýpclküédphy V* ¦apbI�  udisabledports port@0øport@1øhdmi@fe0a0000,rockchip,rk3568-dw-hdmiøþ  †-(üæç“(Úýiahbisfrcecrefèdefault ÞWXY* 9� åuokayöZ[¨ports port@0øendpointÕ\¨Tport@1øendpointÕ]¨¹qos@fe128000,rockchip,rk3568-qossysconøþ€ ¨,qos@fe138080,rockchip,rk3568-qossysconøþ€€ ¨;qos@fe138100,rockchip,rk3568-qossysconøþ� ¨<qos@fe138180,rockchip,rk3568-qossysconøþ�€ ¨=qos@fe148000,rockchip,rk3568-qossysconøþ€ ¨-qos@fe148080,rockchip,rk3568-qossysconøþ€€ ¨.qos@fe148100,rockchip,rk3568-qossysconøþ� ¨/qos@fe150000,rockchip,rk3568-qossysconøþ ¨9qos@fe158000,rockchip,rk3568-qossysconøþ€ ¨3qos@fe158100,rockchip,rk3568-qossysconøþ� ¨4qos@fe158180,rockchip,rk3568-qossysconøþ�€ ¨5qos@fe158200,rockchip,rk3568-qossysconøþ‚ ¨6qos@fe158280,rockchip,rk3568-qossysconøþ‚€ ¨7qos@fe158300,rockchip,rk3568-qossysconøþƒ ¨8qos@fe180000,rockchip,rk3568-qossysconøþ qos@fe190000,rockchip,rk3568-qossysconøþ ¨>qos@fe190280,rockchip,rk3568-qossysconøþ€ ¨?qos@fe190300,rockchip,rk3568-qossysconøþ ¨@qos@fe190380,rockchip,rk3568-qossysconøþ€ ¨Aqos@fe190400,rockchip,rk3568-qossysconøþ ¨Bqos@fe198000,rockchip,rk3568-qossysconøþ€ ¨:qos@fe1a8000,rockchip,rk3568-qossysconøþ€ ¨0qos@fe1a8080,rockchip,rk3568-qossysconøþ€€ ¨1qos@fe1a8100,rockchip,rk3568-qossysconøþ� ¨2dfi@fe230000,rockchip,rk3568-dfiøþ# † ^pcie@fe260000,rockchip,rk3568-pcie0øÀ@þ&ôËdbiapbconfig<†KJIHGvsyspmcmsglegacyerr#(ü�‚ƒ„…$ýaclk_mstaclk_slvaclk_dbipclkauxìpci“-`@____N_n}Œ”  pcie-phy*Töôôô ô à@@I¡¦pipe  udisabledlegacy-interrupt-controller“~ †H¨_mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ+@ †b ü°±Š‹ýbiuciuciu-driveciu-sample²½ðÑ€IÔ¦resetuokayž¨¹èdefaultÞ`abcÄdÐmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ,@ †c ü²³Œ�ýbiuciuciu-driveciu-sample²½ðÑ€IÖ¦reset udisabledspi@fe300000 ,rockchip,sfcøþ0@ †eüxvýclk_sfchclk_sfcÞeèdefault udisabledmmc@fe310000,rockchip,rk3568-dwcmshcøþ1 †S{}c ëÂn6(ü|zy{}ýcorebusaxiblocktimer udisabledrng@fe388000,rockchip,rk3568-rngøþ8€@üpo ýcoreahbIm udisabledi2s@fe400000,rockchip,rk3568-i2s-tdmøþ@ †4S=AcFÏqFÏqü?C9ýmclk_txmclk_rxhclk4fÝtxIPQ ¦tx-mrx-m� åuokay¨ i2s@fe410000,rockchip,rk3568-i2s-tdmøþA †5SEIcFÏqFÏqüGK:ýmclk_txmclk_rxhclk4ffÝrxtxIRS ¦tx-mrx-m� èdefault0Þghijklmnopqrå udisabledi2s@fe420000,rockchip,rk3568-i2s-tdmøþB †6SMcFÏqüOO;ýmclk_txmclk_rxhclk4ffÝtxrxIT¦tx-m� èdefaultÞstuvå udisabledi2s@fe430000,rockchip,rk3568-i2s-tdmøþC †7üSW<ýmclk_txmclk_rxhclk4ffÝtxrxIUV ¦tx-mrx-m� å udisabledpdm@fe440000,rockchip,rk3568-pdmøþD †LüZYýpdm_clkpdm_hclk4f ÝrxÞwxyz{|èdefaultIX¦pdm-må udisabledspdif@fe460000,rockchip,rk3568-spdiføþF †f ýmclkhclkü_\4fÝtxèdefaultÞ}å udisableddma-controller@fe530000,arm,pl330arm,primecelløþS@† çü  ýapb_pclkþ¨&dma-controller@fe550000,arm,pl330arm,primecelløþU@†çü  ýapb_pclkþ¨fi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþZ †/üHG ýi2cpclkÞ~èdefault  udisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ[ †0üJI ýi2cpclkÞèdefault  udisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ\ †1üLK ýi2cpclkÞ€èdefault  udisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ] †2üNM ýi2cpclkÞ�èdefault  udisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ^ †3üPO ýi2cpclkÞ‚èdefault  udisabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtøþ` †•ü ýtclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiøþa †güRQýspiclkapb_pclk4&&Ýtxrxèdefault Þƒ„…  udisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiøþb †hüTSýspiclkapb_pclk4&&Ýtxrxèdefault Þ†‡ˆ  udisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiøþc †iüVUýspiclkapb_pclk4&&Ýtxrxèdefault Þ‰Š‹  udisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiøþd †jüXWýspiclkapb_pclk4&&Ýtxrxèdefault ÞŒ�Ž  udisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartøþe †uüýbaudclkapb_pclk4&&Þ�èdefault9F udisabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartøþf †vü# ýbaudclkapb_pclk4&&Þ�èdefault9Fuokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartøþg †wü'$ýbaudclkapb_pclk4&&Þ‘èdefault9F udisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartøþh †xü+(ýbaudclkapb_pclk4&& Þ’èdefault9F udisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartøþi †yü/,ýbaudclkapb_pclk4& & Þ“èdefault9F udisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþj †zü30ýbaudclkapb_pclk4& & Þ”èdefault9F udisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþk †{ü74ýbaudclkapb_pclk4&&Þ•èdefault9F udisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþl †|ü;8ýbaudclkapb_pclk4&&Þ–èdefault9F udisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþm †}ü?<ýbaudclkapb_pclk4&&Þ—èdefault9F udisabledthermal-zonescpu-thermal d è -˜tripscpu_alert0 =p IÐópassive¨™cpu_alert1 =$ø IÐópassivecpu_crit =s IÐ ócriticalcooling-mapsmap0 T™0 Y ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal  è -˜tripsgpu-threshold =p IÐópassivegpu-target =$ø IÐópassive¨šgpu-crit =s IÐ ócriticalcooling-mapsmap0 Tš Y›ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcøþq †sScf@ ®`üýtsadcapb_pclkI�‚×�  hsèdefaultsleepÞœ � ‰uokay Ÿ ¶¨˜saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcøþr †]üýsaradcapb_pclkI€ ¦saradc-apb Ñuokay ãžpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY ýpwmpclkÞŸèdefaultP udisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY ýpwmpclkÞ èdefaultP udisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn üZY ýpwmpclkÞ¡èdefaultP udisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn0üZY ýpwmpclkÞ¢èdefaultP udisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ ýpwmpclkÞ£èdefaultP udisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ ýpwmpclkÞ¤èdefaultP udisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo ü]\ ýpwmpclkÞ¥èdefaultP udisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo0ü]\ ýpwmpclkÞ¦èdefaultP udisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ ýpwmpclkÞ§èdefaultP udisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ ýpwmpclkÞ¨èdefaultP udisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp ü`_ ýpwmpclkÞ©èdefaultP udisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp0ü`_ ýpwmpclkÞªèdefaultP udisabledphy@fe830000,rockchip,rk3568-naneng-combphyøþƒü"} ýrefapbpipeS"cõáIǦphy ï« ¬ uokay¨phy@fe840000,rockchip,rk3568-naneng-combphyøþ„ü%~ ýrefapbpipeS%cõáIɦphy ï« ­  udisabled¨phy@fe870000,rockchip,rk3568-csi-dphyøþ‡üyýpclk Iº¦apb�  udisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyøþ… ýrefpclküz * ¦apbI» udisabled¨Umipi-dphy@fe860000,rockchip,rk3568-dsi-dphyøþ† ýrefpclkü{ * ¦apbI¼ udisabled¨Vusb2phy@fe8a0000,rockchip,rk3568-usb2phyøþŠüýphyclkËclk_usbphy0_480m †‡ "®uokay¨host-port uokay¨otg-port uokay¨usb2phy@fe8b0000,rockchip,rk3568-usb2phyøþ‹üýphyclkËclk_usbphy1_480m †ˆ "¯ udisabledhost-port  udisabled¨otg-port  udisabled¨pinctrl,rockchip,rk3568-pinctrl� ^ ö¨°gpio@fdd60000,rockchip,gpio-bankøýÖ †!ü.  2 B°  N~“B Zpin-10 [GPIO0_D0]pin-08 [GPIO0_D1]¨"gpio@fe740000,rockchip,gpio-bankøþt †"ücd 2 B°  N~“S Zpin-03 [GPIO1_A0]pin-05 [GPIO1_A1]pin-37 [GPIO1_A4]gpio@fe750000,rockchip,gpio-bankøþu †#üef 2 B°@  N~“ Zgpio@fe760000,rockchip,gpio-bankøþv †$ügh 2 B°`  N~“0 Zpin-11 [GPIO3_A1]pin-13 [GPIO3_A2]pin-12 [GPIO3_A3]pin-35 [GPIO3_A4]pin-40 [GPIO3_A5]pin-38 [GPIO3_A6]pin-36 [GPIO3_A7]pin-15 [GPIO3_B0]pin-16 [GPIO3_B1]pin-18 [GPIO3_B2]pin-29 [GPIO3_B3]pin-31 [GPIO3_B4]pin-22 [GPIO3_C1]pin-32 [GPIO3_C2]pin-33 [GPIO3_C3]pin-07 [GPIO3_C4]¨Rgpio@fe770000,rockchip,gpio-bankøþw †%üij 2 B°€  N~“† Zpin-27 [GPIO4_B2]pin-28 [GPIO4_B3]pin-23 [GPIO4_C2]pin-19 [GPIO4_C3]pin-21 [GPIO4_C5]pin-24 [GPIO4_C6]pcfg-pull-up j¨³pcfg-pull-none w¨±pcfg-pull-none-drv-level-1 w „¨µpcfg-pull-none-drv-level-2 w „¨´pcfg-pull-none-drv-level-3 w „¨¸pcfg-pull-up-drv-level-1 j „¨·pcfg-pull-up-drv-level-2 j „¨²pcfg-pull-none-smt w “¨¶acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ¨±¨cpuebcedpdpemmceth0eth1flashfspifspi-pins` ¨±±±±±±¨egmac0gmac1gmac1m1-miim ¨±±¨Kgmac1m1-clkinout ¨±¨Pgmac1m1-rx-bus20 ¨±± ±¨Mgmac1m1-tx-bus20 ¨´´±¨Lgmac1m1-rgmii-clk ¨±µ¨Ngmac1m1-rgmii-bus@ ¨±±´´¨Ogmac1-rstn ¨±¨Qgpuhdmitxhdmitxm0-cec ¨±¨Yhdmitx-scl ¨±¨Whdmitx-sda ¨±¨Xi2c0i2c0-xfer ¨ ¶ ¶¨!i2c1i2c1-xfer ¨ ¶ ¶¨~i2c2i2c2m0-xfer ¨ ¶¶¨i2c3i2c3m0-xfer ¨¶¶¨€i2c4i2c4m0-xfer ¨ ¶ ¶¨�i2c5i2c5m0-xfer ¨ ¶ ¶¨‚i2s1i2s1m0-lrckrx ¨±¨ji2s1m0-lrcktx ¨±¨ii2s1m0-sclkrx ¨±¨hi2s1m0-sclktx ¨±¨gi2s1m0-sdi0 ¨ ±¨ki2s1m0-sdi1 ¨ ±¨li2s1m0-sdi2 ¨ ±¨mi2s1m0-sdi3 ¨±¨ni2s1m0-sdo0 ¨±¨oi2s1m0-sdo1 ¨±¨pi2s1m0-sdo2 ¨ ±¨qi2s1m0-sdo3 ¨ ±¨ri2s2i2s2m0-lrcktx ¨±¨ti2s2m0-sclktx ¨±¨si2s2m0-sdi ¨±¨ui2s2m0-sdo ¨±¨vi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ¨±¨wpdmm0-clk1 ¨±¨xpdmm0-sdi0 ¨ ±¨ypdmm0-sdi1 ¨ ±¨zpdmm0-sdi2 ¨ ±¨{pdmm0-sdi3 ¨±¨|pmicpmic-int-l ¨³¨#pmupwm0pwm0m0-pins ¨±¨(pwm1pwm1m0-pins ¨±¨)pwm2pwm2m0-pins ¨±¨*pwm3pwm3-pins ¨±¨+pwm4pwm4-pins ¨±¨Ÿpwm5pwm5-pins ¨±¨ pwm6pwm6-pins ¨±¨¡pwm7pwm7-pins ¨±¨¢pwm8pwm8m0-pins ¨ ±¨£pwm9pwm9m0-pins ¨ ±¨¤pwm10pwm10m0-pins ¨ ±¨¥pwm11pwm11m0-pins ¨±¨¦pwm12pwm12m0-pins ¨±¨§pwm13pwm13m0-pins ¨±¨¨pwm14pwm14m0-pins ¨±¨©pwm15pwm15m0-pins ¨±¨ªrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ¨²²²²¨`sdmmc0-clk ¨²¨asdmmc0-cmd ¨²¨bsdmmc0-det ¨³¨csdmmc1sdmmc2spdifspdifm0-tx ¨±¨}spi0spi0m0-pins0 ¨ ±±±¨…spi0m0-cs0 ¨±¨ƒspi0m0-cs1 ¨±¨„spi1spi1m0-pins0 ¨ ±±±¨ˆspi1m0-cs0 ¨±¨†spi1m0-cs1 ¨±¨‡spi2spi2m0-pins0 ¨±±±¨‹spi2m0-cs0 ¨±¨‰spi2m0-cs1 ¨±¨Šspi3spi3m0-pins0 ¨ ±± ±¨Žspi3m0-cs0 ¨±¨Œspi3m0-cs1 ¨±¨�tsadctsadc-shutorg ¨±¨œtsadc-pin ¨±¨�uart0uart0-xfer ¨³³¨'uart1uart1m0-xfer ¨ ³ ³¨�uart2uart2m0-xfer ¨³³¨�uart3uart3m0-xfer ¨³³¨‘uart4uart4m0-xfer ¨³³¨’uart5uart5m0-xfer ¨³³¨“uart6uart6m0-xfer ¨³³¨”uart7uart7m0-xfer ¨³³¨•uart8uart8m0-xfer ¨³³¨–uart9uart9m0-xfer ¨³³¨—vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsuser-led2 ¨±¨ºchosen ¶serial2:1500000n8hdmi-con,hdmi-connectoródportendpointÕ¹¨]leds ,gpio-ledsèdefaultÞºled-green  Èon Öheartbeat o" ßheartbeatregulator-1v8-vcc,regulator-fixed.vcc_1v8=Qzw@’w@)»¨regulator-1v8-vcca,regulator-fixed .vcca_1v8=Qzw@’w@)»¨žregulator-1v8-vcca-image,regulator-fixed.vcca1v8_image=Qzw@’w@)»¨[regulator-3v3-vcc,regulator-fixed.vcc_3v3=Qz2Z ’2Z )d¨regulator-5v0-vcc-sys,regulator-fixed.vcc_sys=QzLK@’LK@¨$ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplydma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsgpio-line-namesbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathcolordefault-statefunctionlinux,default-trigger