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Mutmi_wide7V•]‚okayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF “ ‹ ±ýA»(Ƶusb@fd800000 ,generic-ehciý€ “‚ ½¾¼usb ‚disabledusb@fd840000 ,generic-ohciý„ “ƒ ½¾¼usb ‚disabledusb@fd880000 ,generic-ehciýˆ “… ¿À¼usb‚okayusb@fd8c0000 ,generic-ohciýŒ “† ¿À¼usb‚okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýµaio-domains&,rockchip,rk3568-pmu-io-voltage-domain‚okayÕãñÿ )7syscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsysconµ«syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƵsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȵ¬syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɵ­syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€µ®syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€µ¯clock-controller@fdd00000,rockchip,rk3568-pmucruýÐ+Eµclock-controller@fdd20000,rockchip,rk3568-cruýÒ  xin24m+E Rb€G†Œ ëÂÝÐw޵i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ “. -  i2cpclkë õdefault ‚okaypmic@20,rockchip,rk817 !“Ørk808-clkout1rk808-clkout2 mclk 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‚disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkë)õdefaultÊ ‚disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkë*õdefaultÊ ‚disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0  pwmpclkë+õdefaultÊ ‚disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0  pwmpclkë,õdefaultÊ ‚disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerÕ µpower-domain@7 é-Õpower-domain@8 ÌÍ é./0Õpower-domain@9  ÚÛÜ é123Õpower-domain@10  ñòé456789Õpower-domain@11  íé:Õpower-domain@13  é;Õpower-domain@14  é<=>Õpower-domain@15 é?@ABCÕgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$“()' ðjobmmugpu  gpubus-D7‚okayEµœvideo-codec@fdea0400,rockchip,rk3568-vpuýê “‹ðvdpu îï  aclkhclk F7 iommu@fdea0800,rockchip,rk3568-iommuýê@ “Š  aclkiface îï7 µFrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ “Z óôõ aclkhclksclkV&$%  coreaxiahb7 video-codec@fdee0000,rockchip,rk3568-vepuýî “@ ýþ  aclkhclk G7 iommu@fdee0800,rockchip,rk3568-iommuýî@ “? ýþ  aclkiface7 µGmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ “d  ÁÂŽ� biuciuciu-driveciu-sample,7ðÑ€Vë reset‚okayEO`mƒHŽ ëIJKõdefaultœL¨Methernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ“ ðmacirqeth_wake_irq@ †‰‰ÇÃĉÈW stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refVì  stmmaceth޵NÅÖOéPü ‚disabledmdio,snps,dwmac-mdio stmmac-axi-configµNrx-queues-config/µOqueue0tx-queues-configEµPqueue0vop@fe040000 þ0þ@[vopgamma-lut “”( ÝÞßàá% aclkhclkdclk_vp0dclk_vp1dclk_vp2 Q7 Ž‚okay,rockchip,rk3566-vopRßàwports µport@0 endpoint@2eRµ_port@1 endpoint@4eSµUport@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? “” ÝÞ  aclkiface7 ‚okayµQdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ “D pclk èdphyT7  apbVŽ‚okay ports port@0endpointeUµSport@1endpointeVµ[panel@0(,powkiddy,rk2023-panelnewvision,nv3051duWõdefaultëX Y‹Zportendpointe[µVdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ “E pclk édphy\7  apbVŽ ‚disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  “-( æç“(Ú iahbisfrcecrefõdefaultë]7 ³Ž›‚okay–^µports port@0endpointe_µRport@1endpointe`µÂqos@fe128000,rockchip,rk3568-qossysconþ€ µ-qos@fe138080,rockchip,rk3568-qossysconþ€€ µ<qos@fe138100,rockchip,rk3568-qossysconþ� µ=qos@fe138180,rockchip,rk3568-qossysconþ�€ µ>qos@fe148000,rockchip,rk3568-qossysconþ€ µ.qos@fe148080,rockchip,rk3568-qossysconþ€€ µ/qos@fe148100,rockchip,rk3568-qossysconþ� µ0qos@fe150000,rockchip,rk3568-qossysconþ µ:qos@fe158000,rockchip,rk3568-qossysconþ€ µ4qos@fe158100,rockchip,rk3568-qossysconþ� µ5qos@fe158180,rockchip,rk3568-qossysconþ�€ µ6qos@fe158200,rockchip,rk3568-qossysconþ‚ µ7qos@fe158280,rockchip,rk3568-qossysconþ‚€ µ8qos@fe158300,rockchip,rk3568-qossysconþƒ µ9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ µ?qos@fe190280,rockchip,rk3568-qossysconþ€ µ@qos@fe190300,rockchip,rk3568-qossysconþ µAqos@fe190380,rockchip,rk3568-qossysconþ€ µBqos@fe190400,rockchip,rk3568-qossysconþ µCqos@fe198000,rockchip,rk3568-qossysconþ€ µ;qos@fe1a8000,rockchip,rk3568-qossysconþ€ µ1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ µ2qos@fe1a8100,rockchip,rk3568-qossysconþ� µ3dfi@fe230000,rockchip,rk3568-dfiþ# “ ¢apcie@fe260000,rockchip,rk3568-pcie0À@þ&ô[dbiapbconfig<“KJIHGðsyspmcmsglegacyerr¯( �‚ƒ„…$ aclk_mstaclk_slvaclk_dbipclkauxùpci ¹`ÌbbbbÚëú    pcie-phy7Tôôô ô à@@V¡ pipe  ‚disabledlegacy-interrupt-controller ‹ “Hµbmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ “b  °±Š‹ biuciuciu-driveciu-sample,7ðÑ€VÔ reset‚okayEO *! 3ëcdefõdefault >œ¨mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ “c  ²³Œ� biuciuciu-driveciu-sample,7ðÑ€VÖ reset‚okayEO *g  3ëhijkõdefault >œ¨spi@fe300000 ,rockchip,sfcþ0@ “e xv clk_sfchclk_sfcëlõdefault ‚disabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 “R{}b ëÂn6( |zy{} corebusaxiblocktimer ‚disabledrng@fe388000,rockchip,rk3568-rngþ8€@ po  coreahbVm ‚disabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ “4R=AbFÏqFÏq ?C9 mclk_txmclk_rxhclk®m LtxVPQ  tx-mrx-mŽ›‚okayµ i2s@fe410000,rockchip,rk3568-i2s-tdmþA “5REIbFÏqFÏq GK: mclk_txmclk_rxhclk®mm LrxtxVRS  tx-mrx-mŽõdefaultënopq›‚okay VµÇi2s@fe420000,rockchip,rk3568-i2s-tdmþB “6RMbFÏq OO; mclk_txmclk_rxhclk®mm LtxrxVT tx-mŽõdefaultërstu› ‚disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC “7 SW< mclk_txmclk_rxhclk®mm LtxrxVUV  tx-mrx-mŽ› ‚disabledpdm@fe440000,rockchip,rk3568-pdmþD “L ZY pdm_clkpdm_hclk®m  Lrxëvwxyz{õdefaultVX pdm-m› ‚disabledspdif@fe460000,rockchip,rk3568-spdifþF “f  mclkhclk _\®m Ltxõdefaultë|› ‚disableddma-controller@fe530000,arm,pl330arm,primecellþS@“  q    apb_pclk ˆµ'dma-controller@fe550000,arm,pl330arm,primecellþU@“ q    apb_pclk ˆµmi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ “/ HG  i2cpclkë}õdefault  ‚disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ “0 JI  i2cpclkë~õdefault  ‚disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ “1 LK  i2cpclkëõdefault  ‚disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] “2 NM  i2cpclkë€õdefault  ‚disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ “3 PO  i2cpclkë�õdefault ‚okayµ^watchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` “•   tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa “g RQ spiclkapb_pclk®'' Ltxrxõdefault 낃„  ‚disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb “h TS spiclkapb_pclk®'' Ltxrxõdefault ë…†‡  ‚disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc “i VU spiclkapb_pclk®'' Ltxrxõdefault 눉Š  ‚disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd “j XW spiclkapb_pclk®'' Ltxrxõdefault 닌�  ‚disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe “u  baudclkapb_pclk®'' ëŽ��õdefault³À‚okay “bluetooth*,realtek,rtl8821cs-btrealtek,rtl8723bs-bt £Y µY ÂYserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf “v #  baudclkapb_pclk®''ë‘õdefault³À ‚disabledserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg “w '$ baudclkapb_pclk®''ë’õdefault³À ‚disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh “x +( baudclkapb_pclk®'' ë“õdefault³À ‚disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi “y /, baudclkapb_pclk®' ' ë”õdefault³À ‚disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj “z 30 baudclkapb_pclk®' ' ë•õdefault³À ‚disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk “{ 74 baudclkapb_pclk®''ë–õdefault³À ‚disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl “| ;8 baudclkapb_pclk®''ë—õdefault³À ‚disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm “} ?< baudclkapb_pclk®''ë˜õdefault³À ‚disabledthermal-zonescpu-thermal Òd èè ö™tripscpu_alert0 p Ð?passiveµšcpu_alert1 $ø Ð?passivecpu_crit s Ð ?criticalcooling-mapsmap0 š0 " ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal Ò èè ö™tripsgpu-threshold p Ð?passivegpu-target $ø Ð?passiveµ›gpu-crit s Ð ?criticalcooling-mapsmap0 › "œÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq “sRbf@ ®`  tsadcapb_pclkV�‚׎ 1sõdefaultsleepë� Hž R‚okay h µ™saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr “]  saradcapb_pclkV€  saradc-apb š‚okay ¬µ¼pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkëŸõdefaultÊ‚okayµ¾pwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkë õdefaultÊ ‚disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  ZY  pwmpclkë¡õdefaultÊ‚okayµÃpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY  pwmpclkë¢õdefaultÊ‚okayµÄpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkë£õdefaultÊ ‚disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkë¤õdefaultÊ ‚disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ]\  pwmpclkë¥õdefaultÊ ‚disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\  pwmpclkë¦õdefaultÊ ‚disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkë§õdefaultÊ ‚disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkë¨õdefaultÊ ‚disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  `_  pwmpclkë©õdefaultÊ ‚disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_  pwmpclkëªõdefaultÊ ‚disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "}  refapbpipeR"bõáVÇ phy ¸« ʬ à‚okayµphy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~  refapbpipeR%bõáVÉ phy ¸« Ê­ à ‚disabledµphy@fe870000,rockchip,rk3568-csi-dphyþ‡ y pclk àVº apbŽ ‚disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ…  refpclk z à7  apbV»‚okayµTmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ†  refpclk { à7  apbV¼ ‚disabledµ\usb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ  phyclkØclk_usbphy0_480m “‡ ë®+‚okayµhost-port à ‚disabledotg-port à‚okayµusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹  phyclkØclk_usbphy1_480m “ˆ ë¯+‚okayhost-port à‚okayµotg-port à ‚disabledµpinctrl,rockchip,rk3568-pinctrlŽ¢a µ°gpio@fdd60000,rockchip,gpio-bankýÖ “! .  û °  ‹ µ!gpio@fe740000,rockchip,gpio-bankþt “" cd û °  ‹ gpio@fe750000,rockchip,gpio-bankþu “# ef û °@  ‹ µggpio@fe760000,rockchip,gpio-bankþv “$ gh û °`  ‹ µÀgpio@fe770000,rockchip,gpio-bankþw “% ij û °€  ‹ µYpcfg-pull-up #µ³pcfg-pull-none 0µ±pcfg-pull-none-drv-level-1 0 =µµpcfg-pull-none-drv-level-2 0 =µ´pcfg-pull-none-drv-level-3 0 =µ¸pcfg-pull-up-drv-level-1 # =µ·pcfg-pull-up-drv-level-2 # =µ²pcfg-pull-none-smt 0 Lµ¶pcfg-output-low aµ¹acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 l±µcpuebcedpdpemmceth0eth1flashfspifspi-pins` l±±±±±±µlgmac0gmac1gpuhdmitxhdmitxm0-cec l±µ]i2c0i2c0-xfer l ¶ ¶µ i2c1i2c1-xfer l ¶ ¶µ}i2c2i2c2m0-xfer l ¶¶µ~i2c3i2c3m0-xfer l¶¶µi2c4i2c4m0-xfer l ¶ ¶µ€i2c5i2c5m1-xfer l¶¶µ�i2s1i2s1m0-lrcktx l±µoi2s1m0-mclk l±µ"i2s1m0-sclktx l±µni2s1m0-sdi0 l ±µpi2s1m0-sdo0 l±µqi2s2i2s2m0-lrcktx l±µsi2s2m0-sclktx l±µri2s2m0-sdi l±µti2s2m0-sdo l±µui2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk l±µvpdmm0-clk1 l±µwpdmm0-sdi0 l ±µxpdmm0-sdi1 l ±µypdmm0-sdi2 l ±µzpdmm0-sdi3 l±µ{pmicpmic-int-l l³µ#pmupwm0pwm0m0-pins l±µ)pwm1pwm1m0-pins l±µ*pwm2pwm2m0-pins l±µ+pwm3pwm3-pins l±µ,pwm4pwm4-pins l±µŸpwm5pwm5-pins l±µ pwm6pwm6-pins l±µ¡pwm7pwm7-pins l±µ¢pwm8pwm8m0-pins l ±µ£pwm9pwm9m0-pins l ±µ¤pwm10pwm10m0-pins l ±µ¥pwm11pwm11m0-pins l±µ¦pwm12pwm12m0-pins l±µ§pwm13pwm13m0-pins l±µ¨pwm14pwm14m0-pins l±µ©pwm15pwm15m0-pins l±µªrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ l²²²²µcsdmmc0-clk l²µdsdmmc0-cmd l²µesdmmc0-det l³µfsdmmc1sdmmc1-bus4@ l²²²²µhsdmmc1-clk l²µjsdmmc1-cmd l²µisdmmc1-det l ³µksdmmc2sdmmc2m0-bus4@ l²²²²µIsdmmc2m0-clk l²µKsdmmc2m0-cmd l²µJspdifspdifm0-tx l±µ|spi0spi0m0-pins0 l ±±±µ„spi0m0-cs0 l±µ‚spi0m0-cs1 l±µƒspi1spi1m0-pins0 l ±±±µ‡spi1m0-cs0 l±µ…spi1m0-cs1 l±µ†spi2spi2m0-pins0 l±±±µŠspi2m0-cs0 l±µˆspi2m0-cs1 l±µ‰spi3spi3m0-pins0 l ±± ±µ�spi3m0-cs0 l±µ‹spi3m0-cs1 l±µŒtsadctsadc-shutorg l±µ�tsadc-pin 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interrupt-parent#address-cells#size-cellscompatiblechassis-typemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc1mmc2mmc3device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendmonitored-batteryrockchip,resistor-sense-micro-ohmsrockchip,sleep-enter-current-microamprockchip,sleep-filter-current-microampfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablevmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointbacklightreset-gpiosvdd-supplyddc-i2c-busrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpsd-uhs-sdr104dma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsio-channelspoll-intervalabs-flatabs-fuzzabs-rangelinux,codeio-channel-namesmux-controlssettle-time-uspower-supplypwmscharge-full-design-microamp-hourscharge-term-current-microampconstant-charge-current-max-microampconstant-charge-voltage-max-microvoltfactory-internal-resistance-micro-ohmsvoltage-max-design-microvoltvoltage-min-design-microvoltocv-capacity-celsiusocv-capacity-table-0labelautorepeatmux-gpios#mux-control-cellscolorfunctionmax-brightnesspost-power-on-delay-mssimple-audio-card,widgetssimple-audio-card,routinggpioenable-active-high