Ð þíÙÖ8Í´( "Í| =,xunlong,orangepi-3b-v1.1xunlong,orangepi-3brockchip,rk35667Xunlong Orange Pi 3B v1.1aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe310000ì/mmc@fe2b0000ñ/mmc@fe2c0000cpus cpu@0öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@100öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@200öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@300öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² l3-cache,cacheºÆ@M@_²opp-table-0,operating-points-v2Ô²opp-408000000ßQ– æ »  » Œ0ôœ@opp-600000000ß#ÃF æ »  » Œ0opp-816000000ß0£, æ »  » Œ0opp-1104000000ßAÍ´ æ »  » Œ0opp-1416000000ßTfr æ »  » Œ0opp-1608000000ß_Ø" æà˜à˜Œ0opp-1800000000ßkIÒ æ��Œ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc‚" protocol@14(²opp-table-1,operating-points-v2²Bopp-200000000ß ëÂ æ øP øPB@opp-300000000ßá£ æ øP øPB@opp-400000000ßׄ æ øP øPB@opp-600000000ß#ÃF æ »  » B@opp-700000000ß)¹' æ~ð~ðB@opp-800000000ß/¯ æB@B@B@hdmi-sound,simple-audio-card5HDMILi2seokaysimple-audio-card,codec†simple-audio-card,cpu† pmu,arm,cortex-a55-pmu0�äåæç› psci ,arm,psci-1.0#smctimer,arm,armv8-timer0�   ®xin24m ,fixed-clockÅn6Õxin24m(²xin32k ,fixed-clockÅ€Õxin32kèòdefault(sram@10f000 ,mmio-sramð ðsram@0,arm,scmi-shmem²sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@›œ�satapmaliverxoob �_ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€ ¡¢satapmaliverxoob �` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ �©¦§¥ref_clksuspend_clkbus_clkBhost Jutmi_wide4S”Zokay usb2-phys zhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ �ª©ª¨ref_clksuspend_clkbus_clkBhost usb2-phyusb3-phy Jutmi_wide4S•Zokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF � ˆ�®ýA¸(òusb@fd800000 ,generic-ehciý€ �‚½¾¼usbokayusb@fd840000 ,generic-ohciý„ �ƒ½¾¼usbokayusb@fd880000 ,generic-ehciýˆ �…¿À¼usbokayusb@fd8c0000 ,generic-ohciýŒ �†¿À¼usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý²\io-domains&,rockchip,rk3568-pmu-io-voltage-domainokayÒàîü &4Bsyscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsyscon²­syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƲsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȲ®syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɲ¯syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€²°syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€²³clock-controller@fdd00000,rockchip,rk3568-pmucruýÐ(P²clock-controller@fdd20000,rockchip,rk3568-cruýÒxin24m(P] m€G†Œ ë‚™²i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ �.- i2cpclkè òdefault okaypmic@20,rockchip,rk809 ]H‚–(HmclkÕrk809-clkout1rk809-clkout2!�òdefaultè"#¦·ÏÝ$é$õ$$ $$%$1$=$²ÄregulatorsDCDC_REG1 Ivdd_logicXl~•¡ ­™pÅqregulator-state-memÚDCDC_REG2Ivdd_gpuXl~•¡ ­™pÅq²Cregulator-state-memÚDCDC_REG3Ivcc_ddrXl~regulator-state-memóDCDC_REG4Ivdd_npu~•¡ ­™pÅqregulator-state-memÚDCDC_REG5Ivcc_1v8Xl•w@­w@²regulator-state-memÚLDO_REG1Ivdda0v9_image• » ­ » ²Xregulator-state-memÚLDO_REG2 Ivdda_0v9Xl• » ­ » regulator-state-memÚLDO_REG3 Ivdda0v9_pmuXl• » ­ » regulator-state-memó » LDO_REG4 Ivccio_acodecXl•2Z ­2Z ²regulator-state-memÚLDO_REG5 Ivccio_sdXl•w@­2Z ²regulator-state-memÚLDO_REG6 Ivcc3v3_pmuXl•2Z ­2Z ²regulator-state-memó 2Z LDO_REG7 Ivcca_1v8Xl•w@­w@² regulator-state-memÚLDO_REG8 Ivcca1v8_pmuXl•w@­w@regulator-state-memó w@LDO_REG9Ivcca1v8_image•w@­w@²Yregulator-state-memÚSWITCH_REG1Ivcc_3v3Xl²regulator-state-memÚSWITCH_REG2 Ivcc3v3_sdXl²dregulator-state-memÚregulator@40,silergy,syr827@'Ivdd_cpuXl• ª0­O€ÅüD$²regulator-state-memÚserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ �t ,baudclkapb_pclkO%%è&òdefaultTa disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè'òdefaultk disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè(òdefaultk disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 pwmpclkè)òdefaultk disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0 0 pwmpclkè*òdefaultk disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerv ²power-domain@7Š+vpower-domain@8ÌÍ Š,-.vpower-domain@9 ÚÛÜ Š/01vpower-domain@10 ñòŠ234567vpower-domain@11 íŠ8vpower-domain@13 Š9vpower-domain@14 Š:;<vpower-domain@15Š=>?@Avgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$�()' ‘jobmmugpugpubus *B4okay¡C²�video-codec@fdea0400,rockchip,rk3568-vpuýê �‹‘vdpuîï aclkhclk­D4 iommu@fdea0800,rockchip,rk3568-iommuýê@ �Š aclkifaceîï4 ´²Drga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ �ZóôõaclkhclksclkS&$% Ácoreaxiahb4 video-codec@fdee0000,rockchip,rk3568-vepuýî �@ýþ aclkhclk­E4 iommu@fdee0800,rockchip,rk3568-iommuýî@ �?ýþ aclkiface4 ´²Emmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ �d ÁÂŽ�biuciuciu-driveciu-sampleÍØðÑ€SëÁreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ� ‘macirqeth_wake_irq@†‰‰ÇÃĉÈWstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refSì Ástmmaceth™æFöGH-okay]‰†‚‡Å6input Crgmii-idLòdefaultèIJKLMNWOmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22bN rÃP „P²Ostmmac-axi-config�šª²Frx-queues-configº²Gqueue0tx-queues-configвHqueue0vop@fe040000 þ0þ@ævopgamma-lut �”(ÝÞßàá%aclkhclkdclk_vp0dclk_vp1dclk_vp2­Q4 ™okay,rockchip,rk3566-vop]ßà‚ports ²port@0 endpoint@2ðR²Zport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? �”ÝÞ aclkiface´4 okay²Qdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �DpclkèdphyS4 ÁapbS™ disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �EpclkédphyT4 ÁapbS™ disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  �-(æç“(Úiahbisfrcecrefòdefault èUVW4 T™¦okayXY²ports port@0endpointðZ²Rport@1endpointð[²¾qos@fe128000,rockchip,rk3568-qossysconþ€ ²+qos@fe138080,rockchip,rk3568-qossysconþ€€ ²:qos@fe138100,rockchip,rk3568-qossysconþ� ²;qos@fe138180,rockchip,rk3568-qossysconþ�€ ²<qos@fe148000,rockchip,rk3568-qossysconþ€ ²,qos@fe148080,rockchip,rk3568-qossysconþ€€ ²-qos@fe148100,rockchip,rk3568-qossysconþ� ².qos@fe150000,rockchip,rk3568-qossysconþ ²8qos@fe158000,rockchip,rk3568-qossysconþ€ ²2qos@fe158100,rockchip,rk3568-qossysconþ� ²3qos@fe158180,rockchip,rk3568-qossysconþ�€ ²4qos@fe158200,rockchip,rk3568-qossysconþ‚ ²5qos@fe158280,rockchip,rk3568-qossysconþ‚€ ²6qos@fe158300,rockchip,rk3568-qossysconþƒ ²7qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ²=qos@fe190280,rockchip,rk3568-qossysconþ€ ²>qos@fe190300,rockchip,rk3568-qossysconþ ²?qos@fe190380,rockchip,rk3568-qossysconþ€ ²@qos@fe190400,rockchip,rk3568-qossysconþ ²Aqos@fe198000,rockchip,rk3568-qossysconþ€ ²9qos@fe1a8000,rockchip,rk3568-qossysconþ€ ²/qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ²0qos@fe1a8100,rockchip,rk3568-qossysconþ� ²1dfi@fe230000,rockchip,rk3568-dfiþ# �  \pcie@fe260000,rockchip,rk3568-pcie0À@þ&ôædbiapbconfig<�KJIHG‘syspmcmsglegacyerr-(�‚ƒ„…$aclk_mstaclk_slvaclk_dbipclkauxöpci�7`J]]]]Xix‡–ž pcie-phy4Tôôô ô à@@S¡Ápipe okayòdefaultè^ „!¨_legacy-interrupt-controller�ˆ �H²]mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ �b °±Š‹biuciuciu-driveciu-sampleÍØðÑ€SÔÁresetokay¸ÂÓòdefaultè`abcÞdêmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ �c ²³Œ�biuciuciu-driveciu-sampleÍØðÑ€SÖÁresetokay¸Â÷  e % , 2òdefault èfgh @Þêspi@fe300000 ,rockchip,sfcþ0@ �exvclk_sfchclk_sfcèiòdefaultokay flash@0,jedec,spi-nor N2ê ` qmmc@fe310000,rockchip,rk3568-dwcmshcþ1 �]{}m ëÂn6(|zy{}corebusaxiblocktimerokay¸ ‚Ø ë ” 2òdefaultèjklmÞêrng@fe388000,rockchip,rk3568-rngþ8€@po coreahbSm disabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ �4]=AmFÏqFÏq?C9mclk_txmclk_rxhclkOn £txSPQ Átx-mrx-m™¦okay² i2s@fe410000,rockchip,rk3568-i2s-tdmþA �5]EImFÏqFÏqGK:mclk_txmclk_rxhclkOnn £rxtxSRS Átx-mrx-m™òdefaultèopqr¦okay ­²Æi2s@fe420000,rockchip,rk3568-i2s-tdmþB �6]MmFÏqOO;mclk_txmclk_rxhclkOnn £txrxSTÁtx-m™òdefaultèstuv¦ disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC �7SW<mclk_txmclk_rxhclkOnn £txrxSUV Átx-mrx-m™¦ disabledpdm@fe440000,rockchip,rk3568-pdmþD �LZYpdm_clkpdm_hclkOn  £rxèwxyz{|òdefaultSXÁpdm-m¦ disabledspdif@fe460000,rockchip,rk3568-spdifþF �f mclkhclk_\On £txòdefaultè}¦ disableddma-controller@fe530000,arm,pl330arm,primecellþS@�  È  apb_pclk ß²%dma-controller@fe550000,arm,pl330arm,primecellþU@� È  apb_pclk ß²ni2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ �/HG i2cpclkè~òdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ �0JI i2cpclkèòdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ �1LK i2cpclkè€òdefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] �2NM i2cpclkè�òdefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ �3PO i2cpclkè‚òdefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` �• tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa �gRQspiclkapb_pclkO%% £txrxòdefault 胄…  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb �hTSspiclkapb_pclkO%% £txrxòdefault 膇ˆ  disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc �iVUspiclkapb_pclkO%% £txrxòdefault 艊‹  disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd �jXWspiclkapb_pclkO%% £txrxòdefault èŒ�Ž  disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe �ubaudclkapb_pclkO%% è��‘òdefaultTaokay êserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf �v# baudclkapb_pclkO%%è’òdefaultTaokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg �w'$baudclkapb_pclkO%%è“òdefaultTa disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh �x+(baudclkapb_pclkO%% è”òdefaultTa disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi �y/,baudclkapb_pclkO% % è•òdefaultTa disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj �z30baudclkapb_pclkO% % è–òdefaultTa disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk �{74baudclkapb_pclkO%%è—òdefaultTa disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl �|;8baudclkapb_pclkO%%è˜òdefaultTa disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm �}?<baudclkapb_pclkO%%è™òdefaultTa disabledthermal-zonescpu-thermal úd è štripscpu_alert0 .p :Ðýpassive²›cpu_alert1 .$ø :Ðýpassivecpu_crit .s :Ð ýcriticalcooling-mapsmap0 E›0 J ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal ú è štripsgpu-threshold .p :Ðýpassivegpu-target .$ø :Ðýpassive²œgpu-crit .s :Ð ýcriticalcooling-mapsmap0 Eœ J�ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq �s]mf@ ®`tsadcapb_pclkS�‚×™ Ysòdefaultsleepèž pŸ zokay � §²šsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr �]saradcapb_pclkS€ Ásaradc-apb Âokay Ô pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¡òdefaultk disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¢òdefaultk disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY pwmpclkè£òdefaultk disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0ZY pwmpclkè¤òdefaultk disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè¥òdefaultk disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè¦òdefaultk disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ pwmpclkè§òdefaultk disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0]\ pwmpclkè¨òdefaultk disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè©òdefaultk disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkèªòdefaultk disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ pwmpclkè«òdefaultk disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0`_ pwmpclkè¬òdefaultk disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ"} refapbpipe]"mõáSÇÁphy à­ ò® okay²phy@fe840000,rockchip,rk3568-naneng-combphyþ„%~ refapbpipe]%mõáSÉÁphy à­ ò¯ okay²phy@fe870000,rockchip,rk3568-csi-dphyþ‡ypclk SºÁapb™ disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… refpclkz 4 ÁapbS» disabled²Smipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† refpclk{ 4 ÁapbS¼ disabled²Tusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠphyclkÕclk_usbphy0_480m �‡ °(okay²host-port okayL±²otg-port okayL²²usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹phyclkÕclk_usbphy1_480m �ˆ ³(okayhost-port okayL±²otg-port okayL±²pinctrl,rockchip,rk3568-pinctrl™ \ ²´gpio@fdd60000,rockchip,gpio-bankýÖ �!.  # 3´  ?ˆ�²!gpio@fe740000,rockchip,gpio-bankþt �"cd # 3´  ?ˆ�gpio@fe750000,rockchip,gpio-bankþu �#ef # 3´@  ?ˆ�gpio@fe760000,rockchip,gpio-bankþv �$gh # 3´`  ?ˆ�²Pgpio@fe770000,rockchip,gpio-bankþw �%ij # 3´€  ?ˆ�pcfg-pull-up K²·pcfg-pull-down X²½pcfg-pull-none g²µpcfg-pull-none-drv-level-1 g t²¹pcfg-pull-none-drv-level-2 g t²¸pcfg-pull-none-drv-level-3 g t²¼pcfg-pull-up-drv-level-1 K t²»pcfg-pull-up-drv-level-2 K t²¶pcfg-pull-none-smt g ƒ²ºacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ˜µ²cpuebcedpdpemmcemmc-bus8€ ˜ ¶ ¶¶¶¶¶¶¶²jemmc-clk ˜¶²kemmc-cmd ˜¶²lemmc-datastrobe ˜µ²meth0eth1flashfspifspi-pins` ˜µµµµµµ²igmac0gmac1gmac1m0-miim ˜µµ²Igmac1m0-clkinout ˜µ²Ngmac1m0-rx-bus20 ˜ µ µ µ²Kgmac1m0-tx-bus20 ˜ ¸¸µ²Jgmac1m0-rgmii-clk ˜µ¹²Lgmac1m0-rgmii-bus@ ˜µµ¸¸²Mgpuhdmitxhdmitxm0-cec ˜µ²Whdmitx-scl ˜µ²Uhdmitx-sda ˜µ²Vi2c0i2c0-xfer ˜ º º² i2c1i2c1-xfer ˜ º º²~i2c2i2c2m0-xfer ˜ ºº²i2c3i2c3m0-xfer ˜ºº²€i2c4i2c4m0-xfer ˜ º º²�i2c5i2c5m0-xfer ˜ º º²‚i2s1i2s1m0-lrcktx ˜µ²pi2s1m0-mclk ˜µ²#i2s1m0-sclktx ˜µ²oi2s1m0-sdi0 ˜ µ²qi2s1m0-sdo0 ˜µ²ri2s2i2s2m0-lrcktx ˜µ²ti2s2m0-sclktx ˜µ²si2s2m0-sdi ˜µ²ui2s2m0-sdo ˜µ²vi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ˜µ²wpdmm0-clk1 ˜µ²xpdmm0-sdi0 ˜ µ²ypdmm0-sdi1 ˜ µ²zpdmm0-sdi2 ˜ µ²{pdmm0-sdi3 ˜µ²|pmicpmic-int-l ˜·²"pmupwm0pwm0m0-pins ˜µ²'pwm1pwm1m0-pins ˜µ²(pwm2pwm2m0-pins ˜µ²)pwm3pwm3-pins ˜µ²*pwm4pwm4-pins ˜µ²¡pwm5pwm5-pins ˜µ²¢pwm6pwm6-pins ˜µ²£pwm7pwm7-pins ˜µ²¤pwm8pwm8m0-pins ˜ µ²¥pwm9pwm9m0-pins ˜ µ²¦pwm10pwm10m0-pins ˜ µ²§pwm11pwm11m0-pins ˜µ²¨pwm12pwm12m0-pins ˜µ²©pwm13pwm13m0-pins ˜µ²ªpwm14pwm14m0-pins ˜µ²«pwm15pwm15m0-pins ˜µ²¬refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ˜¶¶¶¶²`sdmmc0-clk ˜¶²asdmmc0-cmd ˜¶²bsdmmc0-det ˜·²csdmmc1sdmmc1-bus4@ ˜¶¶¶¶²fsdmmc1-clk ˜¶²gsdmmc1-cmd ˜¶²hsdmmc2spdifspdifm0-tx ˜µ²}spi0spi0m0-pins0 ˜ µµµ²…spi0m0-cs0 ˜µ²ƒspi0m0-cs1 ˜µ²„spi1spi1m0-pins0 ˜ µµµ²ˆspi1m0-cs0 ˜µ²†spi1m0-cs1 ˜µ²‡spi2spi2m0-pins0 ˜µµµ²‹spi2m0-cs0 ˜µ²‰spi2m0-cs1 ˜µ²Šspi3spi3m0-pins0 ˜ µµ µ²Žspi3m0-cs0 ˜µ²Œspi3m0-cs1 ˜µ²�tsadctsadc-shutorg ˜µ²žtsadc-pin ˜µ²Ÿuart0uart0-xfer ˜··²&uart1uart1m0-xfer ˜ · ·²�uart1m0-ctsn ˜µ²�uart1m0-rtsn ˜ µ²‘uart2uart2m0-xfer ˜··²’uart3uart3m0-xfer ˜··²“uart4uart4m0-xfer ˜··²”uart5uart5m0-xfer ˜··²•uart6uart6m0-xfer ˜··²–uart7uart7m0-xfer ˜··²—uart8uart8m0-xfer ˜··²˜uart9uart9m0-xfer ˜··²™vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2bluetoothbt-reg-on-h ˜µbt-wake-host-h ˜½host-wake-bt-h ˜µledswork-led ˜µ²¿pciepcie20-pins0 ˜µµ µ²^pcie20-pwren ˜µ²Àusbusb-host-pwren-h ˜µ²Âusb-otg-pwren-h ˜µ²Ãwifiwifi-reg-on-h ˜µ²Åwifi-wake-host-h ˜½chosen ¦serial2:1500000n8hdmi-con,hdmi-connectorýaportendpointð¾²[leds ,gpio-ledsòdefaultè¿led-0 ² ¸on Æheartbeat Š! Ïheartbeatregulator-3v3-vcc-pcie30,regulator-fixed å Š!òdefaultèÀIvcc3v3_pcie30•2Z ­2Z D$²_regulator-3v3-vcc-sys,regulator-fixed Ivcc3v3_sysXl•2Z ­2Z DÁ²$regulator-5v0-vcc-sys,regulator-fixed Ivcc5v0_sysXl•LK@­LK@²Áregulator-5v0-vcc-usb-host,regulator-fixed å Š!òdefaultèÂIvcc5v0_usb_host•LK@­LK@DÁ²±regulator-5v0-vcc-usb-otg,regulator-fixed å Š!òdefaultèÃIvcc5v0_usb_otg•LK@­LK@DÁ²²sdio-pwrseq,mmc-pwrseq-simpleÄ ext_clockòdefaultèÅ øÈ LK@ „!²esound,simple-audio-cardLi2s 5Analog RK809esimple-audio-card,cpu†Æsimple-audio-card,codec†Ä interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio6-supplyvccio7-supplyvccio5-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-supplyphy-handlereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplybus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr104spi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthcap-mmc-highspeedmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathcolordefault-statefunctionlinux,default-triggerenable-active-highpost-power-on-delay-mspower-off-delay-us