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 i2cpclkë õdefault ‚okaypmic@20,rockchip,rk817 !“Ørk808-clkout1rk808-clkout2 mclk HRHw–+›õdefaultë"#¬º$Æ$Ò$Þ$ê$ö$$$%µÂregulatorsDCDC_REG1&:L¡ d™p|q‘ ¨vdd_logicregulator-state-mem·Ð » DCDC_REG2&:L¡ d™p|q‘¨vdd_gpuµEregulator-state-mem·DCDC_REG3&:‘¨vcc_ddrregulator-state-memìDCDC_REG4&:L2Z d2Z ‘¨vcc_3v3µregulator-state-memìÐ2Z LDO_REG1&:Lw@dw@ ¨vcca1v8_pmuµMregulator-state-memìÐw@LDO_REG2&:L » d »  ¨vdda_0v9regulator-state-mem·LDO_REG3&:L » d »  ¨vdda0v9_pmuregulator-state-memìÐ » LDO_REG4&:L2Z d2Z  ¨vccio_acodecµregulator-state-mem·LDO_REG5&:Lw@d2Z  ¨vccio_sdµregulator-state-mem·LDO_REG6&:L2Z d2Z  ¨vcc3v3_pmuµregulator-state-memìÐ2Z LDO_REG7&:Lw@dw@¨vcc_1v8µregulator-state-mem·LDO_REG8&:Lw@d2Z  ¨vcc1v8_dvpµregulator-state-mem·LDO_REG9&:L*¹€d*¹€ ¨vcc2v8_dvpregulator-state-mem·BOOST&:LG·`dReÀ¨boostµ%regulator-state-mem·OTG_SWITCH ¨otg_switchregulator-state-mem·charger&'9“à_† regulator@40 ,fcs,fan53555@†&:L ß4d5°¨vdd_cpu|ü£$µregulator-state-mem·power-monitor@62,cellwise,cw2015b ‚disabledserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ “t  , baudclkapb_pclk®''ë(õdefault³À ‚disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkë)õdefaultÊ‚okayµÁpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkë*õdefaultÊ ‚disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0  pwmpclkë+õdefaultÊ ‚disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0  pwmpclkë,õdefaultÊ ‚disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controllerÕ µpower-domain@7 é-Õpower-domain@8 ÌÍ é./0Õpower-domain@9  ÚÛÜ é123Õpower-domain@10  ñòé456789Õpower-domain@11  íé:Õpower-domain@13  é;Õpower-domain@14  é<=>Õpower-domain@15 é?@ABCÕgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$“()' ðjobmmugpu  gpubus-D7‚okayEµœvideo-codec@fdea0400,rockchip,rk3568-vpuýê “‹ðvdpu îï  aclkhclk F7 iommu@fdea0800,rockchip,rk3568-iommuýê@ “Š  aclkiface îï7 µFrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ “Z óôõ aclkhclksclkV&$%  coreaxiahb7 video-codec@fdee0000,rockchip,rk3568-vepuýî “@ ýþ  aclkhclk G7 iommu@fdee0800,rockchip,rk3568-iommuýî@ “? ýþ  aclkiface7 µGmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ “d  ÁÂŽ� biuciuciu-driveciu-sample,7ðÑ€Vë reset‚okayEO`mƒHŽ•› ëIJKõdefault©¶LÂMethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ“ ðmacirqeth_wake_irq@ †‰‰ÇÃĉÈW stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refVì  stmmacethŽÏNßðOP ‚disabledmdio,snps,dwmac-mdio stmmac-axi-config)9µNrx-queues-configIµOqueue0tx-queues-config_µPqueue0vop@fe040000 þ0þ@uvopgamma-lut “”( ÝÞßàá% aclkhclkdclk_vp0dclk_vp1dclk_vp2 Q7 Ž‚okay,rockchip,rk3566-vopRßàwports µport@0 endpoint@2Rµ_port@1 endpoint@4SµUport@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? “” ÝÞ  aclkiface7 ‚okayµQdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ “D pclk èdphyT7  apbVŽ‚okay ports port@0endpointUµSport@1endpointVµ[panel@0(,anbernic,rg353p-panelnewvision,nv3051d�WõdefaultëX ™Y¥Zportendpoint[µVdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ “E pclk édphy\7  apbVŽ ‚disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  “-( æç“(Ú iahbisfrcecrefõdefaultë]7 ³Ž›‚okay°^µports port@0endpoint_µRport@1endpoint`µ¾qos@fe128000,rockchip,rk3568-qossysconþ€ µ-qos@fe138080,rockchip,rk3568-qossysconþ€€ µ<qos@fe138100,rockchip,rk3568-qossysconþ� µ=qos@fe138180,rockchip,rk3568-qossysconþ�€ µ>qos@fe148000,rockchip,rk3568-qossysconþ€ µ.qos@fe148080,rockchip,rk3568-qossysconþ€€ µ/qos@fe148100,rockchip,rk3568-qossysconþ� µ0qos@fe150000,rockchip,rk3568-qossysconþ µ:qos@fe158000,rockchip,rk3568-qossysconþ€ µ4qos@fe158100,rockchip,rk3568-qossysconþ� µ5qos@fe158180,rockchip,rk3568-qossysconþ�€ µ6qos@fe158200,rockchip,rk3568-qossysconþ‚ µ7qos@fe158280,rockchip,rk3568-qossysconþ‚€ µ8qos@fe158300,rockchip,rk3568-qossysconþƒ µ9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ µ?qos@fe190280,rockchip,rk3568-qossysconþ€ µ@qos@fe190300,rockchip,rk3568-qossysconþ µAqos@fe190380,rockchip,rk3568-qossysconþ€ µBqos@fe190400,rockchip,rk3568-qossysconþ µCqos@fe198000,rockchip,rk3568-qossysconþ€ µ;qos@fe1a8000,rockchip,rk3568-qossysconþ€ µ1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ µ2qos@fe1a8100,rockchip,rk3568-qossysconþ� µ3dfi@fe230000,rockchip,rk3568-dfiþ# “ ¼apcie@fe260000,rockchip,rk3568-pcie0À@þ&ôudbiapbconfig<“KJIHGðsyspmcmsglegacyerrÉ( �‚ƒ„…$ aclk_mstaclk_slvaclk_dbipclkauxùpci Ó`æbbbbô   # 2 : pcie-phy7Tôôô ô à@@V¡ pipe  ‚disabledlegacy-interrupt-controller ‹ “Hµbmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ “b  °±Š‹ biuciuciu-driveciu-sample,7ðÑ€VÔ reset‚okayEO D! Mëcdefõdefault X¶Âmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ “c  ²³Œ� biuciuciu-driveciu-sample,7ðÑ€VÖ reset‚okayEO Dg  Mëhijkõdefault X¶Âspi@fe300000 ,rockchip,sfcþ0@ “e xv clk_sfchclk_sfcëlõdefault ‚disabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 “R{}b ëÂn6( |zy{} corebusaxiblocktimer ‚disabledrng@fe388000,rockchip,rk3568-rngþ8€@ po  coreahbVm ‚disabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ “4R=AbFÏqFÏq ?C9 mclk_txmclk_rxhclk®m ftxVPQ  tx-mrx-mŽ›‚okayµ i2s@fe410000,rockchip,rk3568-i2s-tdmþA “5REIbFÏqFÏq GK: mclk_txmclk_rxhclk®mm frxtxVRS  tx-mrx-mŽõdefaultënopq›‚okay pµËi2s@fe420000,rockchip,rk3568-i2s-tdmþB “6RMbFÏq OO; mclk_txmclk_rxhclk®mm ftxrxVT tx-mŽõdefaultërstu› ‚disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC “7 SW< mclk_txmclk_rxhclk®mm ftxrxVUV  tx-mrx-mŽ› ‚disabledpdm@fe440000,rockchip,rk3568-pdmþD “L ZY pdm_clkpdm_hclk®m  frxëvwxyz{õdefaultVX pdm-m› ‚disabledspdif@fe460000,rockchip,rk3568-spdifþF “f  mclkhclk _\®m ftxõdefaultë|› ‚disableddma-controller@fe530000,arm,pl330arm,primecellþS@“  ‹    apb_pclk ¢µ'dma-controller@fe550000,arm,pl330arm,primecellþU@“ ‹    apb_pclk ¢µmi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ “/ HG  i2cpclkë}õdefault  ‚disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ “0 JI  i2cpclkë~õdefault  ‚disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ “1 LK  i2cpclkëõdefault  ‚disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] “2 NM  i2cpclkë€õdefault  ‚disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ “3 PO  i2cpclkë�õdefault ‚okayµ^watchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` “•   tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa “g RQ spiclkapb_pclk®'' ftxrxõdefault 낃„  ‚disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb “h TS spiclkapb_pclk®'' ftxrxõdefault ë…†‡  ‚disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc “i VU spiclkapb_pclk®'' ftxrxõdefault 눉Š  ‚disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd “j XW spiclkapb_pclk®'' ftxrxõdefault 닌�  ‚disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe “u  baudclkapb_pclk®'' ëŽ��õdefault³À‚okay ­bluetooth*,realtek,rtl8821cs-btrealtek,rtl8723bs-bt ½Y ÏY ÜYserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf “v #  baudclkapb_pclk®''ë‘õdefault³À‚okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg “w '$ baudclkapb_pclk®''ë’õdefault³À ‚disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh “x +( baudclkapb_pclk®'' ë“õdefault³À ‚disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi “y /, baudclkapb_pclk®' ' ë”õdefault³À ‚disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj “z 30 baudclkapb_pclk®' ' ë•õdefault³À ‚disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk “{ 74 baudclkapb_pclk®''ë–õdefault³À ‚disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl “| ;8 baudclkapb_pclk®''ë—õdefault³À ‚disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm “} ?< baudclkapb_pclk®''ë˜õdefault³À ‚disabledthermal-zonescpu-thermal ìd è ™tripscpu_alert0 p ,Ð?passiveµšcpu_alert1 $ø ,Ð?passivecpu_crit s ,Ð ?criticalcooling-mapsmap0 7š0 < ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal ì è ™tripsgpu-threshold p ,Ð?passivegpu-target $ø ,Ð?passiveµ›gpu-crit s ,Ð ?criticalcooling-mapsmap0 7› <œÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq “sRbf@ ®`  tsadcapb_pclkV�‚׎ Ksõdefaultsleepë� bž l‚okay ‚ ™µ™saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr “]  saradcapb_pclkV€  saradc-apb ´‚okay Ƶºpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkëŸõdefaultÊ‚okayµÊpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkë õdefaultÊ‚okayµÆpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  ZY  pwmpclkë¡õdefaultÊ‚okayµ¿pwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY  pwmpclkë¢õdefaultÊ‚okayµÀpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkë£õdefaultÊ ‚disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkë¤õdefaultÊ ‚disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ]\  pwmpclkë¥õdefaultÊ ‚disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\  pwmpclkë¦õdefaultÊ ‚disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkë§õdefaultÊ ‚disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkë¨õdefaultÊ ‚disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  `_  pwmpclkë©õdefaultÊ ‚disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_  pwmpclkëªõdefaultÊ ‚disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "}  refapbpipeR"bõáVÇ phy Ò« ä¬ ú‚okayµphy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~  refapbpipeR%bõáVÉ phy Ò« ä­ ú ‚disabledµphy@fe870000,rockchip,rk3568-csi-dphyþ‡ y pclk úVº apbŽ ‚disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ…  refpclk z ú7  apbV»‚okayµTmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ†  refpclk { ú7  apbV¼ ‚disabledµ\usb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ  phyclkØclk_usbphy0_480m “‡ ®+‚okayµhost-port ú ‚disabledotg-port ú‚okayµusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹  phyclkØclk_usbphy1_480m “ˆ ¯+‚okayhost-port ú‚okayµotg-port ú ‚disabledµpinctrl,rockchip,rk3568-pinctrl޼a µ°gpio@fdd60000,rockchip,gpio-bankýÖ “! .   %°  1‹ µ!gpio@fe740000,rockchip,gpio-bankþt “" cd  %°  1‹ gpio@fe750000,rockchip,gpio-bankþu “# ef  %°@  1‹ µggpio@fe760000,rockchip,gpio-bankþv “$ gh  %°`  1‹ µ¼gpio@fe770000,rockchip,gpio-bankþw “% ij  %°€  1‹ µYpcfg-pull-up =µ³pcfg-pull-none Jµ±pcfg-pull-none-drv-level-1 J Wµµpcfg-pull-none-drv-level-2 J Wµ´pcfg-pull-none-drv-level-3 J Wµ¸pcfg-pull-up-drv-level-1 = Wµ·pcfg-pull-up-drv-level-2 = Wµ²pcfg-pull-none-smt J fµ¶pcfg-output-low {µ¹acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 †±µcpuebcedpdpemmceth0eth1flashfspifspi-pins` †±±±±±±µlgmac0gmac1gpuhdmitxhdmitxm0-cec †±µ]i2c0i2c0-xfer † ¶ ¶µ i2c1i2c1-xfer † ¶ ¶µ}i2c2i2c2m0-xfer † ¶¶µ~i2c3i2c3m0-xfer †¶¶µi2c4i2c4m0-xfer † ¶ ¶µ€i2c5i2c5m1-xfer †¶¶µ�i2s1i2s1m0-lrcktx †±µoi2s1m0-mclk †±µ"i2s1m0-sclktx †±µni2s1m0-sdi0 † ±µpi2s1m0-sdo0 †±µqi2s2i2s2m0-lrcktx †±µsi2s2m0-sclktx †±µri2s2m0-sdi †±µti2s2m0-sdo †±µui2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk †±µvpdmm0-clk1 †±µwpdmm0-sdi0 † ±µxpdmm0-sdi1 † ±µypdmm0-sdi2 † ±µzpdmm0-sdi3 †±µ{pmicpmic-int-l †³µ#pmupwm0pwm0m1-pins †±µ)pwm1pwm1m0-pins †±µ*pwm2pwm2m0-pins †±µ+pwm3pwm3-pins †±µ,pwm4pwm4-pins †±µŸpwm5pwm5-pins †±µ pwm6pwm6-pins †±µ¡pwm7pwm7-pins †±µ¢pwm8pwm8m0-pins † ±µ£pwm9pwm9m0-pins † ±µ¤pwm10pwm10m0-pins † ±µ¥pwm11pwm11m0-pins †±µ¦pwm12pwm12m0-pins †±µ§pwm13pwm13m0-pins †±µ¨pwm14pwm14m0-pins †±µ©pwm15pwm15m0-pins †±µªrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ †²²²²µcsdmmc0-clk †²µdsdmmc0-cmd †²µesdmmc0-det †³µfsdmmc1sdmmc1-bus4@ †²²²²µhsdmmc1-clk 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,gpio-keysë»õdefaultbutton-b Ÿ¼ åSOUTH ë0button-down Ÿ¼ åDPAD-DOWN ë!button-l1 Ÿ¼  åTL ë6button-l2 Ÿ¼  åTL2 ë8button-select Ÿ¼ åSELECT ë:button-start Ÿ¼  åSTART ë;button-up Ÿ¼ åDPAD-UP ë button-x Ÿ¼ åNORTH ë3button-a Ÿ¼ åEAST ë1button-left Ÿ¼ åDPAD-LEFT ë"button-right Ÿ¼ åDPAD-RIGHT ë#button-thumbl Ÿ¼ åTHUMBL ë=button-thumbr Ÿ¼ åTHUMBR ë>button-y Ÿ¼ åWEST ë4button-r1 Ÿ¼  åTR ë7button-r2 Ÿ¼  åTR2 ë9gpio-keys-vol ,gpio-keys ë½õdefaultbutton-vol-down Ÿ¼ åVOLUMEDOWN ërbutton-vol-up Ÿ¼ åVOLUMEUP ëshdmi-con,hdmi-connector°^?cportendpoint¾µ`pwm-leds ,pwm-ledsled-0  !on /power 8ÿ G¿a¨led-1  /charging 8ÿ GÀa¨led-2  !off /status 8ÿ GÁa¨sdio-pwrseq,mmc-pwrseq-simple   ext_clockëÃõdefault LÈ ™YµHregulator-vcc3v3-lcd0,regulator-fixed c! hëÄõdefault:L2Z d2Z ¨vcc3v3_lcd0_n£µZregulator-state-mem·regulator-vcc-sys,regulator-fixed&:L9ûÀd9ûÀ¨vcc_sysµ$regulator-vcc-wifi,regulator-fixed h c!ëÅõdefault&:L2Z d2Z  ¨vcc_wifiµLpwm-vibrator ,pwm-vibrator {enable GÆ;šÊadc-joystick ,adc-joystick  ÇÇÇÇëÈõdefault ×< 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ÔµÉbattery,simple-battery ç0˜ “à &„€ K@@ qÉ ˜?¨à µ3á@ Ò¨ ç?¨àd=Ûð_<Ê€Z;çðU;ÐP:aPK9¹XF9(ÐA8«Ð<82¸77±Ð27[à-7`(6î€#6»¸6}8635Ɉ5H  4”ð3á@µ&sound,simple-audio-card 8rk817_intOi2s üYhCMicrophoneMic JackHeadphoneHeadphonesSpeakerInternal SpeakersE4MICLMic JackHeadphonesHPOLHeadphonesHPORInternal SpeakersSPKOsimple-audio-card,codec‰Âsimple-audio-card,cpu‰Ë interrupt-parent#address-cells#size-cellscompatiblechassis-typemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grf#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendmonitored-batteryrockchip,resistor-sense-micro-ohmsrockchip,sleep-enter-current-microamprockchip,sleep-filter-current-microampfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencybus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr50vmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointbacklightreset-gpiosvdd-supplyddc-i2c-busrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpsd-uhs-sdr104dma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltautorepeatcolordefault-statefunctionmax-brightnesspwmspost-power-on-delay-msgpioenable-active-highpwm-namesabs-flatabs-fuzzabs-rangemux-controlssettle-time-uspower-supplymux-gpios#mux-control-cellscharge-full-design-microamp-hourscharge-term-current-microampconstant-charge-current-max-microampconstant-charge-voltage-max-microvoltfactory-internal-resistance-micro-ohmsvoltage-max-design-microvoltvoltage-min-design-microvoltocv-capacity-celsiusocv-capacity-table-0simple-audio-card,hp-det-gpiosimple-audio-card,widgetssimple-audio-card,routing