Ð þíóì8ç8( ´ç'friendlyarm,nanopi-r4srockchip,rk3399 +7FriendlyElec NanoPi R4Saliases=/pinctrl/gpio@ff720000C/pinctrl/gpio@ff730000I/pinctrl/gpio@ff780000O/pinctrl/gpio@ff788000U/pinctrl/gpio@ff790000[/i2c@ff3c0000`/i2c@ff110000e/i2c@ff120000j/i2c@ff130000o/i2c@ff3d0000t/i2c@ff140000y/i2c@ff150000~/i2c@ff160000ƒ/i2c@ff3e0000ˆ/serial@ff180000�/serial@ff190000˜/serial@ff1a0000 /serial@ff1b0000¨/serial@ff370000°/spi@ff1c0000µ/spi@ff1d0000º/spi@ff1e0000¿/spi@ff350000Ä/spi@ff1f0000É/spi@ff200000Î/ethernet@fe300000Ø/mmc@fe310000Ý/mmc@fe320000â/mmc@fe330000cpus+cpu-mapcluster0core0çcore1çcore2çcore3çcluster1core0çcore1çcpu@0ëcpuarm,cortex-a53÷ûpsci å#2dL \€i@{ˆ€•@§€´ Å Ù äcpu@1ëcpuarm,cortex-a53÷ûpsci å#2dL \€i@{ˆ€•@§€´ Å Ù äcpu@2ëcpuarm,cortex-a53÷ûpsci å#2dL \€i@{ˆ€•@§€´ Å Ù äcpu@3ëcpuarm,cortex-a53÷ûpsci å#2dL \€i@{ˆ€•@§€´ Å Ù äcpu@100ëcpuarm,cortex-a72÷ûpsci  #2´L \Ài@{ˆ€•@§´ÅÙäthermal-idle#ì'øôcpu@101ëcpuarm,cortex-a72÷ûpsci  #2´L \Ài@{ˆ€•@§´ÅÙäthermal-idle#ì'øôl2-cache-cluster0cache^k@}ä l2-cache-cluster1cache^k@}äidle-states"pscicpu-sleeparm,idle-state/@Wxøúh„ä cluster-sleeparm,idle-state/@W�øôhÐä memory-controllerrockchip,rk3399-dmcy†¨•dmc_clk ¡disabledpmu_a53arm,cortex-a53-pmu¨pmu_a72arm,cortex-a72-pmu¨psci arm,psci-1.0smctimerarm,armv8-timer@¨   ³xin24m fixed-clockÊn6Úxin24míä™pcie@f8000000rockchip,rk3399-pcie ÷øýúaxi-baseapb-baseëpci+! ÅÄG •aclkaclk-perfhclkpm0¨123+syslegacyclient;`N\k s,xpcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38‚‚úúà�ûàûà8‰‚ƒ„…†�€(�coremgmtmgmt-stickypipepmpclkaclk¡okayœ¦¶Æinterrupt-controllerÖäpcie-ep@f8000000rockchip,rk3399-pcie-ep ÷ýúúapb-basemem-base ÅÄG •aclkaclk-perfhclkpmëœ8‰‚ƒ„…†�€(�coremgmtmgmt-stickypipepmpclkaclk s,xpcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-3ù default% ¡disabledethernet@fe300000rockchip,rk3399-gmac÷þ0¨ +macirq8ighfjÕfM•stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac/‰‰ �stmmaceth=J¡okayUl¦|inputdefault % !‰"”rgmii�#¨(±mdiosnps,dwmac-mdio+ethernet-phy@1÷ $¨ º'Êu0 Ü$ä"mmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc÷þ1@¨@èðÑ€ îMœ�•biuciuciu-driveciu-sampleö/‰y�reset ¡disabled )?%Jdefault %&'(Xmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc÷þ2@¨AèðÑ€lÍf ë ÎLš›•biuciuciu-driveciu-sampleö/‰z�reset¡okay { �)–default%*+,-X¡.­/mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.1÷þ3¨ ºlNf ëÂNð•clk_xinclk_ahbÚemmc_cardclockís0 xphy_arasan/Ð ¡disabledáJäœusb@fe380000 generic-ehci÷þ8¨ÈÉ1s2xusb¡okayusb@fe3a0000 generic-ohci÷þ:¨ÈÉ1s2xusb¡okayusb@fe3c0000 generic-ehci÷þ<¨ÊË3s4xusb¡okayusb@fe3e0000 generic-ohci÷þ>¨ ÊË3s4xusb¡okaydebug@fe430000&arm,coresight-cpu-debugarm,primecell÷þCM •apb_pclkçdebug@fe432000&arm,coresight-cpu-debugarm,primecell÷þC M •apb_pclkçdebug@fe434000&arm,coresight-cpu-debugarm,primecell÷þC@M •apb_pclkçdebug@fe436000&arm,coresight-cpu-debugarm,primecell÷þC`M •apb_pclkçdebug@fe610000&arm,coresight-cpu-debugarm,primecell÷þaL •apb_pclkçdebug@fe710000&arm,coresight-cpu-debugarm,primecell÷þqL •apb_pclkçusb@fe800000rockchip,rk3399-dwc3+‚0�ƒöøôùG•ref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk‰% �usb3-otg¡okayusb@fe800000 snps,dwc3÷þ€¨i�öƒ•refbus_earlysuspendðhosts56xusb2-phyusb3-phy øutmi_wide:St/¡okayusb@fe900000rockchip,rk3399-dwc3+‚0‚„÷øôùG•ref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk‰& �usb3-otg¡okayusb@fe900000 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¡disabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spi÷ÿ K_•spiclkapb_pclk¨„–`` ›txrxdefault%abcd/+ ¡disabledthermal-zonescpu-thermal¥d»èÉetripscpu_alert0ÙpåÐòpassiveäfcpu_alert1Ù$øåÐòpassiveägcpu_critÙsåÐ òcriticalcooling-mapsmap0ðfõÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1ðgHõÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿgpu-thermal¥d»èÉetripsgpu_alert0Ù$øåÐòpassiveähgpu_critÙsåÐ òcriticalcooling-mapsmap0ðh õiÿÿÿÿÿÿÿÿtsadc@ff260000rockchip,rk3399-tsadc÷ÿ&¨alOf q°Od•tsadcapb_pclk‰è �tsadc-apb=sinitdefaultsleep%jk%j/¡okayE\äeqos@ffa58000rockchip,rk3399-qossyscon÷ÿ¥€ äsqos@ffa5c000rockchip,rk3399-qossyscon÷ÿ¥À ätqos@ffa60080rockchip,rk3399-qossyscon÷ÿ¦€ qos@ffa60100rockchip,rk3399-qossyscon÷ÿ¦ qos@ffa60180rockchip,rk3399-qossyscon÷ÿ¦€ qos@ffa70000rockchip,rk3399-qossyscon÷ÿ§ äwqos@ffa70080rockchip,rk3399-qossyscon÷ÿ§€ äxqos@ffa74000rockchip,rk3399-qossyscon÷ÿ§@ äuqos@ffa76000rockchip,rk3399-qossyscon÷ÿ§` ävqos@ffa90000rockchip,rk3399-qossyscon÷ÿ© äyqos@ffa98000rockchip,rk3399-qossyscon÷ÿ©€ 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Rdefault%–‚ ¡disableddfi@ff630000÷ÿc@rockchip,rk3399-dfiy¨ƒy •pclk_ddr_monävideo-codec@ff650000rockchip,rk3399-vpu÷ÿe ¨rq +vepuvdpuëê •aclkhclk ]—/iommu@ff650800rockchip,iommu÷ÿe@¨sëê •aclkiface d/ä—video-codec@ff660000rockchip,rk3399-vdec÷ÿf€¨t í쟞•axiahbcabaccore ]˜/ iommu@ff660480rockchip,iommu ÷ÿf€@ÿfÀ@¨uíì •aclkiface/  dä˜iommu@ff670800rockchip,iommu÷ÿg@¨*áÝ •aclkiface d ¡disabledrga@ff680000rockchip,rk3399-rga÷ÿh¨7Üåm•aclkhclksclk‰jgi �coreaxiahb/!efuse@ff690000rockchip,rk3399-efuse÷ÿi€+} •pclk_efusecpu-id@7÷cpu-leakage@17÷gpu-leakage@18÷center-leakage@19÷cpu-leakage@1a÷logic-leakage@1b÷wafer-info@1c÷dma-controller@ff6d0000arm,pl330arm,primecell÷ÿm@ ¨ q |Ó •apb_pclkä`dma-controller@ff6e0000arm,pl330arm,primecell÷ÿn@ ¨ q |Ô •apb_pclkäOclock-controller@ff750000rockchip,rk3399-pmucru÷ÿu™•xin24m=í “l‚f(Jñä‚clock-controller@ff760000rockchip,rk3399-cru÷ÿv™•xin24m=í “ˆlÀÀ@ÂÁBÉÂCãÞxíDf#g¸€/¯;šÊðÑ€xhÀ<4`õáõáúð€#ÃFõáúð€ׄׄ ë ëÂׄäsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfd÷ÿw+äio-domains"rockchip,rk3399-io-voltage-domain¡okay  K ­š º/ Ç�mipi-dphy-rx0rockchip,rk3399-mipi-dphy-rx0w¥o•dphy-refdphy-cfggrf/ × ¡disabledä®usb2phy@e450rockchip,rk3399-usb2phy÷äP{•phyclkíÚclk_usbphy0_480m¡okayä1host-port ר +linestate¡okay�›ä2otg-port ×0¨ghj+otg-bvalidotg-idlinestate¡okayä5usb2phy@e460rockchip,rk3399-usb2phy÷ä`|•phyclkíÚclk_usbphy1_480m¡okayä3host-port ר +linestate¡okay�›ä4otg-port ×0¨lmo+otg-bvalidotg-idlinestate¡okayä7phy@f780rockchip,rk3399-emmc-phy÷÷€$œ•emmcclk â2 × ¡disabled öä0pcie-phyrockchip,rk3399-pcie-phyŠ•refclk ׉‡�phy¡okayU§fõálŠäphy@ff7c0000rockchip,rk3399-typec-phy÷ÿ|~}•tcpdcoretcpdphy-refl~fúð€/‰•”L�uphyuphy-pipeuphy-tcphy=¡okaydp-port ×ä9usb3-port ×ä6phy@ff800000rockchip,rk3399-typec-phy÷ÿ€€•tcpdcoretcpdphy-refl€fúð€/ ‰�œM�uphyuphy-pipeuphy-tcphy=¡okaydp-port ×ä:usb3-port ×ä8watchdog@ff848000 rockchip,rk3399-wdtsnps,dw-wdt÷ÿ„€|¨xrktimer@ff850000rockchip,rk3399-timer÷ÿ…¨QhZ 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compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4spi0spi1spi2spi3spi4spi5ethernet0mmc0mmc1mmc2cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandleduration-usexit-latency-uscache-levelcache-unifiedentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usrockchip,pmudevfreq-eventsclock-namesstatusinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesnum-lanesvpcie0v9-supplyvpcie1v8-supplyvpcie3v3-supplyinterrupt-controllermax-functionsrockchip,max-outbound-regionspinctrl-namespinctrl-0power-domainsrockchip,grfsnps,txpblassigned-clock-parentsassigned-clocksclock_in_outphy-handlephy-modephy-supplytx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosmax-frequencyfifo-depthbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104assigned-clock-ratescap-mmc-highspeedcd-gpiosdisable-wpvmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs200-1_8vdr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsvref-supplyi2c-scl-rising-time-nsi2c-scl-falling-time-nsreg-shiftreg-io-widthdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosmax-speedvbat-supplyvddio-supplydmasdma-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplyfcs,suspend-voltage-selectorregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-on-in-suspendregulator-suspend-microvoltvbus-supply#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsbt656-supplyaudio-supplysdmmc-supplygpio1830-supply#phy-cellsdrive-impedance-ohmrockchip,enable-strobe-pulldownrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiddc-i2c-busmali-supplygpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsstdout-pathenable-active-highgpioautorepeatdebounce-intervallabellinux,codedefault-state