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.pwmpclk`defaultn0Ý adisabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwmËÿ0Ýyè .pwmpclk`defaultn1Ý adisabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmËÿÝxç .pwmpclk`defaultn2Ý adisabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmËÿÝxç .pwmpclk`defaultn3Ý adisabledpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwmËÿ Ýxç .pwmpclk`defaultn4Ý adisabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwmËÿ0Ýxç .pwmpclk`defaultn5Ý adisabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwmËÿÝÎ .pwmpclk`defaultn6ÝaokayMnpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwmËÿÝÎ .pwmpclk`defaultn7Ý adisabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwmËÿ ÝÎ .pwmpclk`defaultn8Ý adisabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwmËÿ0ÝÎ .pwmpclk`defaultn9Ý adisabledrktimer@ff1a0000rockchip,rk3288-timerËÿ  ÝÔ .pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradcËÿ %Ý%Ò.saradcapb_pclkèúF saradc-apbaokay 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€A…usbaokaymmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcËÿH@ L� Ýš012.biuciuciu-driveciu-sample™¤ðÑ€`defaultnBCDEaokay²ÄÕà mmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcËÿI@ M� Ýœ:;<.biuciuciu-driveciu-sample™¤ðÑ€aokay²Äìô`default nFGHà mmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcËÿJ@ N� Ý›567.biuciuciu-driveciu-sample™¤õá`default nIJKaokay+Ä%L07ô=à J wifi@1Ë M :host-wake`defaultnNnand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcËÿK@ QÝ™-.ahbnfc-WðÑ€nOPQRSTU`default adisabledethernet@ff4e0000rockchip,rk3308-gmacËÿN @:macirq@Ý@BBA@†ÃC[.stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedlrmii`defaultnVWú} stmmaceth;:aokayuoutput‚XU mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22Ë`defaultnY�N �ÃP ¯MMXspi@ff4c0000 rockchip,sfcËÿL@ RÝ=�.clk_sfchclk_sfc nZ[\`default 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compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1mmc2device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsstatusvccio0-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesinterrupt-names#phy-cellsphy-supplypinctrl-namespinctrl-0reg-shiftreg-io-widthuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiosdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyarm,pl330-periph-burst#dma-cellsrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyno-sdionon-removablecap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdsd-uhs-sdr50vqmmc-supplyassigned-clock-ratesphy-modeclock_in_outphy-handlereset-assert-usreset-deassert-usreset-gpios#reset-cells#sound-dai-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathcolordefault-statefunctionlabellinux,default-triggerregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highgpiopwmspwm-supplyregulator-settling-time-up-us