Ð þíTv8H|( úHD4mediatek,mt8395-evkmediatek,mt8395mediatek,mt8195 +"7MediaTek Genio 1200 EVK-P1V2-EMMCaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000ƒ/soc/vpp-merge@1c10f000Š/soc/vpp-merge@1c110000‘/soc/dma-controller@1c104000œ/soc/dma-controller@1c105000§/soc/dma-controller@1c106000²/soc/dma-controller@1c107000½/soc/dma-controller@1c108000È/soc/dma-controller@1c109000Ó/soc/dma-controller@1c10a000Þ/soc/dma-controller@1c10b000é/soc/serial@11001100ñ/soc/ethernet@11021000cpus+cpu@0ûcpuarm,cortex-a55 psci-ec3@=4P`€m@€Œ€™@«€¸ÉØ cpu@100ûcpuarm,cortex-a55 psci-ec3@=4P`€m@€Œ€™@«€¸ÉØ cpu@200ûcpuarm,cortex-a55 psci-ec3@=4P`€m@€Œ€™@«€¸ÉØ cpu@300ûcpuarm,cortex-a55 psci-ec3@=4P`€m@€Œ€™@«€¸ÉØ cpu@400ûcpuarm,cortex-a78 psci-�fÔÀ=P`m@Œ™@«¸ÉØ cpu@500ûcpuarm,cortex-a78 psci-�fÔÀ=P`m@Œ™@«¸ÉØcpu@600ûcpuarm,cortex-a78 psci-�fÔÀ=P`m@Œ™@«¸ÉØcpu@700ûcpuarm,cortex-a78 psci-�fÔÀ=P`m@Œ™@«¸ÉØcpu-mapcluster0core0à core1à core2à core3à core4à core5àcore6àcore7àidle-statesäpscicpu-retention-larm,idle-stateñ2*_:DØcpu-retention-barm,idle-stateñ-*Œ:äØcpu-off-larm,idle-stateñ7*›:HØcpu-off-barm,idle-stateñ2*È:èØl2-cache0cacheKbo@�¸WØl2-cache1cacheKbo@�¸WØl3-cachecacheKb o@�WØdsu-pmu arm,dsu-pmue p ufaildmic-codec dmic-codec|‰Èmt8195-sound™ udisabledfixed-factor-clock-13mfixed-factor-clock«¸¿ÉÔclk13mØ)oscillator-26m fixed-clock«-Œº€Ôclk26mØoscillator-32k fixed-clock«-€Ôclk32kperformance-controller@11bc10mediatek,cpufreq-hw ¼ ½0 çØopp-table-gpuoperating-points-v2Øoopp-390000000 >í€ ‰hopp-410000000 p€ ¡Òopp-431000000 °‰À ¡Òopp-473000000 1h@ º<opp-515000000 ²FÀ º<opp-556000000 !#ã Ò¦opp-598000000 #¤Á€ ëopp-640000000 &%  ëopp-670000000 'ïc€ äopp-700000000 )¹' L¸opp-730000000 +‚ê€ }Œopp-760000000 -L® ®`opp-790000000 /q€ ß4opp-820000000 0à5 opp-850000000 2©ø€ @Üopp-880000000 4s¼ q°pmu-a55arm,cortex-a55-pmu epmu-a78arm,cortex-a78-pmu epsci arm,psci-1.0smctimerarm,armv8-timer @e   soc+ simple-bus!(interrupt-controller@c000000 arm,gic-v33D [    e Øppi-partitionsinterrupt-partition-0p Øinterrupt-partition-1p Øsyscon@10000000 mediatek,mt8195-topckgensyscon«Øsyscon@10001000#mediatek,mt8195-infracfg_aosyscon«yØsyscon@10003000mediatek,mt8195-pericfgsyscon0«ØBpinctrl@10005000mediatek,mt8195-pinctrl€PÑÓÔâëô°B†iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint� ¬�[eë3Øaudio-default-pinspins-cmd-dat4¸=>ABCDEFGHIJKdisp-pwm1-default-pinspins1¸hedp-panel-12v-en-pinsرpins1¸`¿edp-panel-3v3-en-pinsذpins1¸¿eth-default-pinsØ>pins-cc¸UVWXËpins-mdio¸YZÚpins-power¸[\¿pins-rxd¸QRSTpins-txd¸MNOPËeth-sleep-pinsØ?pins-cc¸UVWXpins-mdio¸YZçõpins-rxd¸QRSTpins-txd¸MNOPgpio-keys-pinspins¸jÚi2c0-pinsØ\pins¸ Ïèi2c1-pinsØ]pins¸  Ïèi2c2-pinsØ`pins¸  ÏËi2c6-pinsØXpins¸mmc0-default-pinsØDpins-clk¸zË'fpins-cmd-dat$¸~}|{wvutyÚËepins-rst¸xËemmc0-uhs-pinsØEpins-clk¸zË'fpins-cmd-dat$¸~}|{wvutyÚËepins-ds¸Ë'fpins-rst¸xËemmc1-default-pinsØHpins-clk¸oË'fpins-cmd-dat¸npqrsÚËemmc1-uhs-pinsØIpins-clk¸oË'fpins-cmd-dat¸npqrsÚËemt6360-pinsØYpins¸€Úpcie0-default-pinsØSpins ¸pcie0-idle-pinsØTpins¸õ6pcie1-default-pinsØVpins ¸pwm0-default-pinsØ5pins-cmd-dat¸aspi1-pinsØ6pins¸ˆ‰Š‹õspi-pinsØ9pins¸Œ�Ž�õtouch-pinsØ_pins-irq¸„Úõpins-reset¸…¿uart0-pinsØ0pins¸bcuart1-pinsØ1pins¸defgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+AØ,power-domain@8+AUpower-domain@9 ¸cmfgalto+Apower-domain@10 Apower-domain@11 Apower-domain@12 Apower-domain@13 Apower-domain@14Apower-domain@15ظ @AKà   cvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18o+Apower-domain@168¸â$%&'()Dcvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5o+Apower-domain@17¸ácvppsys1vppsys1-0vppsys1-1oApower-domain@22 ¸$cwepsys-0wepsys-1wepsys-2wepsys-3oApower-domain@23¸cvdec0-0o+Apower-domain@24¸ cvdec1-0oApower-domain@25¸!cvdec2-0oApower-domain@26¸" cvenc0-larbo+Apower-domain@27¸# cvenc1-larboApower-domain@18 ¸ã$$$&cvdosys1vdosys1-0vdosys1-1vdosys1-2o+Apower-domain@19oApower-domain@20oApower-domain@21¸Qchdmi_txApower-domain@28¸%%  cimg-0img-1o+Apower-domain@29Apower-domain@30¸%&cipeipe-0ipe-1oApower-domain@31(¸'''''ccam-0cam-1cam-2cam-3cam-4o+Apower-domain@32 Apower-domain@33!Apower-domain@34"Apower-domain@0oApower-domain@1oApower-domain@2Apower-domain@3Apower-domain@4¸57ccsi_rx_topcsi_rx_top1Apower-domain@5¸( cetherApower-domain@6¸Xn cadspadsp1+oApower-domain@7 ¸g"n2caudioaudio1audio2audio3oAwatchdog@10007000mediatek,mt8195-wdt�pyØ/syscon@1000c000"mediatek,mt8195-apmixedsyssysconÀ«Øtimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerpe ¸)pwrap@10024000mediatek,mt8195-pwrapsyscon@†pwrapeó¸ cspiwrap™$©Ëpmicmediatek,mt6359[3 ÀÞadcmediatek,mt6359-auxadcÔmt6359codecæúregulatorsmediatek,mt6359-regulatorbuck_vs1"vs11 5I!‘Àa}buck_vgpu11"vgpu111€I7‘ˆaÈ ¦}buck_vmodem"vmodem1€IÈà‘*aÈbuck_vpu"vpu1€I7‘ˆaÈ ¦}buck_vcore"vcore1€IÖ ‘ˆaÈ ¦}buck_vs2"vs21 5Ija}buck_vpa"vpa1¡ I7±Ða,buck_vproc2"vproc21€I7‘LaÈ ¦buck_vproc1"vproc11€I7‘LaÈ ¦buck_vcore_sshub "vcore_sshub1€I7buck_vgpu11_sshub "vgpu11_sshub1€I7ldo_vaud18"vaud181w@Iw@að}ldo_vsim1"vsim11ð I/M`ldo_vibr"vibr1O€I2Z ldo_vrf12"vrf121ÈàIÖ }ldo_vusb"vusb1-ÆÀI-ÆÀaÀ}ØCldo_vsram_proc2 "vsram_proc21¡ I½¶‘Lað}ldo_vio18"vio181ð IýàaÀ}ldo_vcamio"vcamio1ð Iýà}ldo_vcn18"vcn181w@Iw@aðldo_vfe28"vfe281*¹€I*¹€axldo_vcn13"vcn131 » IÖ ldo_vcn33_1_bt "vcn33_1_bt1*¹€I5gàldo_vcn33_1_wifi "vcn33_1_wifi1*¹€I5gàldo_vaux18"vaux181w@Iw@að}ldo_vsram_others "vsram_others1¡ I½¶‘ˆaðldo_vefuse"vefuse1ð I„€ldo_vxo22"vxo221w@I!‘À}ldo_vrfck"vrfck1ã`Ið ldo_vrfck_1"vrfck1ëÀIjldo_vbif28"vbif281*¹€I*¹€aðldo_vio28"vio281*¹€I2Z }ldo_vemc"vemc1,@ I2Z ldo_vemc_1"vemc1&% I2Z ØFldo_vcn33_2_bt "vcn33_2_bt12Z I2Z Ø8ldo_vcn33_2_wifi "vcn33_2_wifi1*¹€I5gàldo_va12"va121O€IÖ }ldo_va09"va091 5IO€ldo_vrf18"vrf181ð IžPldo_vsram_md "vsram_md1¡ I½¶‘*aðldo_vufs"vufs1ð IýàØGldo_vm18"vm181ð Iýà}ldo_vbbck"vbbck1ÈàIO€}ldo_vsram_proc1 "vsram_proc11¡ I½¶‘Lað}ldo_vsim2"vsim21ð I/M`ldo_vsram_others_sshub"vsram_others_sshub1¡ I½¶rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi p� †pmifspmimst¸E(cpmif_sys_ckpmif_tmr_ckspmimst_clk_mux™$©Ë+pmic@6mediatek,mt6315-regulatorregulatorsvbuck1"Vbcpu1“àI7a ¦}pmic@7mediatek,mt6315-regulatorregulatorsvbuck1"Vgpu1“àI7a ¦Øinfra-iommu@10315000mediatek,mt8195-iommu-infra1PPPe¾ØPmailbox@10320000mediatek,mt8195-gce2@eâ˸ؒmailbox@10330000mediatek,mt8195-gce3@eä˸Øpscp@10500000mediatek,mt8195-scp0Prp€†sramcfgl1tcmeÎuokay×*Øqclock-controller@10720000mediatek,mt8195-scp_adspr«Ø+dsp@10803000mediatek,mt8195-dsp €0„ †cfgsram,¸XnŠ+#Kcadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_hå,órxtxþ-. udisabledmailbox@10816000mediatek,mt8195-adsp-mboxË�`e¾Ø-mailbox@10817000mediatek,mt8195-adsp-mboxË�pe¿Ø.mt8195-afe-pcm@10890000mediatek,mt8195-audio‰å,e6/ audiosys”¸ÚÛÜÝßg"#neabcd2+ócclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp udisabledØserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uarte� ¸ cbaudbusuokay*04defaultserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uarteŽ ¸ cbaudbusuokay*14defaultserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uarte� ¸ cbaudbus udisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uarteÓ ¸ cbaudbus udisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uarteÔ ¸ cbaudbus udisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uarteÕ ¸ cbaudbus udisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc ¸cmainÔ udisabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0«Ø(spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+ e¿¸™cparent-clksel-clkspi-clk udisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap° e©¸B23$Nlvts-calib-data-1lvts-calib-data-2_Ø­svs@1100bc00mediatek,mt8195-svs¼eǸcmainB42(Nsvs-calibration-datat-calibration-datasvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmàeËå,u¸*0cmainmmuokay4default*5Ø®pwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmðeu¸+Ncmainmm udisabledدspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+eÀ¸™3cparent-clksel-clkspi-clkuokay*64default€ ”@can@0microchip,mcp2518fd¸7�1- À¯8º8spi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ eÁ¸™4cparent-clksel-clkspi-clkuokay*94default€spi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0e¸™5cparent-clksel-clkspi-clk udisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+€eø™<cparent-clksel-clkspi-clk udisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+�eĸ™=cparent-clksel-clkspi-clk udisabledspi@1101d000mediatek,mt8195-spi-slaveÐeŸRcspi™©˜ udisabledspi@1101e000mediatek,mt8195-spi-slaveàeƸScspi™©˜ udisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@eÌÉmacirq.caxiapbmac_mainptp_refrmii_internalmac_cg0¸((RST( ™RST©ÂÃÄå,Ùê:ú; < +6uokay Crgmii-rxidL= W] g''|î‘4defaultsleep*>¢?mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916Ø=stmmac-axi-config¬¼ÌØ:rx-queues-configÖìØ;queue0ýqueue1ýqueue2ýqueue3ýtx-queues-config(>Ø<queue0Pý\queue1Pý\queue2Pý\queue3Pý\usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  -ÿ > †macippc! ?+e€¸/íBcsys_ckref_ckmcu_ckj@Ao }Bguokay”Cusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci†mace�™,-©––$¸/íB$csys_ckref_ckmcu_ckdma_ckxhci_ckuokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #õeƒ¸csourcehclksource_cguokay4defaultstate_uhs*D¢E¢¡ 묾ÍÜíõûL F G #mmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $Çe‡¸$csourcehclksource_cg™©¿uokay4defaultstate_uhs*H¢I¢¡ ë 1 B O ]í J K #mmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %æeˆ¸ Icsourcehclksource_cg™ ©¿ udisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu'€eª¸B23$Nlvts-calib-data-1lvts-calib-data-2_ؤusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> †macippcejLM™./©––$¸(ï($csys_ckref_ckmcu_ckdma_ckxhci_ck }Bhouokay”Cusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 *-ÿ*> †macippc!*?+e™0©–¸(ñ(csys_ckref_ckmcu_ckjNo }Biuokay”Cusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci†mace™1©–¸(csys_ckuokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 +-ÿ+> †macippc!+?+e™2©–¸(ó( csys_ckref_ckmcu_ckjOo }Bjuokay”Cusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci†mace™3©–¸( csys_ckuokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcieûpci+/@ †pcie-mace dÿ8!� ‚ à nP x0¸V#&+K(/cpl_250mtl_26mtl_96mtl_32kperi_26mperi_mem™G©jQ ‡pcie-phyå,mac3 ‘` ¤RRRRuokay 4defaultidle*S¢Tinterrupt-controller[3ØRpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcieûpci+/€@ †pcie-mace dÿ8!�$$ ‚$ $ à nP x(¸WXQ(/cpl_250mtl_26mtl_96mtl_32kperi_26mperi_mem™H©jM ‡pcie-phyå,3 ‘` ¤UUUU udisabled4default*Vinterrupt-controller[3ØUspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2Àe9¸o(( cspisfaxi+ udisabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuseÁ+usb3-tx-imp@184,1„ ²Øfusb3-rx-imp@184,2„ ²Øeusb3-intr@185… ²Ødusb3-tx-imp@186,1† ²Øcusb3-rx-imp@186,2† ²Øbusb3-intr@187‡ ²Øausb2-intr-p0@188,1ˆ ²usb2-intr-p1@188,2ˆ ²usb2-intr-p2@189,1‰ ²usb2-intr-p3@189,2‰ ²pciephy-rx-ln1@190,1� ²Ømpciephy-tx-ln1-nmos@190,2� ²Ølpciephy-tx-ln1-pmos@191,1‘ ²Økpciephy-rx-ln0@191,2‘ ²Øjpciephy-tx-ln0-nmos@192,1’ ²Øipciephy-tx-ln0-pmos@192,2’ ²Øhpciephy-glb-intr@193“ ²Øgdp-data@1ac¬Ø£lvts1-calib@1bc¼Ø2lvts2-calib@1d0Ð8Ø3svs-calib@580€dØ4socinfo-data1@7a0 t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!Äuokayusb-phy@0¸òcref ·ØNt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!Åuokayusb-phy@0¸ôcref ·ØOdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txȸ Ômipi_tx0_pll« · udisabledØ“dsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txɸ Ômipi_tx1_pll« · udisabledØ”i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð"€€eš¿¸W; cmaindma+ udisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð"€e›¿¸W; cmaindma+uokay-€*X4defaultpmic@34mediatek,mt63604 e€ÉIRQB[3*Ychargermediatek,mt6360-chg ÂÝ@ usb-otg-vbus-regulator "usb-otg-vbus1C…(IXáèregulatormediatek,mt6360-regulator ÛZbuck1 "emi_vdd21“àIÖ  ¦}buck2 "emi_vddq1“àIÖ  ¦}ØZldo1 "tp1_p3v012Z I2Z ¦}Ø^ldo2 "panel1_p1v81w@Iw@¦ldo3"vmc_pmu1O€I6ØKldo5 "vmch_pmu1)2àI6ØJldo6 "mt6360_ldo11¡ I ¦ldo7 "emi_vmddr_en1¡ I ¦}i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c Ð "€€eœ¿¸W; cmaindma+ udisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_sÐ0«ØWi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c à"€€e�¿¸[; cmaindma+uokay-€*\4defaulti2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c à"€e“¿¸[; cmaindma+uokay-€*]4defaulttouchscreen@5dgoodix,gt9271] À„ ë„ õ… ^4default*_i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c à "€€e–¿¸[; cmaindma+uokay-€*`4defaulti2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c à0"€€e˜¿¸[; cmaindma+ udisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c à@"€e™¿¸[; cmaindma+ udisabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wàP«Ø[t-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!ãå,uokayusb-phy@0 ¸ð crefda_ref ·ØLusb-phy@700¸ð crefda_ref BabcNintrrx_imptx_imp · ØMt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!äuokayusb-phy@0 ¸î crefda_ref ·Ø@usb-phy@700¸î crefda_ref BdefNintrrx_imptx_imp ·ØAphy@11e80000mediatek,mt8195-pcie-phyè†sifBghijklmGNglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1å, ·uokayØQufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphyúÀ¸ cunipromp · udisabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@¸n0e�Œ‹ Éjobmmugpu #o(å, , , , , 7core0core1core2core3core4 udisabledclock-controller@13fbf000mediatek,mt8195-mfgcfgûð«Ønsyscon@14000000mediatek,mt8195-vppsys0syscon« JpØdma-controller@14001000mediatek,mt8195-mdp3-rdma Jp b  vqå, ƒr€¸<þp p ppp Šdisplay@14002000mediatek,mt8195-mdp3-fg  Jp ¸display@14003000mediatek,mt8195-mdp3-stitch0 Jp0¸display@14004000mediatek,mt8195-mdp3-hdr@ Jp@¸"display@14005000mediatek,mt8195-mdp3-aalPeF JpP¸ å,display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` Jp` b%¸ display@14007000mediatek,mt8195-mdp3-tdshpp Jpp¸#display@14008000mediatek,mt8195-mdp3-color€eI Jp€¸$å,display@14009000mediatek,mt8195-mdp3-ovl�eJ Jp�¸%å, ƒr‚display@1400a000mediatek,mt8195-mdp3-padding  Jp ¸å,display@1400b000mediatek,mt8195-mdp3-tcc° Jp°¸dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotÀ JpÀ b +¸ ƒrƒå, Šmutex@1400f000mediatek,mt8195-vpp-mutexðeP Jpð¸å,smi@14010000mediatek,mt8195-smi-sub-common¸capbsmigals0 •så,Øtsmi@14011000mediatek,mt8195-smi-sub-common¸capbsmigals0 •så,Ø‘smi@14012000mediatek,mt8195-smi-common-vpp  ¸capbsmigals0gals1å,Øslarb@14013000mediatek,mt8195-smi-larb0 ¢ •t¸capbsmiå,Øwiommu@14018000mediatek,mt8195-iommu-vpp€8 ³uvwxyz{|}~€�‚eR¸cbclk¾å,Ørclock-controller@14e00000mediatek,mt8195-wpesysà«Øclock-controller@14e02000mediatek,mt8195-wpesys_vpp0à «clock-controller@14e03000mediatek,mt8195-wpesys_vpp1à0«larb@14e04000mediatek,mt8195-smi-larbà@ ¢ •ƒ¸capbsmiå,ؘlarb@14e05000mediatek,mt8195-smi-larbàP ¢ •s¸ capbsmigalså,Øysyscon@14f00000mediatek,mt8195-vppsys1sysconð« Jp Ømutex@14f01000mediatek,mt8195-vpp-mutexðe{ Jp ¸'å,larb@14f02000mediatek,mt8195-smi-larbð  ¢ •ƒ¸ capbsmigalså,Ø—larb@14f03000mediatek,mt8195-smi-larbð0 ¢ •t¸ capbsmigalså,Øxdisplay@14f06000mediatek,mt8195-mdp3-splitð` Jp `¸+,å,display@14f07000mediatek,mt8195-mdp3-tccðp Jp p¸dma-controller@14f08000mediatek,mt8195-mdp3-rdmað€ Jp € b„¨¸ ƒ„ å, Šdma-controller@14f09000mediatek,mt8195-mdp3-rdmað� Jp � b…©¸  ƒ„¤å, Šdma-controller@14f0a000mediatek,mt8195-mdp3-rdmað  Jp   b†ª¸  ƒrÀå, Šdisplay@14f0b000mediatek,mt8195-mdp3-fgð° Jp °¸ display@14f0c000mediatek,mt8195-mdp3-fgðÀ Jp À¸ display@14f0d000mediatek,mt8195-mdp3-fgðÐ Jp и display@14f0e000mediatek,mt8195-mdp3-hdrðà Jp à¸display@14f0f000mediatek,mt8195-mdp3-hdrðð Jp ð¸display@14f10000mediatek,mt8195-mdp3-hdrñ Jp ¸ display@14f11000mediatek,mt8195-mdp3-aalñei Jp ¸å,display@14f12000mediatek,mt8195-mdp3-aalñ ej Jp ¸å,display@14f13000mediatek,mt8195-mdp3-aalñ0ek Jp 0¸!å,display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszñ@ Jp @ b�¯¸display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszñP Jp P b‘°¸$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszñ` Jp ` b’±¸%display@14f17000mediatek,mt8195-mdp3-tdshpñp Jp p¸display@14f18000mediatek,mt8195-mdp3-tdshpñ€ Jp €¸(display@14f19000mediatek,mt8195-mdp3-tdshpñ� Jp �¸)display@14f1a000mediatek,mt8195-mdp3-mergeñ  Jp  ¸å,display@14f1b000mediatek,mt8195-mdp3-mergeñ° Jp °¸å,display@14f1c000mediatek,mt8195-mdp3-colorñÀet Jp À¸å,display@14f1d000mediatek,mt8195-mdp3-colorñÐ Jp Ðeu¸å,display@14f1e000mediatek,mt8195-mdp3-colorñàev Jp à¸å,display@14f1f000mediatek,mt8195-mdp3-ovlñðew Jp ð¸å, ƒ„¢display@14f20000mediatek,mt8195-mdp3-paddingò Jp ¸å,display@14f21000mediatek,mt8195-mdp3-paddingò Jp ¸å,display@14f22000mediatek,mt8195-mdp3-paddingò  Jp ¸å,dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotò0 Jp 0 bŸ«¸ ƒ„£å, Šdma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotò@ Jp @ b ¬¸ ƒ„¦å, Šdma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotòP Jp P b¡­¸ ƒrÂå, Šclock-controller@15000000mediatek,mt8195-imgsys«Ø%larb@15001000mediatek,mt8195-smi-larb ¢  •…¸%%%  capbsmigalså,Ø™smi@15002000mediatek,mt8195-smi-sub-common ¸%%capbsmigals0 •så,؈smi@15003000mediatek,mt8195-smi-sub-common0¸%%% capbsmigals0 •ƒå,Ø…clock-controller@15110000 mediatek,mt8195-imgsys1_dip_top«؆larb@15120000mediatek,mt8195-smi-larb ¢  •…¸%†capbsmiå,Øšclock-controller@15130000mediatek,mt8195-imgsys1_dip_nr«clock-controller@15220000mediatek,mt8195-imgsys1_wpe"«؇larb@15230000mediatek,mt8195-smi-larb# ¢  •…¸%‡capbsmiå,Ø›clock-controller@15330000mediatek,mt8195-ipesys3«Ø&larb@15340000mediatek,mt8195-smi-larb4 ¢  •ˆ¸&&capbsmiå,Øzclock-controller@16000000mediatek,mt8195-camsys«Ø'larb@16001000mediatek,mt8195-smi-larb ¢  •‰¸''' capbsmigalså,Øœlarb@16002000mediatek,mt8195-smi-larb  ¢ •Џ''capbsmiå,Ø{smi@16004000mediatek,mt8195-smi-sub-common@¸'''capbsmigals0 •ƒå,؉smi@16005000mediatek,mt8195-smi-sub-commonP¸''capbsmigals0 •så,ØŠlarb@16012000mediatek,mt8195-smi-larb  ¢ •Џ‹‹capbsmiå, Ø|larb@16013000mediatek,mt8195-smi-larb0 ¢ •‰¸ŒŒcapbsmiå, Ø�larb@16014000mediatek,mt8195-smi-larb@ ¢ •Џ��capbsmiå,!Ø‚larb@16015000mediatek,mt8195-smi-larbP ¢ •‰¸ŽŽcapbsmiå,!Ø¢clock-controller@1604f000mediatek,mt8195-camsys_rawað«Ø‹clock-controller@1606f000mediatek,mt8195-camsys_yuvað«ØŒclock-controller@1608f000mediatek,mt8195-camsys_rawbð«Ø�clock-controller@160af000mediatek,mt8195-camsys_yuvb ð«ØŽclock-controller@16140000mediatek,mt8195-camsys_mraw«Ø�larb@16141000mediatek,mt8195-smi-larb ¢ •‰¸'�' capbsmigalså,"Ø¡larb@16142000mediatek,mt8195-smi-larb  ¢ •Џ��capbsmiå,"Ø�clock-controller@17200000mediatek,mt8195-ccusys «Ø�larb@17201000mediatek,mt8195-smi-larb  ¢ •Џ��capbsmiå,Ø}video-codec@18000000mediatek,mt8195-vcodec-dec vq ƒ„ + @!`video-codec@2000mediatek,mtk-vcodec-lat-soc  ƒràrá ¸A�cselvdeclattop™A©�å,video-codec@10000mediatek,mtk-vcodec-lateÄ0 ƒ„„„„„„ ¸A�cselvdeclattop™A©�å,video-codec@25000mediatek,mtk-vcodec-corePeÃP ƒ„ „¡„¢„£„¤„¥„¦„§„¨„© ¸A  �cselvdeclattop™A©�å,larb@1800d000mediatek,mt8195-smi-larbÐ ¢ •ƒ¸capbsmiå,Ø larb@1800e000mediatek,mt8195-smi-larbà ¢ •‘¸capbsmiå,Ø€clock-controller@1800f000mediatek,mt8195-vdecsys_socð«Ølarb@1802e000mediatek,mt8195-smi-larbà ¢ •ƒ¸ capbsmiå,ØŸclock-controller@1802f000mediatek,mt8195-vdecsysð«Ø larb@1803e000mediatek,mt8195-smi-larbà ¢ •‘¸!capbsmiå,Øclock-controller@1803f000mediatek,mt8195-vdecsys_core1ð«Ø!clock-controller@190f3000mediatek,mt8195-apusys_pll0«clock-controller@1a000000mediatek,mt8195-vencsys«Ø"larb@1a010000mediatek,mt8195-smi-larb ¢ •ƒ¸""capbsmiå,Øžvideo-codec@1a020000mediatek,mt8195-vcodec-encH ƒ„`„a„b„c„d„v„w„x„yeU vq¸" cvenc_sel™@©�å,+jpgdec-mastermediatek,mt8195-jpgdecå,0 ƒ„m„n„r„s„t„u+!jpgdec@1a040000mediatek,mt8195-jpgdec-hw0 ƒ„m„n„r„s„t„ueW¸"cjpgdecå,jpgdec@1a050000mediatek,mt8195-jpgdec-hw0 ƒ„m„n„r„s„t„ueX¸"cjpgdecå,jpgdec@1b040000mediatek,mt8195-jpgdec-hw0 ƒr�rŽr’r“r”r•e\¸#cjpgdecå,clock-controller@1b000000mediatek,mt8195-vencsys_core1«Ø#syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon  þ’« J’ Øjpgenc-mastermediatek,mt8195-jpgencå, ƒr‡rˆr‰rŒ+!jpgenc@1a030000mediatek,mt8195-jpgenc-hw ƒ„g„h„i„leV¸"cjpgencå,jpgenc@1b030000mediatek,mt8195-jpgenc-hw ƒr‡rˆr‰rŒe[¸#cjpgencå,larb@1b010000mediatek,mt8195-smi-larb ¢ •s¸##  capbsmigalså,Ø~ovl@1c000000mediatek,mt8195-disp-ovle|å,¸ ƒ„ J’rdma@1c002000mediatek,mt8195-disp-rdma e~å,¸ ƒ„ J’ color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color0eå,¸ J’0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr@e€å,¸ J’@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalPe�å,¸ J’Pgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma`e‚å,¸ J’`dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherpeƒå,¸  J’pdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi€e„å,¸*“cenginedigitalhsj“ ‡dphy udisableddsc@1c009000mediatek,mt8195-disp-dsc�e…å,¸ J’�dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi eŽå,¸+”cenginedigitalhsj” ‡dphy udisabledmerge@1c014000mediatek,mt8195-disp-merge@e�å,¸ J’@dp-intf@1c015000mediatek,mt8195-dp-intfPe‘¸,cpixelenginepll udisabledmutex@1c016000mediatek,mt8195-disp-mutex`e’å,¸ J’` bUlarb@1c018000mediatek,mt8195-smi-larb€ ¢ •ƒ¸((  capbsmigalså,Ø•larb@1c019000mediatek,mt8195-smi-larb� ¢ •s¸(  capbsmigalså,Øusyscon@1c100000mediatek,mt8195-vdosys1syscon þ’ J’«yØ$smi@1c01b000mediatek,mt8195-smi-common-vdo° ¸%&)$capbsmigals0gals1å,؃iommu@1c01f000mediatek,mt8195-iommu-vdoð8 ³•–—˜™š›œ�žŸ ¡¢e�¾¸'cbclkå,Ø„mutex@1c101000mediatek,mt8195-disp-mutexeîå,¸$ J’ bÀlarb@1c102000mediatek,mt8195-smi-larb  ¢ •ƒ¸$$$ capbsmigalså,Ø–larb@1c103000mediatek,mt8195-smi-larb0 ¢ •s¸$$  capbsmigalså,Øvdma-controller@1c104000mediatek,mt8195-vdo1-rdma@eï¸$å, ƒ„@ J’@ Šdma-controller@1c105000mediatek,mt8195-vdo1-rdmaPeð¸$å, ƒr` J’P Šdma-controller@1c106000mediatek,mt8195-vdo1-rdma`eñ¸$å, ƒ„A J’` Šdma-controller@1c107000mediatek,mt8195-vdo1-rdmapeò¸$å, ƒra J’p Šdma-controller@1c108000mediatek,mt8195-vdo1-rdma€eó¸$å, ƒ„B J’€ Šdma-controller@1c109000mediatek,mt8195-vdo1-rdma�eô¸$å, ƒrb J’� Šdma-controller@1c10a000mediatek,mt8195-vdo1-rdma eõ¸$å, ƒ„C J’  Šdma-controller@1c10b000mediatek,mt8195-vdo1-rdma°eö¸$å, ƒrc J’° Švpp-merge@1c10c000mediatek,mt8195-disp-mergeÀe÷¸$ $cmergemerge_asyncå, J’À Â$vpp-merge@1c10d000mediatek,mt8195-disp-mergeÐeø¸$ $cmergemerge_asyncå, J’Ð Â$vpp-merge@1c10e000mediatek,mt8195-disp-mergeàeù¸$ $cmergemerge_asyncå, J’à Â$vpp-merge@1c10f000mediatek,mt8195-disp-mergeðeú¸$ $cmergemerge_asyncå, J’ð Â$vpp-merge@1c110000mediatek,mt8195-disp-mergeeû¸$ $cmergemerge_asyncå, J’ Ö$dp-intf@1c113000mediatek,mt8195-dp-intf0eå,¸$/$cpixelenginepll udisabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp@Pp� °À4†mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp J’@’P’p’�’ ’°’Àh¸$%$ $#$!$$$"$1$&$'$($)$*ƒcmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_topå, ƒrdree($3$4$5$6$7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-txP€B£Ndp_calibration_dataå,e¤ í¤ udisableddp-tx@1c600000mediatek,mt8195-dp-tx`€B£Ndp_calibration_dataå,eÊ í¤ udisabledthermal-zonescpu0-thermal þè ú "¤tripstrip-alert 2L >ÐpassiveØ¥trip-crit 2†  >Ð criticalcooling-mapsmap0 I¥0 N ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿcpu1-thermal þè ú "¤tripstrip-alert 2L >Ðpassiveئtrip-crit 2†  >Ð criticalcooling-mapsmap0 I¦0 N ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿcpu2-thermal þè ú "¤tripstrip-alert 2L >Ðpassiveاtrip-crit 2†  >Ð criticalcooling-mapsmap0 I§0 N ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿcpu3-thermal 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criticalimg-thermal þè ú "­ tripstrip-alert 2L >Ðpassivetrip-crit 2†  >Ð criticalinfra-thermal þè ú "­tripstrip-alert 2L >Ðpassivetrip-crit 2†  >Ð criticalcam0-thermal þè ú "­tripstrip-alert 2L >Ðpassivetrip-crit 2†  >Ð criticalcam1-thermal þè ú "­tripstrip-alert 2L >Ðpassivetrip-crit 2†  >Ð criticalchosen ]serial0:921600n8firmwareopteelinaro,optee-tzsmcmemory@40000000ûmemory@reserved-memory+!optee@43200000 iC Àmemory@50000000shared-dma-poolP� iØ*memory@53000000shared-dma-poolS@memory@54600000 iT` memory@60000000shared-dma-pool` imemory@62000000shared-dma-poolb@backlight-lcd0pwm-backlight p®¡  u/ ‚ÿ ”ÿ «@backlight-lcd1pwm-backlight p¯¡  u. ‚ÿ ”ÿ «@can-clk fixed-clock«-1-Ôcan-clkØ7regulator-0regulator-fixed"edp_panel_3v312Z I2Z  Ä b4default*°regulator-1regulator-fixed"edp_backlight_12v1·I· Ä b`4default*±gpio-keys gpio-keysbutton-volume-upo ×d —j évolume_up ïsregulator-2regulator-fixed "wifi_3v312Z I2Z  b‡ Ä} compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0ethernet0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxoutput-highdrive-strengthinput-enableinput-disablebias-disablebias-pull-updrive-strength-microampbias-pull-downoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extended#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellsmemory-regionpower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-0pinctrl-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectcs-gpiosspi-max-frequencyvdd-supplyxceiver-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlesnps,reset-gpiosnps,reset-delays-usmediatek,tx-delay-psmediatek,mac-wolpinctrl-1snps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupvusb33-supplybus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN3-supplyirq-gpiosreset-gpiosAVDD28-supplymediatek,force-modeoperating-points-v2power-domain-namesmediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathno-mappwmsenable-gpiosbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-active-highdebounce-intervallabellinux,code