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X”Óÿopp-556000000¾!#ãÅ ‰hÓÿopp-598000000¾#¤Á€Å º<Óÿopp-640000000¾&% Å ëÓÿopp-670000000¾'ïc€Å äÓÿopp-700000000¾)¹'Å L¸Óÿopp-730000000¾+‚ê€Å }ŒÓÿopp-760000000¾-L®Å ®`Óÿopp-790000000¾/q€Å ß4Óÿopp-835000000¾1ÅÀÅ (rÓÿopp-880000000¾4s¼Å q°Óÿopp-915000000¾6‰ÊÀÅ ÓXÓ�opp-915000000-5¾6‰ÊÀÅ ¢„Ó0opp-915000000-6¾6‰ÊÀÅ q°Ópopp-950000000¾8ŸÙ€Å 5Ó�opp-950000000-5¾8ŸÙ€Å ÓXÓ0opp-950000000-6¾8ŸÙ€Å q°Óppmu-a55arm,cortex-a55-pmu äpmu-a78arm,cortex-a78-pmu äpsci arm,psci-1.0Tsmcthermal-zonescpu-little0-thermalïèý–tripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcooling-mapsmap0:H?ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿcpu-little1-thermalïèý–tripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcooling-mapsmap0:H?ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿcpu-little2-thermalïèý–tripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcooling-mapsmap0:H?ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿcpu-little3-thermalïèý–tripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcooling-mapsmap0:H?ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿcpu-big0-thermalïèýdtripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcooling-mapsmap0:?ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-big1-thermalïèýdtripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcooling-mapsmap0:?ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿapu-thermalïèýútripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalgpu-thermalïèýútripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcooling-mapsmap0: ?ÿÿÿÿÿÿÿÿgpu1-thermalïèýútripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcooling-mapsmap0: ?ÿÿÿÿÿÿÿÿadsp-thermalïèýútripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalvdo-thermalïèýútripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalinfra-thermalïèýútripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcam1-thermalïèýútripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticalcam2-thermalïèýútripstrip-alert0#L/ÐDpassivetrip-alert1#s/ÐDhottrip-crit#† / Dcriticaltimerarm,armv8-timer @ä   [Æ]@soc+ simple-busNinterrupt-controller@c000000 arm,gic-v3Uf } I   ä ppi-partitionsinterrupt-partition-0’ interrupt-partition-1’syscon@10000000 mediatek,mt8188-topckgensysconI“ syscon@10001000#mediatek,mt8188-infracfg-aosysconI“›!syscon@10003000mediatek,mt8188-pericfgsysconI0“;pinctrl@10005000mediatek,mt8188-pinctrl`IPÀáâê°0¨iocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint²Âΰ}äëUaudio-default-pinspins-cmd-datXÚefghijklmnrstuvyz|}~€�dptx-pinspins-cmd-datÚ.áedp-panel-3v3-en-pinsZpins1Úîeth-default-pinspins-ccÚ‹Œ�Žúpins-mdioÚ��ú pins-powerÚ‘’îpins-rxdÚ‡ˆ‰Šúpins-txdÚƒ„…†úeth-sleep-pinspins-ccÚ‹Œ�Žpins-mdioÚ��$pins-rxdÚ‡ˆ‰Špins-txdÚƒ„…†i2c0-pinsGpinsÚ87áË1èi2c1-pinsPpinsÚ:9áË1èi2c2-pinsKpinsÚ<;áË1èi2c3-pinsLpinsÚ>=áË1èi2c4-pinsQpinsÚ@?áË1èi2c5-pinsTpinsÚBAáË1èi2c6-pinsUpinsÚDCáË1ègpio-key-pinspins Ú*+,mmc0-default-pins>pins-clkÚ�úIfpins-cmd-dat$Ú¡ Ÿžš™˜—œ úáepins-rstÚ›úáemmc0-uhs-pins?pins-clkÚ�úIfpins-cmd-dat$Ú¡ Ÿžš™˜—œ úáepins-dsÚ¢úIfpins-rstÚ›úáemmc1-default-pinsBpins-clkÚ¤úIfpins-cmd-datÚ£¥¦§¨ úáepins-insertÚámmc1-uhs-pinsCpins-clkÚ¤úIfpins-cmd-datÚ£¥¦§¨ úáemmc2-default-pinspins-clkÚªúIfpins-cmd-datÚ©«¬­® úáepins-pcmÚ{mmc2-uhs-pinspins-clkÚªúIfpins-cmd-datÚ©«¬­® úáemmc2-eint-pinspins-dat1Ú¬ áemmc2-dat1-pinspins-dat1Ú¬ úáepanel-default-pinspins-dcdcÚ-Xpins-enÚoXpins-rstÚîrt1715-int-pinsRpins_cmd0_datÚ á spi0-pinspins-spiÚEFGH$spi1-pinspins-spiÚKLMN$spi2-pins8pins-spiÚOPQR$touch-pinsJpins-irqÚ $pins-resetÚîuart0-pins4pinsÚ áuart1-pins5pinsÚ!"áuart2-pins6pinsÚ#$áusb-default-pinspins-iddigÚS ápins-validÚU pins-vbusÚTîusb1-default-pinspins-validÚX pins-usb-hub-3v3-enÚpîwifi-pwrseq-pinspins-wifi-enableÚXsyscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfdI`power-controller!mediatek,mt8188-power-controller+cXpower-domain@0I+cpower-domain@1Iw ~mfgaltŠ!+cpower-domain@2Icpower-domain@3Icpower-domain@4Icpower-domain@15Iàw    3 4 = ¹ ¾" " """"""""""""""""" û~topcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1Š!+cpower-domain@16IHw » À#######A~cfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-busŠ!+cpower-domain@20I0w º ¿$$$$8~cfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6Š!cpower-domain@23Iw%~ss-vdecŠ!cpower-domain@22Iw&~ss-vdecŠ!cpower-domain@29I w   ½~camccubuscfgckŠ!+cpower-domain@30I(w'''''6~ss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsysŠ!+cpower-domain@32I w'()$~ss-camb-subss-camb-rawss-camb-yuvcpower-domain@31Iw'*+$~ss-cama-subss-cama-rawss-cama-yuvcpower-domain@17I(w ¼ Á,,,&~cfgckcfgxoss-larb2ss-larb3ss-galsŠ!+cpower-domain@9I w @ ? ~bushdcpŠ!cpower-domain@18IŠ!cpower-domain@19IŠ!cpower-domain@24I w----0~ss-ve1-larbss-ve1-coress-ve1-galsss-ve1-sramŠ!cpower-domain@21Iw..~ss-wpe-l7ss-wpe-l7pceŠ!cpower-domain@5IŠ!w/ ~ss-pextp-fmemcpower-domain@7Iw 0 1~seninf0seninf1cpower-domain@6Icpower-domain@10I w E D ~busmainŠ!+cpower-domain@11I Š!+cpower-domain@14Iw F~asmŠ!cpower-domain@13I w S 0~a1sysintbusadspckŠ!cpower-domain@12I Š!cpower-domain@8Iw/  ~ethermacŠ!cwatchdog@10007000mediatek,mt8188-wdtIpœ›syscon@1000c000"mediatek,mt8188-apmixedsyssysconIÀ“timer@10017000,mediatek,mt8188-timermediatek,mt6765-timerIpä w1pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsysconI@¨pwrapäów!! ~spiwrappmicmediatek,mt6359}U äÞadcmediatek,mt6359-auxadc´mt6359codecÆÚregulatorsmediatek,mt6359-regulatorbuck_vs1îvs1ý 5!‘À-Ibuck_vgpu11îvgpu11ý€7]ˆ-È rIbuck_vmodemîvmodemý€Èà]*-Èbuck_vpuîvpuý€7]ˆ-È rIbuck_vcoreîvcoreý€Ö ]ˆ-È rIbuck_vs2îvs2ý 5j-Ibuck_vpaîvpaý¡ /M`-,Dbuck_vproc2îvproc2ý€7]L-È rbuck_vproc1îvproc1ý€7]L-È rbuck_vcore_sshub îvcore_sshubý€7buck_vgpu11_sshub îvgpu11_sshubý€7ldo_vaud18îvaud18ýw@w@-ðldo_vsim1îvsim1ýð /M`-àEldo_vibrîvibrýO€2Z ldo_vrf12îvrf12ýÈàÖ Ildo_vusbîvusbý-ÆÀ-ÆÀ-ÀI<ldo_vsram_proc2 îvsram_proc2ý¡ ½¶]L-ðIldo_vio18îvio18ýð ýà-ÀIIldo_vcamioîvcamioýð ýàldo_vcn18îvcn18ýw@w@-ðIldo_vfe28îvfe28ý*¹€*¹€-xldo_vcn13îvcn13ý » Ö ldo_vcn33_1_bt îvcn33_1_btý*¹€5gàldo_vcn33_1_wifi îvcn33_1_wifiý*¹€5gàldo_vaux18îvaux18ýw@w@-ðIldo_vsram_others îvsram_othersý¡ ½¶]ˆ-ðldo_vefuseîvefuseýð „€ldo_vxo22îvxo22ýw@!‘ÀIldo_vrfckîvrfckýã`ð ldo_vrfck_1îvrfckýëÀjldo_vbif28îvbif28ý*¹€*¹€-ðldo_vio28îvio28ý*¹€2Z Ildo_vemcîvemcý,@ 2Z ldo_vemc_1îvemcý&% 2Z @ldo_vcn33_2_bt îvcn33_2_btý*¹€5gàIldo_vcn33_2_wifi îvcn33_2_wifiý*¹€5gàldo_va12îva12ýO€Ö Ildo_va09îva09ý 5O€ldo_vrf18îvrf18ýð žPldo_vsram_md îvsram_mdý¡ ½¶]*-ðldo_vufsîvufsýð ýàIAldo_vm18îvm18ýð ýàIldo_vbbckîvbbckýÈàO€Ildo_vsram_proc1 îvsram_proc1ý¡ ½¶]L-ðIldo_vsim2îvsim2ýð /M`ldo_vsram_others_sshubîvsram_others_sshubý¡ ½¶rtcmediatek,mt6358-rtcmailbox@10320000mediatek,mt8188-gceI2@äâŠw!Ymailbox@10330000mediatek,mt8188-gceI3@ääŠw!scp@10500000mediatek,mt8188-scp IPr ¨sramcfgäΖ2¤okayclock-controller@10b91100mediatek,mt8188-adsp-audio26mI¹“0serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uartIä� w3! ~baudbus¤okay«4µdefaultserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uartIäŽ w3! ~baudbus¤okay«5µdefaultserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uartIä� w3! ~baudbus¤okay«6µdefaultserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uartIäÓ w3! ~baudbus ¤disabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadcI w!~main´ ¤disabledsyscon@11003000"mediatek,mt8188-pericfg-aosysconI0“/spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+I ä¿w y !~parent-clksel-clkspi-clk ¤disabledthermal-sensor@1100b000mediatek,mt8188-lvts-apI° äÈw!Ã!Ê7Ölvts-calib-data-1çspi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+IäÀw y !2~parent-clksel-clkspi-clk ¤disabledspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+I äÁw y !3~parent-clksel-clkspi-clk¤okay«8µdefaultýspi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+I0äÂw y !4~parent-clksel-clkspi-clk ¤disabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+I€äÃw y !8~parent-clksel-clkspi-clk ¤disabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+I�äÄw y !9~parent-clksel-clkspi-clk ¤disabledusb@11200000'mediatek,mt8188-xhcimediatek,mtk-xhci I  > ¨macippcä�9: ) *& v vw/ Å/ ~sys_ckref_ckmcu_ck =;hT¤okayb<p=mmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc I#õäƒ w !!!M!~sourcehclksource_cgcrypto_clk¤okayµdefaultstate_uhs«>|?†� ëž°¿ÎÛìôúH @A"mmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc I$ëä‡w !!$~sourcehclksource_cg & �¤okayµdefaultstate_uhs«B|C†� ëÂ0AN\ì c DEthermal-sensor@11278000mediatek,mt8188-lvts-mcuI'€äÊw!Ã!Ê7Ölvts-calib-data-1çi2c@11280000mediatek,mt8188-i2c I("€€ä—lwF!7 ~maindma+¤okayµdefault«G[€touchscreen@5dgoodix,gt9271I]  v Š ” H®Iµdefault«Ji2c@11281000mediatek,mt8188-i2c I("€€ä’lwF!7 ~maindma+¤okayµdefault«K[€i2c@11282000mediatek,mt8188-i2c I( "€€ä“lwF!7 ~maindma+¤okayµdefault«L[€clock-controller@11283000mediatek,mt8188-imp-iic-wrap-cI(0“Fusb@112a0000'mediatek,mt8188-xhcimediatek,mtk-xhci I**> ¨macippcäM . -& v vw/ Ë/~sys_ckref_ckmcu_ck¤okayb<usb@112b0000'mediatek,mt8188-xhcimediatek,mtk-xhci I++> ¨macippcäN , +& v vw/ É/~sys_ckref_ckmcu_ck =;`T¤okayb<spi@1132c000(mediatek,mt8188-normediatek,mt8186-norI2Àw X// ~spisfaxi Xä9 ¤disabledi2c@11e00000mediatek,mt8188-i2c Ià"€ä˜lwO!7 ~maindma+¤okayµdefault«P[€i2c@11e01000mediatek,mt8188-i2c Ià"€€ä”lwO!7 ~maindma+¤okayµdefault«Q|R[B@clock-controller@11e02000mediatek,mt8188-imp-iic-wrap-wIà “Ot-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+Nã¤okayusb-phy@0Iw Ê ~refda_ref»Nt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+Nä¤okayusb-phy@0Iw Æ ~refda_ref»9usb-phy@700I w3 ~refda_ref»:t-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+Nè¤okayusb-phy@0Iw Ì ~refda_ref»Mi2c@11ec0000mediatek,mt8188-i2c Iì"€€ä•lwS!7 ~maindma+¤okayµdefault«T[€i2c@11ec1000mediatek,mt8188-i2c Iì"€ä–lwS!7 ~maindma+¤okayµdefault«U[€clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-enIì “Sefuse@11f20000%mediatek,mt8188-efusemediatek,efuseIò+lvts1-calib@1acI¬@7gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jmI@wV0ä~} ÆjobmmugpuÖWêXXXøcore0core1core2÷ ¤disabledclock-controller@13fbf000mediatek,mt8188-mfgcfgIûð“Vclock-controller@14000000mediatek,mt8188-vppsys0I“"clock-controller@14e00000mediatek,mt8188-wpesysIà“.clock-controller@14e02000mediatek,mt8188-wpesys-vpp0Ià “clock-controller@14f00000mediatek,mt8188-vppsys1Ið“$clock-controller@15000000mediatek,mt8188-imgsysI“clock-controller@15110000 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YY,aliases*/soc/serial@11001100chosen2serial0:921600n8firmwareopteelinaro,optee-tzTsmcmemory@40000000=memoryI@reserved-memory+Noptee@43200000>IC Àmemory@50000000shared-dma-poolIP�>2memory@54600000>IT` memory@55000000shared-dma-poolIU@memory@57000000shared-dma-poolIW@regulator-0regulator-fixedî5v_enýLK@LK@ E JIregulator-1regulator-fixedîedp_panel_3v3ý2Z 2Z J Eµdefault«Zregulator-2regulator-fixed îgpio_3v3_ený2Z 2Z  E JIregulator-3regulator-fixedîsdio_ioýw@w@JIregulator-4regulator-fixed îsdio_cardý2Z 2Z  EJJIregulator-5regulator-fixed îtouch_3v3ý2Z 2Z  EwJHregulator-6regulator-fixed îusb_hub_3v3ý2Z 2Z  Ep]'J[regulator-7regulator-fixedîusb_hub_resetýw@w@ En[=regulator-8regulator-fixed îusb_p0_vbusýLK@LK@ ETJregulator-9regulator-fixed îusb_p1_vbusýLK@LK@ EWJregulator-10regulator-fixed îusb_p2_vbusýLK@LK@J compatibleinterrupt-parent#address-cells#size-cellsmodeldevice_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptspolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-deviceranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upoutput-highdrive-strengthinput-enableinput-disablebias-disabledrive-strength-microampbias-pull-downoutput-low#power-domain-cellsclocksclock-namesmediatek,infracfgmediatek,disable-extrst#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#mbox-cellsmemory-regionstatuspinctrl-0pinctrl-namesresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsmediatek,pad-selectphysassigned-clocksassigned-clock-parentsmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplypinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmccd-gpiosclock-divinterrupts-extendedirq-gpiosreset-gpiosAVDD28-supplyVDDIO-supply#phy-cellsinterrupt-namesoperating-points-v2power-domainspower-domain-namesmboxesmediatek,gce-client-regserial0stdout-pathno-mapgpioenable-active-highstartup-delay-usvin-supply