Ð þí!$8Ì(X”$mediatek,mt8195-evbmediatek,mt8195 +!7MediaTek MT8195 evaluation boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000ƒ/soc/vpp-merge@1c10f000Š/soc/vpp-merge@1c110000‘/soc/dma-controller@1c104000œ/soc/dma-controller@1c105000§/soc/dma-controller@1c106000²/soc/dma-controller@1c107000½/soc/dma-controller@1c108000È/soc/dma-controller@1c109000Ó/soc/dma-controller@1c10a000Þ/soc/dma-controller@1c10b000é/soc/serial@11001100cpus+cpu@0ñcpuarm,cortex-a55ýpsci#ec3@34FV€c@u€‚€�@¡€®¿Î cpu@100ñcpuarm,cortex-a55ýpsci#ec3@34FV€c@u€‚€�@¡€®¿Î cpu@200ñcpuarm,cortex-a55ýpsci#ec3@34FV€c@u€‚€�@¡€®¿Î cpu@300ñcpuarm,cortex-a55ýpsci#ec3@34FV€c@u€‚€�@¡€®¿Î cpu@400ñcpuarm,cortex-a78ýpsci#�fÔÀ3FVc@u‚�@¡®¿Î cpu@500ñcpuarm,cortex-a78ýpsci#�fÔÀ3FVc@u‚�@¡®¿Îcpu@600ñcpuarm,cortex-a78ýpsci#�fÔÀ3FVc@u‚�@¡®¿Îcpu@700ñcpuarm,cortex-a78ýpsci#�fÔÀ3FVc@u‚�@¡®¿Îcpu-mapcluster0core0Ö core1Ö core2Ö core3Ö core4Ö core5Öcore6Öcore7Öidle-statesÚpscicpu-retention-larm,idle-stateçþ2 _0DÎcpu-retention-barm,idle-stateçþ- Œ0äÎcpu-off-larm,idle-stateçþ7 ›0HÎcpu-off-barm,idle-stateçþ2 È0èÎl2-cache0cacheAXe@w®MÎl2-cache1cacheAXe@w®MÎl3-cachecacheAX e@wMÎdsu-pmu arm,dsu-pmu[ f kfaildmic-codec dmic-codecr2mt8195-sound� kdisabledfixed-factor-clock-13mfixed-factor-clock¡®µ¿Êclk13mÎ(oscillator-26m fixed-clock¡#Œº€Êclk26mÎoscillator-32k fixed-clock¡#€Êclk32kperformance-controller@11bc10mediatek,cpufreq-hw ý¼ ½0 ÝÎopp-table-gpuoperating-points-v2÷ÎUopp-390000000>í€ ‰hopp-410000000p€ ¡Òopp-431000000°‰À ¡Òopp-4730000001h@ º<opp-515000000²FÀ º<opp-556000000!#ã Ò¦opp-598000000#¤Á€ ëopp-640000000&%  ëopp-670000000'ïc€ äopp-700000000)¹' L¸opp-730000000+‚ê€ }Œopp-760000000-L® ®`opp-790000000/q€ ß4opp-8200000000à5 opp-8500000002©ø€ @Üopp-8800000004s¼ q°pmu-a55arm,cortex-a55-pmu [pmu-a78arm,cortex-a78-pmu [psci arm,psci-1.0smctimerarm,armv8-timer @[   soc+ simple-businterrupt-controller@c000000 arm,gic-v3): Q ý   [ Îppi-partitionsinterrupt-partition-0f Îinterrupt-partition-1f Îsyscon@10000000 mediatek,mt8195-topckgensysconý¡Îsyscon@10001000#mediatek,mt8195-infracfg_aosysconý¡oÎsyscon@10003000mediatek,mt8195-pericfgsysconý0¡Î7pinctrl@10005000mediatek,mt8195-pinctrl€ýPÑÓÔâëô°B|iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint†–¢�Q[ë)Îi2c0-pinsÎDpins® µeÂi2c1-pinsÎEpins®  µeÂi2c4-pinsÎFpins®µeÑèi2c6-pinsÎBpins®µei2c7-pinspins®µenor-pinsÎ@pins0 ®Ž��épins1 ®Œ‚ƒµuart0-pinsÎ.pins®bcsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfdý`power-controller!mediatek,mt8195-power-controller+øÎ*power-domain@8ý+øpower-domain@9ý ® mfgalt+øpower-domain@10ý øpower-domain@11ý øpower-domain@12ý øpower-domain@13ý øpower-domain@14ýøpower-domain@15ýØ® @AKà    vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+øpower-domain@16ý8®â$%&'()D vdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+øpower-domain@17ý®á vppsys1vppsys1-0vppsys1-1øpower-domain@22ý ®$ wepsys-0wepsys-1wepsys-2wepsys-3øpower-domain@23ý® vdec0-0+øpower-domain@24ý® vdec1-0øpower-domain@25ý®  vdec2-0øpower-domain@26ý®!  venc0-larb+øpower-domain@27ý®"  venc1-larbøpower-domain@18ý ®ã###& vdosys1vdosys1-0vdosys1-1vdosys1-2+øpower-domain@19ýøpower-domain@20ýøpower-domain@21ý®Q hdmi_txøpower-domain@28ý®$$   img-0img-1+øpower-domain@29ýøpower-domain@30ý®$% ipeipe-0ipe-1øpower-domain@31ý(®&&&&& cam-0cam-1cam-2cam-3cam-4+øpower-domain@32ý øpower-domain@33ý!øpower-domain@34ý"øpower-domain@0ýøpower-domain@1ýøpower-domain@2ýøpower-domain@3ýøpower-domain@4ý®57 csi_rx_topcsi_rx_top1øpower-domain@5ý®'  etherøpower-domain@6ý®Xn  adspadsp1+øpower-domain@7ý ®g"n2 audioaudio1audio2audio3øwatchdog@10007000mediatek,mt8195-wdt*ýpoÎ-syscon@1000c000"mediatek,mt8195-apmixedsyssysconýÀ¡Îtimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerýp[ ®(pwrap@10024000mediatek,mt8195-pwrapsysconý@|pwrap[ó®  spiwrapB$RËspmi@10027000mediatek,mt8195-spmi ýp� |pmifspmimst®E( pmif_sys_ckpmif_tmr_ckspmimst_clk_muxB$RËinfra-iommu@10315000mediatek,mt8195-iommu-infraý1PPP[iÎ<mailbox@10320000mediatek,mt8195-gceý2@[âv®Îxmailbox@10330000mediatek,mt8195-gceý3@[äv®ÎVscp@10500000mediatek,mt8195-scp0ýPrp€|sramcfgl1tcm[Î kdisabledÎWclock-controller@10720000mediatek,mt8195-scp_adspýr¡Î)dsp@10803000mediatek,mt8195-dsp ý€0„ |cfgsram,®XnŠ)#K adsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h‚*�rxtx›+, kdisabledmailbox@10816000mediatek,mt8195-adsp-mboxvý�`[¾Î+mailbox@10817000mediatek,mt8195-adsp-mboxvý�p[¿Î,mt8195-afe-pcm@10890000mediatek,mt8195-audioý‰¢‚*[6´- »audiosys”®ÚÛÜÝßg"#neabcd2)ó clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp kdisabledÎserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uartý[� ®  baudbuskokayÇdefaultÕ.serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uartý[Ž ®  baudbus kdisabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uartý[� ®  baudbus kdisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uartý[Ó ®  baudbus kdisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uartý[Ô ®  baudbus kdisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uartý[Õ ®  baudbus kdisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadcý ® mainßkokaysyscon@11003000"mediatek,mt8195-pericfg_aosysconý0¡Î'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+ý [¿®™ parent-clksel-clkspi-clk kdisabledthermal-sensor@1100b000mediatek,mt8195-lvts-apý° [©®´ñ/0$ýlvts-calib-data-1lvts-calib-data-2Γsvs@1100bc00mediatek,mt8195-svsý¼[Ç® mainñ1/(ýsvs-calibration-datat-calibration-data´»svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmýà[Ë‚*$®*0 mainmm kdisabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmýð[$®+N mainmm kdisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+ý[À®™3 parent-clksel-clkspi-clk kdisabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ý [Á®™4 parent-clksel-clkspi-clk kdisabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+ý0[®™5 parent-clksel-clkspi-clk kdisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+ý€[î™< parent-clksel-clkspi-clk kdisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+ý�[Ä®™= parent-clksel-clkspi-clk kdisabledspi@1101d000mediatek,mt8195-spi-slaveýÐ[Å®R spiBR˜ kdisabledspi@1101e000mediatek,mt8195-spi-slaveýà[Æ®S spiBR˜ kdisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10aý@[Ì/macirq. axiapbmac_mainptp_refrmii_internalmac_cg0®''RST' BRSTRÂÃÄ‚*?P2`3s4†‘œ kdisabledmdiosnps,dwmac-mdio+stmmac-axi-config©¹ÉÎ2rx-queues-configÓéÎ3queue0ú queue1ú queue2ú queue3ú tx-queues-config%;Î4queue0MúYqueue1MúYqueue2MúYqueue3MúYusb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 ý -ÿ > |macippc ?+[€®/íB sys_ckref_ckmcu_ckg56l z7gkokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhciý|mac[�B,-R––$®/íB$ sys_ckref_ckmcu_ckdma_ckxhci_ckkokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc ý#õ[ƒ® sourcehclksource_cg kdisabledmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc ý$Ç[‡®$ sourcehclksource_cgBR¿ kdisabledmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc ý%æ[ˆ® I sourcehclksource_cgB R¿ kdisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcuý'€[ª®´ñ/0$ýlvts-calib-data-1lvts-calib-data-2Ίusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ý))> |macippc[g89B./R––$®'ï'$ sys_ckref_ckmcu_ckdma_ckxhci_ck z7hlkokayusb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 ý*-ÿ*> |macippc*?+[B0R–®'ñ' sys_ckref_ckmcu_ckg:l z7ikokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhciý|mac[B1R–®' sys_ckkokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 ý+-ÿ+> |macippc+?+[B2R–®'ó'  sys_ckref_ckmcu_ckg;l z7jkokayusb@0'mediatek,mt8195-xhcimediatek,mtk-xhciý|mac[B3R–®'  sys_ckkokay‘pcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcieñpci+ý/@ |pcie-mac[¢ÿ8� ‚ à¬<¶0®V#&+K'/ pl_250mtl_26mtl_96mtl_32kperi_26mperi_memBGRg= Åpcie-phy‚*´»mac)Ï`â>>>> kdisabledinterrupt-controllerQ)Î>pcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcieñpci+ý/€@ |pcie-mac[¢ÿ8�$$ ‚$ $ à¬<¶(®WXQ'/ pl_250mtl_26mtl_96mtl_32kperi_26mperi_memBHRg9 Åpcie-phy‚*)Ï`â???? kdisabledinterrupt-controllerQ)Î?spi@1132c000(mediatek,mt8195-normediatek,mt8173-norý2À[9®o''  spisfaxi+kokayÇdefaultÕ@flash@0jedec,spi-norýðúð€efuse@11c10000%mediatek,mt8195-efusemediatek,efuseýÁ+usb3-tx-imp@184,1ý„ÎLusb3-rx-imp@184,2ý„ÎKusb3-intr@185ý…ÎJusb3-tx-imp@186,1ý†ÎIusb3-rx-imp@186,2ý†ÎHusb3-intr@187ý‡ÎGusb2-intr-p0@188,1ýˆusb2-intr-p1@188,2ýˆusb2-intr-p2@189,1ý‰usb2-intr-p3@189,2ý‰pciephy-rx-ln1@190,1ý�ÎSpciephy-tx-ln1-nmos@190,2ý�ÎRpciephy-tx-ln1-pmos@191,1ý‘ÎQpciephy-rx-ln0@191,2ý‘ÎPpciephy-tx-ln0-nmos@192,1ý’ÎOpciephy-tx-ln0-pmos@192,2ý’ÎNpciephy-glb-intr@193ý“ÎMdp-data@1acý¬Ήlvts1-calib@1bcý¼Î/lvts2-calib@1d0ýÐ8Î0svs-calib@580ý€dÎ1socinfo-data1@7a0ý t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Äkokayusb-phy@0ý®ò refÎ:t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Åkokayusb-phy@0ý®ô refÎ;dsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txýÈ® Êmipi_tx0_pll¡ kdisabledÎydsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txýÉ® Êmipi_tx1_pll¡ kdisabledÎzi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýÐ"€€[šµ®A;  maindma+ kdisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýÐ"€[›µ®A;  maindma+kokayÇdefaultÕB#€i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýÐ "€€[œµ®A;  maindma+ kdisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_sýÐ0¡ÎAi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýà"€€[�µ®C;  maindma+kokayÇdefaultÕD#† i2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýà"€[“µ®C;  maindma+kokayÇdefaultÕE#€i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýà "€€[–µ®C;  maindma+ kdisabledi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýà0"€€[˜µ®C;  maindma+ kdisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýà@"€[™µ®C;  maindma+kokayÇdefaultÕF#€clock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wýàP¡ÎCt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+ã‚*kokayusb-phy@0ý ®ð  refda_refÎ8usb-phy@700ý®ð  refda_ref ñGHIýintrrx_imptx_impÎ9t-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+äkokayusb-phy@0ý ®î  refda_refÎ5usb-phy@700ý®î  refda_ref ñJKLýintrrx_imptx_impÎ6phy@11e80000mediatek,mt8195-pcie-phyýè|sifñMNOPQRSGýglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1‚* kdisabledÎ=ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphyýúÀ®  unipromp kdisabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jmý@®T0[�Œ‹ /jobmmugpuU(‚* * * * *&core0core1core2core3core4 kdisabledclock-controller@13fbf000mediatek,mt8195-mfgcfgýûð¡ÎTsyscon@14000000mediatek,mt8195-vppsys0sysconý¡9VÎdma-controller@14001000mediatek,mt8195-mdp3-rdmaý9VQ eW‚*rX€®<›V V VVVydisplay@14002000mediatek,mt8195-mdp3-fgý 9V ®display@14003000mediatek,mt8195-mdp3-stitchý09V0®display@14004000mediatek,mt8195-mdp3-hdrý@9V@®"display@14005000mediatek,mt8195-mdp3-aalýP[F9VP® ‚*display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszý`9V`Q%® display@14007000mediatek,mt8195-mdp3-tdshpýp9Vp®#display@14008000mediatek,mt8195-mdp3-colorý€[I9V€®$‚*display@14009000mediatek,mt8195-mdp3-ovlý�[J9V�®%‚*rX‚display@1400a000mediatek,mt8195-mdp3-paddingý 9V ®‚*display@1400b000mediatek,mt8195-mdp3-tccý°9V°®dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotýÀ9VÀQ +®rXƒ‚*ymutex@1400f000mediatek,mt8195-vpp-mutexýð[P9Vð®‚*smi@14010000mediatek,mt8195-smi-sub-commoný® apbsmigals0„Y‚*ÎZsmi@14011000mediatek,mt8195-smi-sub-commoný® apbsmigals0„Y‚*Îwsmi@14012000mediatek,mt8195-smi-common-vppý  ® apbsmigals0gals1‚*ÎYlarb@14013000mediatek,mt8195-smi-larbý0‘„Z® apbsmi‚*Î]iommu@14018000mediatek,mt8195-iommu-vppý€8¢[\]^_`abcdefgh[R® bclki‚*ÎXclock-controller@14e00000mediatek,mt8195-wpesysýà¡Îclock-controller@14e02000mediatek,mt8195-wpesys_vpp0ýà ¡clock-controller@14e03000mediatek,mt8195-wpesys_vpp1ýà0¡larb@14e04000mediatek,mt8195-smi-larbýà@‘„i® apbsmi‚*Î~larb@14e05000mediatek,mt8195-smi-larbýàP‘„Y®  apbsmigals‚*Î_syscon@14f00000mediatek,mt8195-vppsys1sysconýð¡9V Îmutex@14f01000mediatek,mt8195-vpp-mutexýð[{9V ®'‚*larb@14f02000mediatek,mt8195-smi-larbýð ‘„i®  apbsmigals‚*Î}larb@14f03000mediatek,mt8195-smi-larbýð0‘„Z®  apbsmigals‚*Î^display@14f06000mediatek,mt8195-mdp3-splitýð`9V `®+,‚*display@14f07000mediatek,mt8195-mdp3-tccýðp9V p®dma-controller@14f08000mediatek,mt8195-mdp3-rdmaýð€9V €Q„¨®rj ‚*ydma-controller@14f09000mediatek,mt8195-mdp3-rdmaýð�9V �Q…©® rj¤‚*ydma-controller@14f0a000mediatek,mt8195-mdp3-rdmaýð 9V  Q†ª® rXÀ‚*ydisplay@14f0b000mediatek,mt8195-mdp3-fgýð°9V °® display@14f0c000mediatek,mt8195-mdp3-fgýðÀ9V À® display@14f0d000mediatek,mt8195-mdp3-fgýðÐ9V Ю display@14f0e000mediatek,mt8195-mdp3-hdrýðà9V à®display@14f0f000mediatek,mt8195-mdp3-hdrýðð9V ð®display@14f10000mediatek,mt8195-mdp3-hdrýñ9V ® display@14f11000mediatek,mt8195-mdp3-aalýñ[i9V ®‚*display@14f12000mediatek,mt8195-mdp3-aalýñ [j9V ®‚*display@14f13000mediatek,mt8195-mdp3-aalýñ0[k9V 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