Ð þí 8úÈ(Wú�>google,tentacruel-sku327681google,tentacruelmediatek,mt8186 +7Google Tentacool board=laptopaliasesJ/soc/ovl@14005000O/soc/ovl@14006000W/soc/rdma@14007000]/soc/rdma@1401f000c/soc/i2c@11007000h/soc/i2c@11008000m/soc/i2c@11009000r/soc/i2c@1100f000w/soc/i2c@11016000|/soc/mmc@11230000�/soc/mmc@11240000†/soc/serial@11002000Ž/soc/i2c@11011000ccimediatek,mt8186-cci“šcciintermediate¦ºÆ"opp-table-ccioperating-points-v2ÎÆopp-500000000ÙÍeà 'ÀÆopp-560000000Ù!`ìà L¸Æopp-612000000Ù$zaà •öÆopp-682000000Ù(¦~€à ÷žÆ opp-752000000Ù,Òœà YFÆ opp-822000000Ù0þ¹€à ºîÆ opp-875000000Ù4'pÀà ëÂÆ opp-927000000Ù7@åÀà 5Æ opp-980000000Ù:i�à ~>Æopp-1050000000Ù>•º€à ßæÆopp-1120000000ÙBÁØà )$Æopp-1155000000ÙD׿Àà ŠÌÆopp-1190000000ÙFíõ€à Ô Æopp-1260000000ÙKà~ðÆopp-1330000000ÙOF0€à)ÖÆopp-1400000000ÙSrNà¼RÆopp-table-cluster0operating-points-v2ÎÆopp-500000000ÙÍeà 'Àîopp-774000000Ù."M€à L¸îopp-875000000Ù4'pÀà ®`îopp-975000000Ù:QÀà î opp-1075000000Ù@2Àà q°î opp-1175000000ÙF Àà ÓXî opp-1275000000ÙKþôÀà 5î opp-1375000000ÙQôÕÀà –¨î opp-1500000000ÙYh/à ºîopp-1618000000Ù`p¸€à Yøîopp-1666000000ÙcM$€à » îopp-1733000000ÙgK{@àHîopp-1800000000ÙkIÒà~ðîopp-1866000000Ùo8æ€àùîopp-1933000000Ùs7=@àZªîopp-2000000000Ùw5”à¼Rîopp-table-cluster1operating-points-v2ÎÆ#opp-774000000Ù."M€à L¸îopp-835000000Ù1ÅÀà •öîopp-919000000Ù6ÆÓÀà ÷žîopp-1002000000Ù;¹N€à YFî opp-1085000000Ù@«É@à ÓXî opp-1169000000ÙE­†@à 5î opp-1308000000ÙMöà ßæî opp-1419000000ÙT”8Àà Yøî opp-1530000000Ù[1ò€à ìtîopp-1670000000ÙcŠ-€à—Zîopp-1733000000ÙgK{@àùîopp-1796000000Ùk Éàsîopp-1860000000ÙnÝYàÔ¼îopp-1923000000Ùrž¦Àà6dîopp-1986000000Ùv_ô€à°vîopp-2050000000Ùz0„€àîcpus+cpu-mapcluster0core0ücore1ücore2ücore3ücore4ücore5ücore6ücore7ücpu@0cpuarm,cortex-a55 psciw5”“šcpuintermediate¦.TH~[ k€x@Š€—€¤@¶€Ã!Ôã"ºÆcpu@100cpuarm,cortex-a55 psciw5”“šcpuintermediate¦.TH~[ k€x@Š€—€¤@¶€Ã!Ôã"ºÆcpu@200cpuarm,cortex-a55 psciw5”“šcpuintermediate¦.TH~[ k€x@Š€—€¤@¶€Ã!Ôã"ºÆcpu@300cpuarm,cortex-a55 psciw5”“šcpuintermediate¦.TH~[ k€x@Š€—€¤@¶€Ã!Ôã"ºÆcpu@400cpuarm,cortex-a55 psciw5”“šcpuintermediate¦.TH~[ k€x@Š€—€¤@¶€Ã!Ôã"ºÆcpu@500cpuarm,cortex-a55 psciw5”“šcpuintermediate¦.TH~[ k€x@Š€—€¤@¶€Ã!Ôã"ºÆcpu@600cpuarm,cortex-a76 psciz0„€“šcpuintermediate¦#.OH[$%kx@Š—¤@¶Ã&Ôã"º'Æcpu@700cpuarm,cortex-a76 psciz0„€“šcpuintermediate¦#.OH[$%kx@Š—¤@¶Ã&Ôã"º'Æidle-statesðpscicpu-retention-larm,idle-stateý%26dF@Æcpu-retention-barm,idle-stateý%26dFxÆ$cpu-off-larm,idle-stateý%d6úF4Æ cpu-off-barm,idle-stateý%d6úFlÆ%l2-cache0cacheWmz@ŒÃ(cÆ!l2-cache1cacheWmz@ŒÃ(cÆ&l3-cachecacheWmz@ŒcÆ(fixed-factor-clock-13mfixed-factor-clockq“)~ˆ“clk13mÆ=oscillator-26m fixed-clockqŒº€“clk26mÆ)oscillator-32k fixed-clockq€“clk32kopp-table-gpuoperating-points-v2Æwopp-299000000ÙÒ`Àà X”¦ÿopp-332000000ÙÉëà ‰h¦ÿopp-366000000Ùз€à º<¦ÿopp-400000000Ùׄà Ò¦¦ÿopp-434000000ÙÞP€à z¦ÿopp-484000000ÙÙAà 4N¦ÿopp-535000000ÙãsÀà }Œ¦ÿopp-586000000Ù"í¦€à ®`¦ÿopp-637000000Ù%÷Ù@à ß4¦ÿopp-690000000Ù) �€à @ܦÿopp-743000000Ù,IGÀà Š¦ÿopp-796000000Ù/qÿà ë¦ÿopp-850000000Ù2©ø€à 5¦ÿopp-900000000-3Ù5¤éà øP¦Ïopp-900000000-4Ù5¤éà Ç|¦opp-900000000-5Ù5¤éà –¨¦ opp-950000000-3Ù8ŸÙ€à » ¦Ïopp-950000000-4Ù8ŸÙ€à Yø¦opp-950000000-5Ù8ŸÙ€à øP¦ opp-1000000000-3Ù;šÊà~ð¦Ïopp-1000000000-4Ù;šÊà ìt¦opp-1000000000-5Ù;šÊà Yø¦ pmu-a55arm,cortex-a55-pmu ·*pmu-a76arm,cortex-a76-pmu ·+psci arm,psci-1.0smctimerarm,armv8-timer @·   soc+ simple-busÂÆinterrupt-controller@c000000 arm,gic-v3ÍÞ õ    ·  Æppi-partitionsinterrupt-partition-0*Æ*interrupt-partition-1*Æ+syscon@c53a000mediatek,mt8186-mcusyssyscon S qÆsyscon@10000000 mediatek,mt8186-topckgensyscon qÆ-syscon@10001000#mediatek,mt8186-infracfg_aosyscon q3Æ/syscon@10003000mediatek,mt8186-pericfgsyscon 0Æipinctrl@10005000mediatek,mt8186-pinctrl€ P "$&*,°B@iocfg0iocfg_ltiocfg_lmiocfg_lbiocfg_bliocfg_rbiocfg_rteintJZf,¹õ·ºÍ ßrTPTPTPI2S0_HP_DII2S3_DP_SPKR_DOSAR_INT_ODLBT_WAKE_AP_ODLWIFI_INT_ODLDPBRDG_INT_ODLEDPBRDG_INT_ODLEC_AP_HPD_ODTCHPAD_INT_ODLTCHSCR_INT_1V8_ODLEC_AP_INT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLAP_FLASH_WP_LHP_INT_ODLPEN_EJECT_ODWCAM_PWDN_LWCAM_RST_LUCAM_SEN_ENUCAM_RST_LLTE_RESET_LLTE_SAR_DETECT_LI2S2_DP_SPK_MCKI2S2_DP_SPKR_BCKI2S2_DP_SPKR_LRCKI2S2_DP_SPKR_DI (TP)EN_PP1000_EDPBRDGEN_PP1800_EDPBRDGEN_PP3300_EDPBRDGUART_GSC_TX_AP_RXUART_AP_TX_GSC_RXUART_DBGCON_TX_ADSP_RXUART_ADSP_TX_DBGCON_RXEN_PP1000_DPBRDGTCHSCR_REPORT_DISABLEEN_PP3300_DPBRDGEN_PP1800_DPBRDGSPI_AP_CLK_ECSPI_AP_CS_EC_LSPI_AP_DO_EC_DISPI_AP_DI_EC_DOSPI_AP_CLK_GSCSPI_AP_CS_GSC_LSPI_AP_DO_GSC_DISPI_AP_DI_GSC_DOUART_DBGCON_TX_SCP_RXUART_SCP_TX_DBGCON_RXEN_PP1200_CAM_XEN_PP2800A_VCM_XEN_PP2800A_UCAM_XEN_PP2800A_WCAM_XWLAN_MODULE_RST_LEN_PP1200_UCAM_XI2S1_HP_DOI2S1_HP_BCKI2S1_HP_LRCKI2S1_HP_MCKTCHSCR_RST_1V8_LSPI_AP_CLK_ROMSPI_AP_CS_ROM_LSPI_AP_DO_ROM_DISPI_AP_DI_ROM_DONCNCEMMC_STRBEMMC_CLKEMMC_CMDEMMC_RST_LEMMC_DATA0EMMC_DATA1EMMC_DATA2EMMC_DATA3EMMC_DATA4EMMC_DATA5EMMC_DATA6EMMC_DATA7AP_KPCOL0NCNCNCTPSDIO_CLKSDIO_CMDSDIO_DATA0SDIO_DATA1SDIO_DATA2SDIO_DATA3NCNCNCNCNCNCEDPBRDG_PWRENBL_PWM_1V8EDPBRDG_RST_LMIPI_DPI_CLKMIPI_DPI_VSYNCMIPI_DPI_HSYNCMIPI_DPI_DEMIPI_DPI_D0MIPI_DPI_D1MIPI_DPI_D2MIPI_DPI_D3MIPI_DPI_D4MIPI_DPI_D5MIPI_DPI_D6MIPI_DPI_DA7MIPI_DPI_D8MIPI_DPI_D9MIPI_DPI_D10MIPI_DPI_D11PCM_BT_CLKPCM_BT_SYNCPCM_BT_DIPCM_BT_DOJTAG_TMS_TPJTAG_TCK_TPJTAG_TDI_TPJTAG_TDO_TPJTAG_TRSTN_TPCLK_24M_WCAMCLK_24M_UCAMUCAM_DET_ODLAP_I2C_EDPBRDG_SCL_1V8AP_I2C_EDPBRDG_SDA_1V8AP_I2C_TCHSCR_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_TCHPAD_SDA_1V8AP_I2C_DPBRDG_SCL_1V8AP_I2C_DPBRDG_SDA_1V8AP_I2C_WLAN_SCL_1V8AP_I2C_WLAN_SDA_1V8AP_I2C_AUD_SCL_1V8AP_I2C_AUD_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_UCAM_SDA_1V8AP_I2C_UCAM_SCL_1V8AP_I2C_UCAM_SDA_1V8AP_I2C_WCAM_SCL_1V8AP_I2C_WCAM_SDA_1V8SCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AP_EC_WARM_RST_REQAP_XHCI_INIT_DONEUSB3_HUB_RST_LEN_SPKRBEEP_ONAP_EDP_BKLTENEN_PP3300_DISP_XEN_PP3300_SDBRDG_XBT_KILL_1V8_LWIFI_KILL_1V8_LPWRAP_SPI0_CSNPWRAP_SPI0_CKPWRAP_SPI0_MOPWRAP_SPI0_MISRCLKENA0SRCLKENA1SCP_VREQ_VAOAP_RTC_CLK32KAP_PMIC_WDTRST_LAUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_CLK_MISOAUD_SYNC_MISOAUD_DAT_MISO0AUD_DAT_MISO1NCNCDPBRDG_PWRENDPBRDG_RST_LLTE_W_DISABLE_LLTE_SAR_DETECT_LEN_PP3300_LTE_XLTE_PWR_OFF_LLTE_RESET_LTPTPÆ,aud-clk-mosi-off-pinsÆ pins-clk-sync‚¦§‰–aud-clk-mosi-on-pinsÆ¡pins-clk-sync‚¦§aud-clk-miso-off-pinsÆ¢pins-clk-sync‚ª«‰–aud-clk-miso-on-pinsÆ£pins-clk-sync‚ª«aud-dat-mosi-off-pinsƦpins-dat‚¨©‰–aud-dat-mosi-on-pinsƧpins-dat‚¨©aud-dat-miso-off-pinsƤpins-dat‚¬­‰–aud-dat-miso-on-pinsÆ¥pins-dat‚¬­¥ºaud-gpio-i2s0-off-pinsƨpins-sdata‚aud-gpio-i2s0-on-pinsÆ©pins-sdata‚aud-gpio-i2s-off-pinsƪpins-clk-sdata‚89:;Çaud-gpio-i2s1-on-pinsÆ«pins-clk-sdata‚89:;aud-gpio-i2s2-off-pinsƬpins-cmd-dat‚Çaud-gpio-i2s2-on-pinsÆ­pins-clk‚Òaud-gpio-i2s3-off-pinsÆ®pins-sdata‚Çaud-gpio-i2s3-on-pinsƯpins-sdata‚Òaud-gpio-pcm-off-pinsưpins-clk-sdata‚stuvÇaud-gpio-pcm-on-pinsƱpins-clk-sdata‚stuvaud-gpio-dmic-sec-pinsƲpins‚Çbt-reset-pinsÆqpins-bt-reset‚›ádpi-sleep-pinsÆ|pins-cmd-dat@‚ghijklmnopqredfcÒ Çdpi-default-pinsÆ{pins-cmd-dat@‚ghijklmnopqredfcÒ cros-ec-int-pinsÆdpins-ec-ap-int-odl‚ ‰edp-panel-fixed-pinsÆŸpins-vreg-en‚™áen-pp1800-dpbrdg-pinsÆžpins-vreg-en‚'Çgsc-int-pinsÆfpins-gsc-ap-int-odl‚‰i2c0-pinsÆGpins-bus‚€ºÒ‰i2c1-pinsÆPpins-bus‚‚�ºÒ‰i2c2-pinsÆSpins-bus‚„ƒºÒ‰i2c3-pinsÆUpins-bus‚†…ºÒ‰i2c5-pinsÆ]pins-bus‚ЉºÒ‰it6505-pinsÆVpins-hpd‚ ‰ípins-int‚‰ípins-reset‚±Çímmc0-default-pinsÆjpins-clk‚D–fpins-cmd-dat$‚GHIJKLMNE‰íepins-rst‚Fíemmc0-uhs-pinsÆkpins-clk‚DÒ–fpins-cmd-dat$‚GHIJKLMNE‰Òíepins-ds‚CÒ–fpins-rst‚Fíemmc1-default-pinsÆmpins-clk‚TÒ–fpins-cmd-dat‚VWXYU‰Òíemmc1-uhs-pinsÆnpins-clk‚TÒ–fpins-cmd-dat‚VWXYU‰Òíemmc1-eint-pinsÆopins-dat1‚W‰íenor-default-pinsÆEpins-clk-dat ‚?=@Ò–pins-cs-dat ‚>ABÒípen-eject-pinsÆ�pins‚‰ºdisp-pwm-pinsÆbpins‚aáspeaker-codec-default-pinsƸpins-sdb‚–Çscp-default-pinsÆ>pins-scp-uart‚01spi1-pinsÆcpins-bus‚()*+º‰spi2-pinsÆepins-bus‚,-./º‰spmi-pinspins-bus‚·¸touchscreen-pinsÆQpins-irq‚ ‰ípins-reset‚<ápins-report-sw‚%Çtrackpad-default-pinsÆTpins-int-n‚ ‰ºwifi-enable-pinsƺpins-wifi-enable‚6wifi-wakeup-pinsÆ»pins-wifi-wakeup‚‰i2c4-pinsÆZpins-bus‚ˆ‡ºÒ‰ps8640-pinsÆHpins-pwrdn-rst‚`bÇsar-sensor-pinsÆ[pins-irq‚‰ísyscon@10006000)mediatek,mt8186-scpsyssysconsimple-mfd `power-controller!mediatek,mt8186-power-controller+úÆBpower-domain@0 “-šmfg00+ú.power-domain@1 /+ú0power-domain@2 úpower-domain@3 úpower-domain@17 “--$šsubsys-csirx-top0subsys-csirx-top1úpower-domain@4 “-/=šsys_ckref_ckúpower-domain@5 “/B/?šsys_ckref_ckúpower-domain@18 “-/->šaudioadspsubsys-adsp-bus+úpower-domain@19 +úpower-domain@20 /úpower-domain@16 /úpower-domain@6 0“-*-+1 111Mšdispmdpsubsys-smi-infrasubsys-smi-commonsubsys-smi-galssubsys-smi-iommu/+úpower-domain@14 “-)2 švdec0larb/úpower-domain@10 8“---- 3-#-%6šcam0cam1cam2cam3galssubsys-cam-tmsubsys-cam-top/+úpower-domain@12 úpower-domain@11 úpower-domain@7 “4-&šgalssubsys-img-top/+úpower-domain@8 úpower-domain@9 (“-'5555Pšsubsys-ipe-topsubsys-ipe-larb0subsys-ipe-larb1subsys-ipe-smisubsys-ipe-gals/úpower-domain@13 “-$6švenc0subsys-larb/úpower-domain@15 “-:77%šwpe0subsys-larb-cksubsys-larb-pclk/úwatchdog@10007000mediatek,mt8186-wdt. p3FÆgsyscon@1000c000"mediatek,mt8186-apmixedsyssyscon ÀqÆpwrap@1000d000mediatek,mt8186-pwrapsyscon Ð@pwrap·Â“// šspiwrappmic mediatek,mt6366mediatek,mt6358õ _,ÉÍcodec,mediatek,mt6366-soundmediatek,mt6358-sounds8regulators4mediatek,mt6366-regulatormediatek,mt6358-regulator’9£9´9Å9×9ê9û99929F9V9f:v;†<–<vcore¦pp0750_dvdd_coreµdpÍ 5åjúÈ.vdram1¦pp1125_emi_vdd2µ*ˆÍ*ˆå0Ôú.Æ;vgpu¦ppvar_dvdd_vgpuµ¡ Í~ðåjúÈB.Y† Æ0vproc11¦ppvar_dvdd_proc_bc_mt6366µ 'ÀÍO€åjúÈ.Æ'vproc12¦ppvar_dvdd_proc_lcµ 'ÀÍO€åjúÈ.Ævs1 ¦pp2000_vs1µ„€Í„€å0Ôú.Æ:vs2 ¦pp1350_vs2µ™pÍ™på0Ôú.Æ<va12 ¦pp1200_va12µO€ÍO€ú.vaud28¦pp2800_vaud28µ*¹€Í*¹€úÆ8vaux18¦pp1840_vaux18µw@Í€úvbif28¦pp2800_vbif28µ*¹€Í*¹€úvcn18¦pp1800_vcn18_xµw@Íw@úvcn28¦pp2800_vcn28_xµ*¹€Í*¹€úvefuse¦pp1800_vefuseµw@Íw@úvfe28¦pp2800_vfe28_xµ*¹€Í*¹€úvemc ¦pp3000_vemcµ-ÆÀÍ-ÆÀú<Ælvibr¦pp2800_vibr_xµ*¹€Í*¹€ú<vio18¦pp1800_vio18_s3µw@Íw@ú Œ.Æ\vio28¦pp2800_vio28_xµ*¹€Í*¹€úvm18¦pp1800_emi_vdd1µw@Í€úE.vmc ¦pp3000_vmcµ-ÆÀÍ-ÆÀú<vmddr¦pm0750_emi_vmddrµ ®`Í q°úE.vmch ¦pp3000_vmchµ-ÆÀÍ-ÆÀú<vcn33¦pp3300_vcn33_xµ2Z Í2Z úÆJvdram2¦pp0600_emi_vddqµ 'ÀÍ 'Àú ä.vrf12¦pp1200_vrf12_xµO€ÍO€úxÆIvrf18¦pp1800_vrf18_xµw@Íw@úxvsim1¦pp1860_vsim1_xµw@Ía úvsim2¦pp2760_vsim2_xµ)2àÍ*@úÆWvsram-gpu¦pp0900_dvdd_sram_gpuµ øPÍ�åjúðB0Y† Æ.vsram-others¦pp0900_dvdd_sram_coreµ » Í » åjúð.vsram-proc11¦pp0900_dvdd_sram_bcµ øPÍåjúð.vsram-proc12¦pp0900_dvdd_sram_lcµ øPÍåjúð.vusb ¦pp3070_vusbµ-ÆÀÍ.Ø0ú.vxo22 ¦pp2240_vxo22µ!‘ÀÍ".úx.rtc(mediatek,mt6366-rtcmediatek,mt6358-rtcspmi@10015000*mediatek,mt8186-spmimediatek,mt8195-spmi  P° @pmifspmimst“//-2(špmif_sys_ckpmif_tmr_ckspmimst_clk_muxv-2†-t ·íñ �disabledtimer@10017000,mediatek,mt8186-timermediatek,mt6765-timer p·Ï“=mailbox@1022c000mediatek,mt8186-gce "À@“/šgce·ª¤Æxscp@10500000mediatek,mt8186-scp  P\�€ @sramcfg·Í°default¾>Èmediatek/mt8186/scp.imgÖ?�okayÆ�cros-ec-rpmsggoogle,cros-ec-rpmsgäcros-ec-rpmsgadsp@10680000mediatek,mt8186-dsp@ h €h°hð@cfgsramsecbus“-/->šaudiodspadsp_busv-/-> †)-Eørxtx@A B�okayÖCDƳmailbox@10686100mediatek,mt8186-adsp-mbox¤ ha·iÆ@mailbox@10687100mediatek,mt8186-adsp-mbox¤ hq·jÆAspi@11000000mediatek,mt8186-nor  “-3/O/c/dšspisfaxiaxi_sv-3†-P·%�okay°default¾E+flash@0jedec,spi-nor SÀadc@11001000.mediatek,mt8186-auxadcmediatek,mt8173-auxadc *“/"šmainserial@11002000*mediatek,mt8186-uartmediatek,mt6577-uart  ·p “)/ šbaudbus�okayserial@11003000*mediatek,mt8186-uartmediatek,mt6577-uart 0·q “)/ šbaudbus �disabledi2c@11007000mediatek,mt8186-i2c  p ·i“F/' šmaindma~+�okay°default¾G€edp-bridge@8parade,ps8640 °default¾H <,` L,bXIeJports+port@0 endpointrKÆport@1 endpointrLÆOaux-buspanel edp-panel‚M�NportendpointrOÆLi2c@11008000mediatek,mt8186-i2c  € ·j“F/' šmaindma~+ �disabled°default¾P€™'touchscreen@10 hid-over-i2c  _, °default¾Q³ ÊtR �disabledi2c@11009000mediatek,mt8186-i2c  � €·k“F/' šmaindma~+�okay°default¾ST€™'trackpad@15elan,ekth3000  _, ÙRäi2c@1100f000mediatek,mt8186-i2c  ð €·l“F/' šmaindma~+�okay°default¾U† dp-bridge@5c ite,it6505 \ _,°default¾VòWX L,±ƶports+port@0 endpointðÑ€rYÆ}port@1 i2c@11011000mediatek,mt8186-i2c   €€·m“F/' šmaindma~+�okay°default¾Z€proximity@28semtech,sx9324 (* _,°default¾[t\-\i2c@11016000mediatek,mt8186-i2c  ` ·b“F/' šmaindma~+�okay°default¾]codec@1arealtek,rt5682s  _,ò9\E\R\a^oƵi2c@1100d000mediatek,mt8186-i2c  Ð ·c“F/' šmaindma~+ �disabledi2c@11004000mediatek,mt8186-i2c  @ €·n“F/' šmaindma~+ �disabledi2c@11005000mediatek,mt8186-i2c  P €€·o“F/' šmaindma~+ �disabledspi@1100a000(mediatek,mt8186-spimediatek,mt6765-spi+  ·Š“-K- /šparent-clksel-clkspi-clk �disabledthermal-sensor@1100b000mediatek,mt8186-lvts °·c“/ ~/…_`$‘lvts-calib-data-1lvts-calib-data-2¢Æ“svs@1100bc00mediatek,mt8186-svs ¼·Ž“/ šmain…a_(‘svs-calibration-datat-calibration-data~/¸svs_rstpwm@1100e0002mediatek,mt8186-disp-pwmmediatek,mt8183-disp-pwm à·�Ä“-/4šmainmm�okay°default¾bÆ›spi@11010000(mediatek,mt8186-spimediatek,mt6765-spi+ ·‹“-K- /8šparent-clksel-clkspi-clk�okay°default¾cÏec@0google,cros-ec-spi  _, °default¾dB@i2c-tunnelgoogle,cros-ec-i2c-tunnelã+sbs-battery@bsbs,sbs-battery õ typecgoogle,cros-ec-typec+connector@0usb-c-connector  left $dual /host 9sourceconnector@1usb-c-connector  right $dual /host 9sourcekeyboard-controllergoogle,cros-ec-keyb H X  kD …ž­txcàá q rs}0Y1 d"#(  \V |})  Ž + ^a !%$' & + ,./-32*5 4 9    8 l j6  g i( ’  spi@11012000(mediatek,mt8186-spimediatek,mt6765-spi+  ·‘“-K- /;šparent-clksel-clkspi-clk�okay°default¾e §,-Ïtpm@0 google,cr50  _,°default¾fB@spi@11013000(mediatek,mt8186-spimediatek,mt6765-spi+ 0·’“-K- /<šparent-clksel-clkspi-clk �disabledspi@11014000(mediatek,mt8186-spimediatek,mt6765-spi+ @·t“-K- /Jšparent-clksel-clkspi-clk �disabledspi@11015000(mediatek,mt8186-spimediatek,mt6765-spi+ P·u“-K- /Kšparent-clksel-clkspi-clk �disabledclock-controller@11017000mediatek,mt8186-imp_iic_wrap pqÆFserial@11018000*mediatek,mt8186-uartmediatek,mt6577-uart €·ö “)/ šbaudbus �disabledi2c@11019000mediatek,mt8186-i2c  � €·d“F /' šmaindma~+ �disabledaudio-controller@11210000mediatek,mt8186-sound ! Ä“/,/6---F- - --e--h-?-@-A-B-C-ƒ-„-…-†-‡-,)}šaud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_audio_inttop_mainpll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s4_m_seltop_tdm_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div4top_apll12_div_tdmtop_mux_audio_htop_clk26m_clk·© °/ Ä-~g ¸audiosys�okayÆ´usb@11201000#mediatek,mt8186-mtu3mediatek,mtu3   -ÿ > @macippc(“-/=/3//>$šsys_ckref_ckmcu_ckdma_ckxhci_ck·/ Öh B+Æä Ûi �okayusb@11200000'mediatek,mt8186-xhcimediatek,mtk-xhci  @mac(“-/=/3//>$šsys_ckref_ckmcu_ckdma_ckxhci_ck·&�okay òRmmc@11230000(mediatek,mt8186-mmcmediatek,mt8183-mmc  #Í “- //U/šsourcehclksource_cgcrypto·dv- †�okay°defaultstate_uhs¾j þk  ë   2 A P ] c k | ‹ ¢l ®\mmc@11240000(mediatek,mt8186-mmcmediatek,mt8183-mmc  $É“-//Všsourcehclksource_cgv-†-o�okay°defaultstate_uhsstate_eint¾m þn »o Åmsdcsdio_wakeup _e,W+  ëÂ Õ æ ô ä  $ ]  ¢R ®\ +pbluetooth@2mediatek,mt7921s-bluetooth °default¾q L,›usb@11281000#mediatek,mt8186-mtu3mediatek,mtu3  (-ÿ(> @macippc$“/B/?/7)/@$šsys_ckref_ckmcu_ckdma_ckxhci_ck·K Örs B+Æä Ûi$�okayusb@11280000'mediatek,mt8186-xhcimediatek,mtk-xhci (@mac$“/B/?/7)/@$šsys_ckref_ckmcu_ckdma_ckxhci_ck·D�okay òtt-phy@11c80000.mediatek,mt8186-tphymediatek,generic-tphy-v2+ÆÈ�okayusb-phy@0 “)šref 6Ærusb-phy@700  “)šref 6Æst-phy@11ca0000.mediatek,mt8186-tphymediatek,generic-tphy-v2+ÆÊ�okayusb-phy@0 “)šref 6 AÆhefuse@11cb0000%mediatek,mt8186-efusemediatek,efuse Ë+lvts1-calib@1cc ÌÆ_lvts2-calib@2f8 øÆ`calib@550 PPÆagpu-speedbin@59c œ QÆvsocinfo-data1@7a0  dsi-phy@11cc0000mediatek,mt8183-mipi-tx Ì“)q 6 “mipi_tx0_pll�okayÆ~clock-controller@13000000mediatek,mt8186-mfgsys qÆugpu@13040000&mediatek,mt8186-maliarm,mali-bifrost @“u0· Åjobmmugpu BB Vcore0core1Ô…v ‘speed-bin¦w.O�okay i0Ƙsyscon@14000000mediatek,mt8186-mmsyssyscon q3xx uxÆ1mutex@14001000mediatek,mt8186-disp-mutex “1·' ux �²³ Bsmi@14002000mediatek,mt8186-smi-common   “1111šapbsmigals0gals1 BÆysmi@14003000mediatek,mt8186-smi-larb 0“11šapbsmi ¡ ²y BÆ€smi@14004000mediatek,mt8186-smi-larb @“11šapbsmi ¡ ²y BÆ�ovl@140050002mediatek,mt8186-disp-ovlmediatek,mt8192-disp-ovl P“1·) ¿z uxP Bovl@140060008mediatek,mt8186-disp-ovl-2lmediatek,mt8192-disp-ovl-2l `“1·* ¿z! ux` Brdma@140070004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdma p“1·+ ¿z" uxp Bcolor@140090006mediatek,mt8186-disp-colormediatek,mt8173-disp-color �“1 ·- ux€ Bdpi@1400a000mediatek,mt8186-dpi  “-;1 špixelenginepllv-;†-j·5 B �disabled°defaultsleep¾{ þ|portendpointr}ÆYccorr@1400b0006mediatek,mt8186-disp-ccorrmediatek,mt8192-disp-ccorr °“1·. ux° Baal@1400c0002mediatek,mt8186-disp-aalmediatek,mt8183-disp-aal À“1·0 uxÀ Bgamma@1400d0006mediatek,mt8186-disp-gammamediatek,mt8183-disp-gamma Г1 ·1 uxÐ Bpostmask@1400e000<mediatek,mt8186-disp-postmaskmediatek,mt8192-disp-postmask à“1 ·2 uxà Bdither@1400f0008mediatek,mt8186-disp-dithermediatek,mt8183-disp-dither ð“1·3 uxð Bdsi@14013000mediatek,mt8186-dsi 0“11~šenginedigitalhs·7 B~1 Ö~ Ædphy�okayportendpointrÆKiommu@14016000mediatek,mt8186-iommu-mm `“1šbclk·98 Ѐ�‚ƒ„…†‡ˆ‰Š‹Œ� B ߯zrdma@1401f0004mediatek,mt8186-disp-rdmamediatek,mt8183-disp-rdma ð“1·4 ¿z  uxð Bclock-controller@14020000mediatek,mt8186-wpesys qÆ7smi@14023000mediatek,mt8186-smi-larb 0“77šapbsmi ¡ ²y BÆ…clock-controller@15020000mediatek,mt8186-imgsys1 qÆ4smi@1502e000mediatek,mt8186-smi-larb à“44šapbsmi ¡  ²y BƆclock-controller@15820000mediatek,mt8186-imgsys2 ‚qÆŽsmi@1582e000mediatek,mt8186-smi-larb ‚à“4Žšapbsmi ¡  ²y BƇvideo-decoder@16000000mediatek,mt8186-vcodec-dec Æ+Â@ÿð ¿z€ ì�video-codec@16025000mediatek,mtk-vcodec-core P·W` ¿z€z�z‚zƒz„z…z†z‡zˆz‰zŠz‹ “-)22-U%švdec-selvdec-soc-vdecvdecvdec-topv-)†-U Bsmi@1602e000mediatek,mt8186-smi-larb à“22šapbsmi ¡ ²y Bƃclock-controller@1602f000mediatek,mt8186-vdecsys ðqÆ2clock-controller@17000000mediatek,mt8186-vencsys qÆ6smi@17010000mediatek,mt8186-smi-larb “66šapbsmi ¡ ²y B Æ„video-encoder@170200006mediatek,mt8186-vcodec-encmediatek,mt8183-vcodec-enc  ·óH ¿zàzázâzãzäzåzæzçzè“6 švenc_selv-$†-U B  ì�jpeg-encoder@17030000+mediatek,mt8186-jpgencmediatek,mtk-jpgenc ·õ“6šjpgenc ¿zézêzëzì B clock-controller@1a000000mediatek,mt8186-camsys qÆ3smi@1a001000mediatek,mt8186-smi-larb “33šapbsmi ¡  ²y B ƈsmi@1a002000mediatek,mt8186-smi-larb  “33šapbsmi ¡ ²y B Ɖsmi@1a00f000mediatek,mt8186-smi-larb ð“3�šapbsmi ¡ ²y B ÆŠsmi@1a010000mediatek,mt8186-smi-larb “3‘šapbsmi ¡ ²y B Æ‹clock-controller@1a04f000mediatek,mt8186-camsys_rawa ðqÆ�clock-controller@1a06f000mediatek,mt8186-camsys_rawb ðqÆ‘clock-controller@1b000000mediatek,mt8186-mdpsys qÆ’smi@1b002000mediatek,mt8186-smi-larb  “’’šapbsmi ¡ ²y BÆ‚clock-controller@1c000000mediatek,mt8186-ipesys qÆ5smi@1c00f000mediatek,mt8186-smi-larb ð“55šapbsmi ¡ ²y B Æ�smi@1c10f000mediatek,mt8186-smi-larb ð“55šapbsmi ¡ ²y B ÆŒthermal-zonescpu-little0-thermal ùè – “tripstrip-alert0 -L 9ÐEpassiveÆ”trip-alert1 -s 9ÐEhottrip-crit -†  9 Ecriticalcooling-mapsmap0 D”H Iÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little1-thermal ùè – “tripstrip-alert0 -L 9ÐEpassiveÆ•trip-alert1 -s 9ÐEhottrip-crit -†  9 Ecriticalcooling-mapsmap0 D•H Iÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-little2-thermal ùè – “tripstrip-alert0 -L 9ÐEpassiveÆ–trip-alert1 -s 9ÐEhottrip-crit -†  9 Ecriticalcooling-mapsmap0 D–H Iÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcam-thermal ùè ú “tripstrip-alert0 -L 9ÐEpassivetrip-alert1 -s 9ÐEhottrip-crit -†  9 Ecriticalnna-thermal ùè ú “tripstrip-alert0 -L 9ÐEpassivetrip-alert1 -s 9ÐEhottrip-crit -†  9 Ecriticaladsp-thermal ùè ú “tripstrip-alert0 -L 9ÐEpassivetrip-alert1 -s 9ÐEhottrip-crit -†  9 Ecriticalgpu-thermal ùè ú “tripstrip-alert0 -L 9ÐEpassiveÆ—trip-alert1 -s 9ÐEhottrip-crit -†  9 Ecriticalcooling-mapsmap0 D— I˜ÿÿÿÿÿÿÿÿcpu-big0-thermal ùè d “tripstrip-alert0 -L 9ÐEpassiveÆ™trip-alert1 -s 9ÐEhottrip-crit -†  9 Ecriticalcooling-mapsmap0 D™ Iÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿcpu-big1-thermal ùè d “tripstrip-alert0 -L 9ÐEpassiveÆštrip-alert1 -s 9ÐEhottrip-crit -†  9 Ecriticalcooling-mapsmap0 Dš Iÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿchosen Xserial0:115200n8memory@40000000memory @backlight-lcd0pwm-backlight d›¡ ‚œ i,˜ vÿ ˆÿ Ÿ@ÆNbt-sco linux,bt-scoòdmic-codec dmic-codecò ¸ Å2gpio-keys gpio-keys°default¾� �disabledpen-insert-switch Pen Insert F, Õä é ôregulator-pp1800-dpbrdg-dxregulator-fixed°default¾ž F,'¦pp1800_dpbrdg_dx  \ÆXregulator-pp3300-disp-xregulator-fixed°default¾Ÿ F,™¦pp3300_disp_x  # ^ÆMregulator-pp3300-ldo-z5regulator-fixed¦pp3300_ldo_z5. #µ2Z Í2Z  œregulator-pp3300-s3regulator-fixed ¦pp3300_s3. # ^ÆRregulator-pp3300-z2regulator-fixed ¦pp3300_z2. #µ2Z Í2Z  œÆ^regulator-pp4200-z2regulator-fixed ¦pp4200_z2. #µ@@Í@@ œÆ9regulator-pp5000-z2regulator-fixed ¦pp5000_z2. #µLK@ÍLK@ œƹregulator-ppvar-sysregulator-fixed ¦ppvar_sys. #Æœreserved-memory+Æmemory@61000000shared-dma-pool a 5ÆCmemory@60000000shared-dma-pool ` 5ÆDmemory@50000000shared-dma-pool P  5Æ?sound,mediatek,mt8186-mt6366-rt1019-rt5682s-soundC°aud_clk_mosi_offaud_clk_mosi_onaud_clk_miso_offaud_clk_miso_onaud_dat_miso_offaud_dat_miso_onaud_dat_mosi_offaud_dat_mosi_onaud_gpio_i2s0_offaud_gpio_i2s0_onaud_gpio_i2s1_offaud_gpio_i2s1_onaud_gpio_i2s2_offaud_gpio_i2s2_onaud_gpio_i2s3_offaud_gpio_i2s3_onaud_gpio_pcm_offaud_gpio_pcm_onaud_gpio_dmic_sec¾  þ¡ »¢ <£ F¤ P¥ Z¦ d§ n¨ x© ‚ª �« ˜¬ £­ ®® ¹¯ İ ϱ Ú² å³ ó´IHeadphoneHPOLHeadphoneHPORIN1PHeadset MicSpeakersSpeakerHDMI1TXhs-playback-dai-linkI2S0i2s(cpucodec>µhs-capture-dai-linkI2S1i2s(cpucodec>µspk-share-dai-linkI2S2(cpuspk-hdmi-playback-dai-linkI2S3i2s(cpucodec>¶·speaker-codecrealtek,rt1019p°default¾¸ò H,–Æ·regulator-usb-p1-vbusregulator-fixed R,”¦vbus1µLK@ÍLK@  ¹Ætwifi-pwrseqmmc-pwrseq-simple°default¾º³2 L,6Æpwifi-wakeup gpio-keys°default¾»wowlan-event Wake on WiFi F, é�ä compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl-2l0rdma0rdma1i2c0i2c1i2c2i2c3i2c5mmc0mmc1serial0i2c4clocksclock-namesoperating-points-v2proc-supplyphandleopp-sharedopp-hzopp-microvoltrequired-oppscpudevice_typeregenable-methodclock-frequencydynamic-power-coefficientcapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-divclock-multclock-output-namesopp-supported-hwinterruptsdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxinput-enablebias-pull-downinput-schmitt-enablebias-disableoutput-lowdrive-strengthoutput-highbias-pull-up#power-domain-cellsdomain-supplymediatek,infracfgmediatek,disable-extrstmediatek,reset-by-toprguinterrupts-extendedAvdd-supplymediatek,dmic-modevsys-ldo1-supplyvsys-ldo2-supplyvsys-ldo3-supplyvsys-vcore-supplyvsys-vdram1-supplyvsys-vgpu-supplyvsys-vmodem-supplyvsys-vpa-supplyvsys-vproc11-supplyvsys-vproc12-supplyvsys-vs1-supplyvsys-vs2-supplyvs1-ldo1-supplyvs2-ldo1-supplyvs2-ldo2-supplyvs2-ldo3-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-allowed-modesregulator-always-onregulator-coupled-withregulator-coupled-max-spreadassigned-clocksassigned-clock-parentsstatus#mbox-cellspinctrl-namespinctrl-0firmware-namememory-regionmediatek,rpmsg-namembox-namesmboxespower-domainsspi-max-frequency#io-channel-cellspowerdown-gpiosreset-gpiosvdd12-supplyvdd33-supplyremote-endpointpower-supplybacklighti2c-scl-internal-delay-nspost-power-on-delay-mshid-descr-addrvcc-supplywakeup-source#sound-dai-cellsovdd-supplypwr18-supplylink-frequenciessvdd-supplyAVDD-supplyDBVDD-supplyLDO1-IN-supplyMICVDD-supplyrealtek,jd-srcresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsreset-names#pwm-cellsmediatek,pad-selectgoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countlabelpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapcs-gpiosmediatek,apmixedsysmediatek,topckgenphysmediatek,syscon-wakeupvbus-supplypinctrl-1bus-widthnon-removablecap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqeno-sdno-sdiocap-mmc-hw-reseths400-ds-delaymediatek,hs400-ds-dly3vmmc-supplyvqmmc-supplypinctrl-2interrupt-namescap-sd-highspeedsd-uhs-sdr104sd-uhs-sdr50keep-power-in-suspendcap-sdio-irqno-mmcmmc-pwrseq#phy-cellsmediatek,discthbitspower-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusphy-namesmediatek,larbs#iommu-cellsmediatek,scppolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathpwmsenable-gpiosbrightness-levelsnum-interpolated-stepsdefault-brightness-levelnum-channelswakeup-delay-mswakeup-event-actionlinux,codelinux,input-typeenable-active-highvin-supplyregulator-boot-onno-mappinctrl-3pinctrl-4pinctrl-5pinctrl-6pinctrl-7pinctrl-8pinctrl-9pinctrl-10pinctrl-11pinctrl-12pinctrl-13pinctrl-14pinctrl-15pinctrl-16pinctrl-17pinctrl-18mediatek,adspmediatek,platformaudio-routinglink-namedai-formatmediatek,clk-providersound-daisdb-gpiosgpio