Ð þíp@8id(Üi,sony,xperia-m5mediatek,mt6795 +7Sony Xperia M5=handsetaliasesJ/soc/ovl@1400c000O/soc/ovl@1400d000T/soc/rdma@1400e000Z/soc/rdma@1400f000`/soc/rdma@14010000f/soc/wdma@14011000l/soc/wdma@14012000r/soc/color@14013000y/soc/color@14014000€/soc/split@14018000‡/soc/split@14019000Ž/soc/dpi@1401d000“/soc/dsi@1401b000˜/soc/dsi@1401c000�/soc/mmc@11230000¢/soc/mmc@11240000§/soc/mmc@11250000¬/soc/serial@11002000´/soc/serial@11003000psci arm,psci-0.2¼smccpus+cpu@0Ãcpuarm,cortex-a53ÏpsciÝáòcpu@1Ãcpuarm,cortex-a53ÏpsciÝá €@*7€D@V€òcpu@2Ãcpuarm,cortex-a53ÏpsciÝá €@*7€D@V€òcpu@3Ãcpuarm,cortex-a53ÏpsciÝá €@*7€D@V€ò cpu@100Ãcpuarm,cortex-a53ÏpsciÝá €@*7€D@V€ò cpu@101Ãcpuarm,cortex-a53ÏpsciÝá €@*7€D@V€ò cpu@102Ãcpuarm,cortex-a53ÏpsciÝá €@*7€D@V€ò cpu@103Ãcpuarm,cortex-a53ÏpsciÝá €@*7€D@V€ò cpu-mapcluster0core0ccore1ccore2ccore3c cluster1core0c core1c core2c core3c l2-cache0cacheg @,sl2-cache1cacheg @,soscillator-26m fixed-clock�ŽŒº€žclk26moscillator-32k fixed-clock�Ž}žclk32kdummy13m fixed-clockŽÆ]@�pmuarm,cortex-a53-pmu0±   ¼ timerarm,armv8-timer 0± ÿÿ ÿ ÿsoc+ simple-busÏsyscon@10000000 mediatek,mt6795-topckgensysconÝ�syscon@10001000 mediatek,mt6795-infracfgsysconÝ�Ösyscon@10003000mediatek,mt6795-pericfgsysconÝ0�Ösyscon@10006000sysconsimple-mfdÝ`ãpower-controller!mediatek,mt6795-power-controller+ãpower-domain@1Ý÷Rþmmãpower-domain@2Ý÷RUþmmvencãpower-domain@3Ý÷Rþmmãpower-domain@0Ý÷Rþmmã power-domain@4Ý÷Reþmmmjcãpower-domain@5Ýãpower-domain@6Ý÷þmfg+ãpower-domain@7Ý+ãpower-domain@8Ýã pinctrl@10005000mediatek,mt6795-pinctrl ÝP° baseeint±™š&6BÄNclcm-pins6pins-rsttjemmc-sdr-pins'pins-cmd-dat$tš›œ�žŸ ¡¢{ˆepins-clkt£•fpins-rstt¥ˆfemmc-uhs-pins(pins-cmd-dat$tš›œ�žŸ ¡¢{¤ˆepins-clkt£¤•fpins-rstt¥¤ˆfpins-dst¤¤•fnfc-pins%pins-irqt•{pins-fw-vent^•touchscreen-pins#pins-irqtˆ{pins-rsttf³proximity-pins&pins-irqtˆ{accelerometer-pins!pins-irqt ˆ{i2c0-pinspins-bust-.{i2c1-pins pins-bust}~¿i2c2-pins"pins-bust+,¿i2c3-pins$pins-bustˆ‰¿i2c4-pinspins-bustde¿uart0-pinspins-rxtqˆ{pins-txtr³uart2-pinspins-rxtˆ{pins-txt watchdog@10007000mediatek,mt6795-wdtÝp ±€ÖÌtimer@10008000,mediatek,mt6795-timermediatek,mt6577-timerÝ€ ±˜÷pwrap@1000d000mediatek,mt6795-pwrapÝÐpwrap ±¡Øßpwrap ÷c þspiwrapmt6331mediatek,mt6331Nc ± mt6331regulatormediatek,mt6331-regulatorbuck-vdvfs11ëvdvfs11ú ®`Êö*0Ô?[sbuck-vdvfs12ëvdvfs12ú ®`Êö*0Ô?[sbuck-vdvfs13ëvdvfs13ú ®`Êö*0Ô?[sbuck-vdvfs14ëvdvfs14ú ®`Êö*0Ô?[sbuck-vcore2ëvcore2ú ®`Êö*0Ô?[sbuck-vio18ëvio18úw@w@*0Ô?[s*ldo-vtcxo1ëvtcxo1ú*¹€*¹€*s‡ldo-vtcxo2ëvtcxo2ú*¹€*¹€*s‡ldo-avdd32aud ëavdd32_audú*¹€0Ô*s‡ldo-vauxa32ëvauxa32ú*¹€0Ô*ldo-vcamaëvcamaúã`*¹€*ldo-vio28ëvio28ú*¹€*¹€*s‡ldo-vcamafëvcam_afúO€2Z *ldo-vmcëvmcúw@2Z *+ldo-vmchëvmchú-ÆÀ2Z *,ldo-vemc33ëvemc33ú2Z 2Z *s)ldo-vgp1ëvgp1úO€2Z *sldo-vsim1ëvsim1úð /M`*sldo-vsim2ëvsim2úð /M`*ldo-vmipiëvmipiúO€2Z *sldo-vibrëvibrúO€2Z *ldo-vgp4ëvgp4új!‘À*sldo-vcamdëvcamdú » ã`*sldo-vusb10ëvusbúB@Ö *s‡ldo-vcamioëvcam_ioúO€w@*ldo-vsramëvsramúss*s‡ldo-vgp2ëvgp2úÈàã`*s‡ldo-vgp3ëvgp3úw@w@*s3ldo-vrtcëvrtcú*¹€*¹€*sldo-vdig18 ëdvdd18_digúw@w@*smt6331rtcmediatek,mt6331-rtcmt6331keysmediatek,mt6331-keyspower™t¨home™fmt6332-ledmediatek,mt6332-led+led@0ݶbacklight-pmic>intpol-controller@10200620.mediatek,mt6795-sysirqmediatek,mt6577-sysirqNc Ý  timer@10200670mediatek,mt6795-systimerÝ p ±@÷þclk13miommu@10205000mediatek,mt6795-m4uÝ P÷þbclk ±’¼ËÙ/syscon@10209000"mediatek,mt6795-apmixedsyssysconÝ ��clock-controller@10209f00mediatek,mt6795-fhctlÝ Ÿæokay÷ ímailbox@10212000(mediatek,mt6795-gcemediatek,mt8173-gceÝ!  ±�÷þgce -dsi-phy@10215000mediatek,mt8173-mipi-txÝ!P÷ žmipi_tx0_pll� ædisabled0dsi-phy@10216000mediatek,mt8173-mipi-txÝ!`÷ žmipi_tx1_pll� ædisabled9interrupt-controller@10221000 arm,gic-400c N@Ý"" "@ "`  ± cci@10390000 arm,cci-400+Ý9Ï9slave-if@1000arm,cci-400-ctrl-if !ace-liteÝslave-if@4000arm,cci-400-ctrl-if!aceÝ@slave-if@5000arm,cci-400-ctrl-if!aceÝPpmu@9000arm,cci-400-pmu,r1Ý�P<±:;<=>serial@11002000*mediatek,mt6795-uartmediatek,mt6577-uartÝ  ±[÷ þbaudbus05txrxæokay?defaultMserial@11003000*mediatek,mt6795-uartmediatek,mt6577-uartÝ0 ±\÷ þbaudbus05txrx ædisableddma-controller@110003802mediatek,mt6795-uart-dmamediatek,mt6577-uart-dma€Ý€``€``€``€```±ghijklmnW÷ þapdmadxserial@11004000*mediatek,mt6795-uartmediatek,mt6577-uartÝ@ ±]÷  þbaudbus05txrxæokay?defaultMserial@11005000*mediatek,mt6795-uartmediatek,mt6577-uartÝP ±^÷! þbaudbus05txrx ædisabledpwm@11006000mediatek,mt6795-pwmÝ`ƒ ±MH÷S ,þtopmainpwm1pwm2pwm3pwm4pwm5pwm6pwm7 ædisabledi2c@11007000(mediatek,mt6795-i2cmediatek,mt8173-i2c Ýpp€ ±TŽ÷  þmaindma+æokay?defaultMi2c@11008000(mediatek,mt6795-i2cmediatek,mt8173-i2c Ý€p€€ ±UŽ÷  þmaindma+æokay?defaultM accelerometer@10 bosch,bma255Ý?defaultM!magnetometer@12 bosch,bmm150Ýi2c@11009000(mediatek,mt6795-i2cmediatek,mt8173-i2c Ý�p€ ±VŽ÷  þmaindma+æokay?defaultM"touchscreen@20syna,rmi4-i2cÝ + ˜?defaultM#¬ ÂZrmi4-f01@1ÝÖrmi4-f12@12Ýèi2c@11010000(mediatek,mt6795-i2cmediatek,mt8173-i2c Ýp€€ ±WŽ÷  þmaindma+æokay?defaultM$nfc@28nxp,pn544-i2cÝ( ˜?defaultM% ù• ^proximity@48sensortek,stk3310ÝH ˜?defaultM&i2c@11011000(mediatek,mt6795-i2cmediatek,mt8173-i2c Ýp€ ±XŽ÷  þmaindma+ ædisabledmmc@11230000mediatek,mt6795-mmcÝ# ±O÷ \]þsourcehclksource_cgæokay'Dax?defaultstate_uhsM'†(�)œ*mmc@11240000mediatek,mt6795-mmcÝ$ ±P÷O þsourcehclkæokay�+œ,mmc@11250000mediatek,mt6795-mmcÝ% ±Q÷O þsourcehclkæokay�+œ,mmc@11260000mediatek,mt6795-mmcÝ& ±R÷O þsourcehclk ædisabledsyscon@14000000mediatek,mt6795-mmsyssysconÝË©R¹ׄ�ÖÎ--Õ-.ovl@1400c0002mediatek,mt6795-disp-ovlmediatek,mt8173-disp-ovlÝÀ ±¼Ë÷.í/Õ-Àovl@1400d0002mediatek,mt6795-disp-ovlmediatek,mt8173-disp-ovlÝÐ ±½Ë÷.í/Õ-Ðrdma@1400e0004mediatek,mt6795-disp-rdmamediatek,mt8173-disp-rdmaÝà ±¾Ë÷.í/Õ-àrdma@1400f0004mediatek,mt6795-disp-rdmamediatek,mt8173-disp-rdmaÝ𠱿Ë÷.í/Õ-ðrdma@140100004mediatek,mt6795-disp-rdmamediatek,mt8173-disp-rdmaÝ ±ÀË÷.í/Õ-wdma@140110004mediatek,mt6795-disp-wdmamediatek,mt8173-disp-wdmaÝ ±ÁË÷.í/Õ-wdma@140120004mediatek,mt6795-disp-wdmamediatek,mt8173-disp-wdmaÝ  ±ÂË÷.í/Õ- color@140130006mediatek,mt6795-disp-colormediatek,mt8173-disp-colorÝ0 ±ÃË÷.Õ-0color@140140006mediatek,mt6795-disp-colormediatek,mt8173-disp-colorÝ@ ±ÄË÷.Õ-@aal@140150002mediatek,mt6795-disp-aalmediatek,mt8173-disp-aalÝP ±ÅË÷.Õ-Pgamma@140160006mediatek,mt6795-disp-gammamediatek,mt8173-disp-gammaÝ` ±ÆË÷.Õ-`merge@140170006mediatek,mt6795-disp-mergemediatek,mt8173-disp-mergeÝpË÷.split@140180006mediatek,mt6795-disp-splitmediatek,mt8173-disp-splitÝ€Ë÷.split@140190006mediatek,mt6795-disp-splitmediatek,mt8173-disp-splitÝ�Ë÷.ufoe@1401a0004mediatek,mt6795-disp-ufoemediatek,mt8173-disp-ufoeÝ  ±ÇË÷.Õ- dsi@1401b000(mediatek,mt6795-dsimediatek,mt8173-dsiݰ ±ÈË÷.$.%0þenginedigitalhsô0ùdphyæokay+panel@0sharp,ls060t1sx01Ý123'4 3j?5M6?defaultportendpointI78portendpointI87dsi@1401c000(mediatek,mt6795-dsimediatek,mt8173-dsiÝÀ ±ÉË÷.&.'9þenginedigitalhsô9ùdphy ædisableddpi@1401d000(mediatek,mt6795-dpimediatek,mt8183-dpiÝÐ ±ÊË÷.(.)þpixelenginepll ædisabledpwm@1401e0002mediatek,mt6795-disp-pwmmediatek,mt8173-disp-pwmÝàƒ÷.!. þmainmmæokay?pwm@1401f0002mediatek,mt6795-disp-pwmmediatek,mt8173-disp-pwmÝðƒ÷.#."þmainmm ædisabledmutex@14020000mediatek,mt8173-disp-mutexÝ ±±Ë÷.Y45Õ-larb@14021000mediatek,mt6795-smi-larbÝ÷..þapbsmim:zËsmi@14022000mediatek,mt6795-smi-commonÝ Ë÷.þapbsmi:od@140230000mediatek,mt6795-disp-odmediatek,mt8173-disp-odÝ0÷.Õ-0larb@15001000mediatek,mt6795-smi-larbÝ÷.þapbsmim:zËclock-controller@16000000mediatek,mt6795-vdecsysÝ�;larb@16010000mediatek,mt6795-smi-larbÝm:z÷;;þapbsmiËclock-controller@18000000mediatek,mt6795-vencsysÝ�<larb@18001000mediatek,mt6795-smi-larbÝ÷<<þapbsmim:zËbacklightled-backlight‹=>�,5led-controller-display pwm-ledsled-0¶backlight-pwm ©?¡ ®=memory@40000000ÃmemoryÝ@€reserved-memory+Ïsecmon@43000000ÝC½preloader-region@44800000ÝD€½bootloader-region@46000000ÝF@½regulator-disp-avddregulator-fixed ëdisp_avddúLK@LK@ ÄŠÉ1regulator-disp-aveeregulator-fixed ëdisp_aveeúLK@LK@ Ä‹É2regulator-disp-vddhregulator-fixed ëdisp_vddhúw@w@s‡4 compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1mmc0mmc1mmc2serial0serial1methoddevice_typeenable-methodregcci-control-portnext-level-cachephandlei-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setscpucache-levelcache-unified#clock-cellsclock-frequencyclock-output-namesinterruptsinterrupt-affinityranges#reset-cells#power-domain-cellsclocksclock-namesmediatek,infracfgreg-namesgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspinmuxinput-enablebias-pull-upbias-pull-downdrive-strengthoutput-highbias-disabletimeout-secresetsreset-namesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-allowed-modesregulator-always-onregulator-boot-onlinux,keycodeswakeup-sourcelabelmediatek,larbspower-domains#iommu-cellsstatusmediatek,hopping-ssc-percent#mbox-cells#phy-cellsinterface-typedmasdma-namespinctrl-namespinctrl-0dma-requestsmediatek,dma-33bits#dma-cells#pwm-cellsclock-divinterrupts-extendedsyna,startup-delay-mssyna,reset-delay-mssyna,nosleep-modesyna,sensor-typeenable-gpiosfirmware-gpiosmediatek,latch-ckmediatek,hs200-cmd-int-delaymediatek,hs400-cmd-int-delaymediatek,hs400-ds-dly3non-removablepinctrl-1vmmc-supplyvqmmc-supplyassigned-clocksassigned-clock-ratesmboxesmediatek,gce-client-regiommusphysphy-namesavdd-supplyavee-supplyvddi-supplyvddh-supplyreset-gpiosbacklightremote-endpointmediatek,gce-eventsmediatek,smimediatek,larb-idledsdefault-brightness-levelpwmsmax-brightnessno-mapgpioenable-active-high