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ÿmainmm ¾disabledpwm@1401f0002mediatek,mt6795-disp-pwmmediatek,mt8173-disp-pwmÞð&ø#"ÿmainmm ¾disabledmutex@14020000mediatek,mt8173-disp-mutexÞ ²±£ø•45glarb@14021000mediatek,mt6795-smi-larbÞøÿapbsmi©"¶£smi@14022000mediatek,mt6795-smi-commonÞ £øÿapbsmi"od@140230000mediatek,mt6795-disp-odmediatek,mt8173-disp-odÞ0øg0larb@15001000mediatek,mt6795-smi-larbÞøÿapbsmi©"¶£clock-controller@16000000mediatek,mt6795-vdecsysÞ‚#larb@16010000mediatek,mt6795-smi-larbÞ©"¶ø##ÿapbsmi£clock-controller@18000000mediatek,mt6795-vencsysÞ‚$larb@18001000mediatek,mt6795-smi-larbÞø$$ÿapbsmi©"¶£memory@40000000ÄmemoryÞ@€chosenÇserial0:921600n8 compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeovl0ovl1rdma0rdma1rdma2wdma0wdma1color0color1split0split1dpi0dsi0dsi1serial0serial1serial2serial3methoddevice_typeenable-methodregcci-control-portnext-level-cachephandlei-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setscpucache-levelcache-unified#clock-cellsclock-frequencyclock-output-namesinterruptsinterrupt-affinityranges#reset-cells#power-domain-cellsclocksclock-namesmediatek,infracfgreg-namesgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellstimeout-secresetsreset-namesmediatek,larbspower-domains#iommu-cellsstatus#mbox-cells#phy-cellsinterface-typedmasdma-namesdma-requestsmediatek,dma-33bits#dma-cells#pwm-cellsclock-divassigned-clocksassigned-clock-ratesmboxesmediatek,gce-client-regiommusphysphy-namesmediatek,gce-eventsmediatek,smimediatek,larb-idstdout-path