Ð þí\8UÜ(+U¤$mediatek,mt2712-evbmediatek,mt2712 +!7MediaTek MT2712 evaluation board =embeddedopp-table-0operating-points-v2JUopp00]#¤Á€dB@opp01])׫€dB@opp02]/D8@dB@opp-table-1operating-points-v2JU opp00]#¤Á€dB@opp01])׫€dB@opp02]/D8@dB@opp03]5w"@dB@opp04];ª @dB@cpus+cpu-mapcluster0core0rcore1rcluster1core0rcpu@0vcpuarm,cortex-a35‚†%�cpuintermediate™¥¹ Ucpu@1vcpuarm,cortex-a35‚Épsci†%�cpuintermediate™¥¹ Ucpu@200vcpuarm,cortex-a72‚Épsci†'�cpuintermediate™ ¥ ¹ Uidle-states×pscicpu-sleep-0arm,idle-stateäõdPÐ'U cluster-sleep-0arm,idle-stateäõ^P ¸'U psci arm,psci-0.2Ðsmcdummy26m fixed-clock>Œº€NUdummyclk fixed-clock>Œº€NUoscillator-26m fixed-clockN>Œº€[clk26mU*oscillator-32k fixed-clockN>€[clk32koscillator-50m fixed-clockN>úð€[clkfpcoscillator-aud0 fixed-clockN>c. [clkaud_ext_i_0oscillator-aud1 fixed-clockN> ¸[clkaud_ext_i_1oscillator-aud2 fixed-clockN> Ä@[clkaud_ext_i_2oscillator-i2s0 fixed-clockN>ÉÀ[clki2si0_mck_ioscillator-i2s1 fixed-clockN>ÉÀ[clki2si1_mck_ioscillator-i2s2 fixed-clockN>ÉÀ[clki2si2_mck_ioscillator-mclk fixed-clockN>ÉÀ[clktdmin_mclk_itimerarm,armv8-timer 0n   syscon@10000000 mediatek,mt2712-topckgensyscon‚NUclock-controller@10001000 mediatek,mt2712-infracfgsyscon‚NyUsyscon@10003000mediatek,mt2712-pericfgsyscon‚0NUsyscon@10005000%mediatek,mt2712-pctl-a-syscfgsyscon‚PUpinctrl@1000b000mediatek,mt2712-pinctrl‚°†›«·Ì n™U"eth-default-pinsU#tx_pinsÝGHIJKLärx_pinsÝNOPQRTómdio_pinsÝUVäóeth-sleep-pinsU$tx_pinsÝGHIJKLrx_pinsÝNOPQRTmdio_pinsÝUVusb0-iddig-pinsU)pins_iddigÝ usb1-iddig-pinsU1pins_iddigÝpower-controller@10006000mediatek,mt2712-scpsyssyscon(‚`0†eihœ�g�mmmfgvencjpgdecaudiovdec<Userial@1000f000*mediatek,mt2712-uartmediatek,mt6577-uart‚ð n† �baudbusE  Jtxrx Tdisabledrtc@10011000mediatek,mt2712-rtc‚ nïspi@10013000mediatek,mt2712-spi-slave‚0 n†�spi[�k Tdisablediommu@10205000mediatek,mt2712-m4u‚ P n“†�bclk‚”£syscon@10209000"mediatek,mt2712-apmixedsyssyscon‚ �Niommu@1020a000mediatek,mt2712-m4u‚   n‘†�bclk‚ ”£syscon@10220000mediatek,mt2712-mcucfgsyscon‚"NUinterrupt-controller@10220a80.mediatek,mt2712-sysirqmediatek,mt6577-sysirq·Ì ‚" €@Uinterrupt-controller@10510000 arm,gic-400Ì ·@‚QRTV n U dma-controller@110004002mediatek,mt2712-uart-dmamediatek,mt6577-uart-dmaÀ‚€€€€€€€€€€€€€€€ € €€�nghijklmnopqr° † �apdma½Uadc@11001000mediatek,mt2712-auxadc‚†�mainÈTokayserial@11002000*mediatek,mt2712-uartmediatek,mt6577-uart‚  n[† �baudbusEJtxrxTokayserial@11003000*mediatek,mt2712-uartmediatek,mt6577-uart‚0 n\† �baudbusEJtxrx Tdisabledserial@11004000*mediatek,mt2712-uartmediatek,mt6577-uart‚@ n]† �baudbusEJtxrx Tdisabledserial@11005000*mediatek,mt2712-uartmediatek,mt6577-uart‚P n^† �baudbusEJtxrx Tdisabledpwm@11006000mediatek,mt2712-pwm‚`Ú nMP†f  1�topmainpwm1pwm2pwm3pwm4pwm5pwm6pwm7pwm8 Tdisabledi2c@11007000mediatek,mt2712-i2c ‚p�€€ nTå†  �maindma+ Tdisabledi2c@11008000mediatek,mt2712-i2c ‚€�€ nUå†  �maindma+ Tdisabledi2c@11009000mediatek,mt2712-i2c ‚��€€ nVå†  �maindma+ Tdisabledspi@1100a000mediatek,mt2712-spi+‚  nv†l�parent-clksel-clkspi-clk Tdisablednand-controller@1100e000mediatek,mt2712-nfc‚à n`†½�nfi_clkpad_clkï+ Tdisabledecc@1100f000mediatek,mt2712-ecc‚ð n_†¿ �nfiecc_clk TdisabledUi2c@11010000mediatek,mt2712-i2c ‚�€ nWå†  �maindma+ Tdisabledi2c@11011000mediatek,mt2712-i2c ‚�€€ nXå†  �maindma+ Tdisabledi2c@11013000mediatek,mt2712-i2c ‚0�€ nZå†  �maindma+ Tdisabledspi@11015000mediatek,mt2712-spi+‚P n†l�parent-clksel-clkspi-clk Tdisabledspi@11016000mediatek,mt2712-spi+‚` n†l�parent-clksel-clkspi-clk Tdisabledspi@10012000mediatek,mt2712-spi+‚  n†l�parent-clksel-clkspi-clk Tdisabledspi@11018000mediatek,mt2712-spi+‚€ n†l�parent-clksel-clkspi-clk Tdisabledserial@11019000*mediatek,mt2712-uartmediatek,mt6577-uart‚� n~† �baudbusE Jtxrx Tdisabledstmmac-axi-configú Urx-queues-config$:Uqueue0K^vtx-queues-config„šU queue0¬Kvqueue1¬Kvqueue2¬Kvethernet@1101c000&mediatek,mt2712-gmacsnps,dwmac-4.20a‚À ní¸macirqÈU{µ}÷'�axiapbmac_mainptp_refrmii_internal(†"%š›ž[š›žk=º>Ôâó )4?Tokay Lrgmii-rxidU!`ú u"W …''šdefaultsleep¨#²$mdiosnps,dwmac-mdio+ethernet-phy@5ethernet-phy-id0243.0d90‚U!mmc@11230000mediatek,mt2712-mmc‚# nO † *&,�sourcehclksource_cgbus_clk Tdisabledmmc@11240000mediatek,mt2712-mmc‚$ nP† c'�sourcehclksource_cg Tdisabledmmc@11250000mediatek,mt2712-mmc‚% nQ†c(�sourcehclksource_cg Tdisabledusb@11271000#mediatek,mt2712-mtu3mediatek,mtu3 ‚'0( ¼macippc nzÆ%&Ô†n�sys_ck Ë+âTokayé'õ(üotgšdefault¨)usb@11270000'mediatek,mt2712-xhcimediatek,mtk-xhci‚'¼mac n{Ô †n*�sys_ckref_ckTokayé+t-phy@11290000.mediatek,mt2712-tphymediatek,generic-tphy-v2+â)�Tokayusb-phy@0‚†*�ref'TokayU%usb-phy@8000‚€†*�ref'TokayU&usb-phy@8700‚‡ †*�ref'TokayU3usb@112c1000#mediatek,mt2712-mtu3mediatek,mtu3 ‚,0- ¼macippc nøÆ,-.Ô†n�sys_ck Ë+âTokayé/õ0üotg2šdefault¨1usb@112c0000'mediatek,mt2712-xhcimediatek,mtk-xhci‚,¼mac nùÔ †n*�sys_ckref_ckTokayt-phy@112e0000.mediatek,mt2712-tphymediatek,generic-tphy-v2+â.�Tokayusb-phy@0‚†*�ref'TokayU,usb-phy@8000‚€†*�ref'TokayU-usb-phy@8700‚‡ †*�ref'TokayU.pcie@112ff000mediatek,mt2712-pcievpci‚/ð¼port1D+ nu ¸pcie_irq†„$�sys_ck1ahb_ck1Æ. Upcie-phy1_ÿâ‚@@0 TdisabledÌi`|2222interrupt-controller·ÌU2pcie@11700000mediatek,mt2712-pcievpci‚p¼port0D+ ns ¸pcie_irq†ƒ#�sys_ck0ahb_ck0Æ3 Upcie-phy0_ÿâ‚  TdisabledÌi`|4444interrupt-controller·ÌU4syscon@13000000mediatek,mt2712-mfgcfgsyscon‚Nsyscon@14000000mediatek,mt2712-mmsyssyscon‚NU6larb@14021000mediatek,mt2712-smi-larb‚Š5—Ô†66�apbsmiUsmi@14022000mediatek,mt2712-smi-common‚ Ô†66�apbsmiU5larb@14027000mediatek,mt2712-smi-larb‚pŠ7—Ô†6,6,�apbsmiUlarb@14030000mediatek,mt2712-smi-larb‚Š7—Ô†6.6.�apbsmiUsmi@14031000mediatek,mt2712-smi-common‚Ô†6-6-�apbsmiU7larb@14032000mediatek,mt2712-smi-larb‚ Š7—Ô†6868�apbsmiUsyscon@15000000mediatek,mt2712-imgsyssyscon‚NU8larb@15001000mediatek,mt2712-smi-larb‚Š5—Ô†88�apbsmiUsyscon@15010000mediatek,mt2712-bdpsyssyscon‚Nsyscon@16000000mediatek,mt2712-vdecsyssyscon‚NU9larb@16010000mediatek,mt2712-smi-larb‚Š5—Ô†99�apbsmiUsyscon@18000000mediatek,mt2712-vencsyssyscon‚NU:larb@18001000mediatek,mt2712-smi-larb‚Š5—Ô†::�apbsmiUlarb@18002000mediatek,mt2712-smi-larb‚ Š5—Ô†::�apbsmiUsyscon@19000000!mediatek,mt2712-jpgdecsyssyscon‚Naliases¨/serial@11002000memory@40000000vmemory‚@€chosen°serial0:921600n8regulator-vproc-buck0regulator-fixed ¼vproc_buck0ËB@ãB@Uregulator-vproc-buck1regulator-fixed ¼vproc_buck1ËB@ãB@U extcon_iddiglinux,extcon-usb-gpio û" U(extcon_iddig1linux,extcon-usb-gpio û"U0regulator-usb-p0-vbusregulator-fixed¼p0_vbusËLK@ãLK@ €" U'regulator-usb-p1-vbusregulator-fixed¼p1_vbusËLK@ãLK@ €"U/regulator-usb-p2-vbusregulator-fixed¼p2_vbusËLK@ãLK@ €"U+regulator-usb-p3-vbusregulator-fixed¼p3_vbusËLK@ãLK@ €" compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeopp-sharedphandleopp-hzopp-microvoltcpudevice_typeregclocksclock-namesproc-supplyoperating-points-v2cpu-idle-statesenable-methodentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramclock-frequency#clock-cellsclock-output-namesinterrupts#reset-cellsmediatek,pctl-regmapgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxdrive-strengthinput-enableinput-disablebias-disablebias-pull-up#power-domain-cellsinfracfgdmasdma-namesstatusassigned-clocksassigned-clock-parentsmediatek,infracfgmediatek,larbs#iommu-cellsdma-requests#dma-cells#io-channel-cells#pwm-cellsclock-divecc-enginesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,prioritysnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightinterrupt-namesmac-addresspower-domainsmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlemediatek,tx-delay-pssnps,reset-gpiosnps,reset-delays-uspinctrl-namespinctrl-0pinctrl-1reg-namesphysmediatek,syscon-wakeuprangesvbus-supplyextcondr_modewakeup-sourcemediatek,u3p-dis-msk#phy-cellsenable-manual-drdlinux,pci-domainphy-namesbus-rangeinterrupt-map-maskinterrupt-mapmediatek,smimediatek,larb-idserial0stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltid-gpiosenable-active-highregulator-always-on