Ð þíV8¤(²lMarvell RD-AC5X Board)marvell,rd-ac5xmarvell,ac5xmarvell,ac5"1cpus"1cpu-mapcluster0core0=core1=cpu@0Acpuarm,cortex-a55MQpsci_pcpu@1Acpuarm,cortex-a55MQpsci_pl2-cachecachex„ppsci arm,psci-0.2Xsmctimerarm,armv8-timer0’  pmuarm,cortex-a55-pmu ’ soc simple-bus"1�internal-regs@7f000000"1 simple-bus�¤serial@12000snps,dw-apb-uartM ± ’S»ÈÏokayserial@12100snps,dw-apb-uartM!± ’T»È Ïdisabledserial@12200snps,dw-apb-uartM"± ’U»È Ïdisabledserial@12300snps,dw-apb-uartM#± ’V»È Ïdisabledmdio@22004"1marvell,orion-mdioM Èethernet-phy@0Mp i2c@11000marvell,mv78230-i2cM "1ÈÖcore ’W↠ òdefaultgpio   Ïokayi2c@11100marvell,mv78230-i2cM "1ÈÖcore ’X↠ òdefaultgpio    Ïokaygpio@18100marvell,orion-gpioM�@( /?K Wðj0’KLMNpgpio@18140M�@@marvell,orion-gpio(/?K Wðj’OPbus@80500000 simple-bus�"1M€P�€¤mmc@805c0000-marvell,ac5-sdhcimarvell,armada-ap806-sdhciM€\ ’\È  Öcoreaxi›¥³ÀÏÏokaybehind-32bit-controller@7f000000 simple-bus"1��¤ethernet@20000marvell,armada-ac5-netaM@ ’-ÈÞsgmiiÏokayç ethernet@24000marvell,armada-ac5-netaM@@ ’7ÈÞsgmii Ïdisabledusb@80000marvell,orion-ehciM ’CÏokayusb@a0000marvell,orion-ehciM  ’EÏokayò÷usb-phy peripheralpinctrl@80020100marvell,ac5-pinctrlM€ p i2c0-pins  mpp26mpp27i2c0pi2c0-gpio-pins  mpp26mpp27gpiopi2c1-pins  mpp20mpp21i2c1p i2c1-gpio-pins  mpp20mpp21i2c1p spi@805a0000marvell,armada-3700-spiM€ZP"1È ’Z'Ïokayflash@0jedec,spi-nor.úð€@QM"1partition@0bspi_flash_part0M€parition@1bspi_flash_part1M€pparition@2bspi_flash_part2Mðspi@805a8000marvell,armada-3700-spiM€Z€P"1È ’[' Ïdisablednand-controller@805b0000marvell,ac5-nand-controllerM€[T"1 ’YÈ Ïdisabledinterrupt-controller@80600000 arm,gic-v3j M€`€f ’pclockscnm-clock fixed-clockhâ_@pspi-clock fixed-clockhâ ëÂpnand-clock fixed-clockhâׄpemmc-clock fixed-clockhâׄp aliases)u/soc/internal-regs@7f000000/serial@12000}/soc/spi@805a0000/flash@0'‡/soc/internal-regs@7f000000/gpio@18100'�/soc/internal-regs@7f000000/gpio@181405“/soc/behind-32bit-controller@7f000000/ethernet@200005�/soc/behind-32bit-controller@7f000000/ethernet@24000memory@0AmemoryM@usb-phyusb-nop-xceiv§p modelcompatibleinterrupt-parent#address-cells#size-cellscpudevice_typeregenable-methodnext-level-cachephandlecache-levelcache-unifiedinterruptsrangesdma-coherentreg-shiftreg-io-widthclocksstatusclock-namesclock-frequencypinctrl-namespinctrl-0pinctrl-1scl-gpiossda-gpiosngpiosgpio-controller#gpio-cellsgpio-rangesmarvell,pwm-offsetinterrupt-controller#interrupt-cellsdma-rangesbus-widthnon-removablemmc-ddr-1_8vmmc-hs200-1_8vmmc-hs400-1_8vphy-modephy-handlephysphy-namesdr_modemarvell,pinsmarvell,functionnum-csspi-max-frequencyspi-tx-bus-widthspi-rx-bus-widthlabel#clock-cellsserial0spiflash0gpio0gpio1ethernet0ethernet1#phy-cells