Ð þí¨„8žä(  ž¬+hisilicon,hi3660-hikey960hisilicon,hi3660 + 7HiKey960psci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53HcpuTXpscif w ‡Pš ¡µÄnÞcpu@1arm,cortex-a53HcpuTXpscif w ‡Pš ¡µÞcpu@2arm,cortex-a53HcpuTXpscif w ‡Pš ¡µÞcpu@3arm,cortex-a53HcpuTXpscif w ‡Pš ¡µÞcpu@100arm,cortex-a73HcpuTXpscifw‡š ¡µÄ&Þcpu@101arm,cortex-a73HcpuTXpscifw‡š ¡µÞcpu@102arm,cortex-a73HcpuTXpscifw‡š ¡µÞcpu@103arm,cortex-a73HcpuTXpscifw‡š ¡µÞ idle-statesæpscicpu-sleep-0arm,idle-stateó�,Š<ÜÞ cluster-sleep-0arm,idle-stateóô,@< ¬Þ cpu-sleep-1arm,idle-stateó�,&<ÜÞcluster-sleep-1arm,idle-stateó , T< ¬Þl2-cache0cacheMYÞ l2-cache1cacheMYÞopp-table-0operating-points-v2gÞopp00rÄï@y ®`‡“àopp01r;‹‡Ày 5‡“àopp02rS�Ò€y » ‡“àopp03reÝE@yB@‡“àopp04rmé5yÈà‡“àopp-table-1operating-points-v2gÞopp10r5Ò¯Ày ®`‡“àopp11rT²½@y 5‡“àopp12rk–@y » ‡“àopp13r}â�yB@‡“àopp14rŒÉB€yÈà‡“àinterrupt-controller@e82b0000 arm,gic-400@Tè+è+ è+@ è+` ˜© ¾ ÿÞa53-pmuarm,cortex-a53-pmu0¾Éa73-pmuarm,cortex-a73-pmu0¾É timerarm,armv8-timer 0¾ ÿÿ ÿ ÿsoc simple-bus+Ücrg_ctrl@fff35000 hisilicon,hi3660-crgctrlsysconTÿóPãÞcrg_rst_controllerhisilicon,hi3660-resetðýÞpctrl@e8a09000hisilicon,hi3660-pctrlsysconTè � ãÞMcrg_ctrl@fff34000 hisilicon,hi3660-pmuctrlsysconTÿó@ãsctrl@fff0a000hisilicon,hi3660-sctrlsysconTÿð ãÞ9iomcu@ffd7e000hisilicon,hi3660-iomcusysconTÿ×àãÞresethisilicon,hi3660-resetýðÞmailbox@e896b000hisilicon,hi3660-mboxTè–°¾ÀÁ Þstub_clock@e896b500hisilicon,hi3660-stub-clkTè–µã Þ timer@fff14000arm,sp804arm,primecellTÿñ@¾01š    timer1timer2apb_pclki2c@ffd71000snps,designware-i2cTÿ× ¾v+,€š < CdefaultQ[okaybLS-I2C0i2c@ffd72000snps,designware-i2cTÿ×  ¾w+,€š < CdefaultQ[okayrt1711h@4erichtek,rt1711hTN[okay ¾CdefaultQconnectorusb-c-connectorbUSB-Chdualrdual}sinkŒ�2˜�2†A�d¢˜–€ports+port@1Tendpoint´ÞPport+endpoint@0T´ÞOadv7533@39[okay adi,adv7533T9Äports+port@0Tport@1Ti2c@fdf0c000snps,designware-i2cTýðÀ ¾Q+,€š7 <xCdefaultQ ! [disabledi2c@fdf0b000snps,designware-i2cTýð° ¾:+,€š6 <`CdefaultQ"#[okaybLS-I2C1serial@fdf02000arm,pl011arm,primecellTýð  ¾Jšh uartclkapb_pclkCdefaultQ$% [disabledserial@fdf00000arm,pl011arm,primecellTýð ¾KÒrxtxÜ&&š99 uartclkapb_pclkCdefaultQ'( [disabledserial@fdf03000arm,pl011arm,primecellTýð0 ¾LÒrxtxÜ&&š: uartclkapb_pclkCdefaultQ)* [disabledserial@ffd74000arm,pl011arm,primecellTÿ×@ ¾rš uartclkapb_pclkCdefaultQ+,[okay bLS-UART0serial@fdf01000arm,pl011arm,primecellTýð ¾MÒrxtxÜ&&š;; uartclkapb_pclkCdefaultQ-.[okaybluetooth ti,wl1837-st á/î-ÆÀserial@fdf05000arm,pl011arm,primecellTýðP ¾NÒrxtxÜ&& š<< uartclkapb_pclkCdefaultQ01 [disabledserial@fff32000arm,pl011arm,primecellTÿó  ¾Oš  uartclkapb_pclkCdefaultQ23[okay bLS-UART1dma@fdf30000hisilicon,k3-dma-1.0Týóø ÿþ ¾�š>. 9hi3660_dmaÞ&dma-controller@e804b000hisilicon,hisi-pcm-asp-dma-1.0Tè°ø  ¾Ø Basp_dma_irqrtc@fff04000arm,pl031arm,primecellTÿð@ ¾.š  apb_pclkgpio@e8a0b000arm,pl061arm,primecellTè ° ¾TRbn4©˜š  apb_pclkLzTP901[PMU0_SSI][PMU1_SSI][PMU2_SSI][PMU0_CLKOUT][JTAG_TCK][JTAG_TMS]gpio@e8a0c000arm,pl061arm,primecellTè À ¾URbn4©˜š   apb_pclkCz[JTAG_TRST_N][JTAG_TDI][JTAG_TDO]NCNC[I2C3_SCL][I2C3_SDA]NCgpio@e8a0d000arm,pl061arm,primecellTè Ð ¾VRbn4©˜š!  apb_pclkGzNCNCNCGPIO-JGPIO_020_HDMI_SELGPIO-LGPIO_022_UFSBUCK_INT_NGPIO-Ggpio@e8a0e000arm,pl061arm,primecellTè à ¾WRbn4©˜š"  apb_pclkJz[CSI0_MCLK][CSI1_MCLK]NC[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]NCgpio@e8a0f000arm,pl061arm,primecellTè ð ¾XRbn4©˜š#  apb_pclkAzNCNCPWR_BTN_NGPIO_035_PMU2_ENGPIO_036_USB_HUB_RESETNCNCNCÞvgpio@e8a10000arm,pl061arm,primecellTè¡ ¾YRbn4&©˜š$  apb_pclkQzGPIO-HGPIO_041_HDMI_PDTP904TP905NCNCGPIO_046_HUB_VDD33_ENGPIO_047_PMU1_ENgpio@e8a11000arm,pl061arm,primecellTè¡ ¾ZRbn4.©˜š%  apb_pclkAzNCNCNCGPIO_051_WIFI_ENGPIO-I[SD_DAT1][SD_DAT2][UART1_RXD]Þxgpio@e8a12000arm,pl061arm,primecellTè¡  ¾[Rbn46©˜š&  apb_pclkyz[UART1_TXD][UART0_CTS][UART0_RTS][UART0_RXD][UART0_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD]gpio@e8a13000arm,pl061arm,primecellTè¡0 ¾\Rbn4>©˜š'  apb_pclk?z[SOC_BT_UART4_TXD]NC[PMU_HKADC_SSI]NCGPIO_068_SELNCNCNCgpio@e8a14000arm,pl061arm,primecellTè¡@ ¾]Rbn4F©˜š(  apb_pclkzNCNCNCGPIO-KNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTè¡P ¾^Rbn4N©˜š)  apb_pclkzNCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellTè¡` ¾_Rbn4V©˜š*  apb_pclk$zNC[PCIE_PERST_N]NCNCNCNCNCNCÞ?gpio@e8a17000arm,pl061arm,primecellTè¡p ¾`Rb n4^4e©˜š+  apb_pclkzNCNCNCNCgpio@e8a18000arm,pl061arm,primecellTè¡€ ¾aRbn4f©˜š,  apb_pclkzNCNCNCNCNCNCNCNCgpio@e8a19000arm,pl061arm,primecellTè¡� ¾bRbn4n©˜š-  apb_pclkzNCNCNCNCNCNCNCNCgpio@e8a1a000arm,pl061arm,primecellTè¡  ¾cRbn4v©˜š.  apb_pclk'zNCNCNCNCNCNCGPIO_126_BT_ENTP902Þ/gpio@e8a1b000arm,pl061arm,primecellTè¡° ¾dRb©˜š/  apb_pclkzgpio@e8a1c000arm,pl061arm,primecellTè¡À ¾eRb©˜š0  apb_pclkzgpio@ff3b4000arm,pl061arm,primecellTÿ;@ ¾fRbn5©˜š1  apb_pclkmz[UFS_REF_CLK][UFS_RST_N][SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS]GPIO_150_USER_LED1GPIO_151_USER_LED2Þ>gpio@ff3b5000arm,pl061arm,primecellTÿ;P ¾gRbn5©˜š2  apb_pclkzNCNCNCNCgpio@e8a1f000arm,pl061arm,primecellTè¡ð ¾hRbn6©˜š3  apb_pclk@z[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]gpio@e8a20000arm,pl061arm,primecellTè¢ ¾iRb©˜n7š4  apb_pclk^z[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3]gpio@fff0b000arm,pl061arm,primecellTÿð° ¾jRbn8©˜š9  apb_pclkdz[GPIO_176_PMU_PWR_HOLD]NA[SYSCLK_EN]GPIO_179_WL_WAKEUP_APGPIO_180_HDMI_INTNAGPIO-F[I2C0_SCL]ÞJgpio@fff0c000arm,pl061arm,primecellTÿðÀ ¾kRbn8©˜š9  apb_pclk^z[I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C1_SCL][I2C1_SDA]GPIO_189_USER_LED3GPIO_190_USER_LED4Þwgpio@fff0d000arm,pl061arm,primecellTÿðÐ ¾lRbn8 ©˜š9  apb_pclktz[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][GPIO_196_I2S2_DI][GPIO_197_I2S2_DO][GPIO_198_I2S2_XCLK][GPIO_199_I2S2_XFS]gpio@fff0e000arm,pl061arm,primecellTÿðà ¾mRb n88©˜š9  apb_pclkzzNCNCGPIO_202_VBUS_TYPECGPIO_203_SD_DETGPIO_204_PMU12_IRQ_NGPIO_205_WIFI_ACTIVEGPIO_206_USBSW_SELGPIO_207_BT_ACTIVEÞ@gpio@fff0f000arm,pl061arm,primecellTÿðð ¾nRbn8©˜š9  apb_pclkLzGPIO-AGPIO-BGPIO-CGPIO-DGPIO-E[PCIE_CLKREQ_N][PCIE_WAKE_N][SPI0_CLK]gpio@fff10000arm,pl061arm,primecellTÿñ ¾oRbn8$©˜š9  apb_pclkBz[SPI0_DIN][SPI0_DOUT][SPI0_CS]GPIO_219_CC_INTNCNC[PMU_INT]Þgpio@fff1d000arm,pl061arm,primecellTÿñÐ ¾�Rb©˜š9  apb_pclkzspi@ffd68000arm,pl022arm,primecellTÿÖ€+ ¾tš sspclkapb_pclkCdefaultQ:;Š ‘[okaybLS-SPI0spi@ff3b3000arm,pl022arm,primecellTÿ;0+ ¾8š55 sspclkapb_pclkCdefaultQ<=Š ‘>[okaybHS-SPI1pcie@f4000000hisilicon,kirin960-pcie@Tôÿ?àóòõ šdbiapbphyconfig¤ÿ+HpciÜö®˜ ¾Bmsi¸ø€Ë(šRSQP: pcie_phy_refpcie_auxpcie_apb_phypcie_apb_syspcie_aclk Ù?ufs@ff3b0000#hisilicon,hi3660-ufsjedec,ufs-1.1 Tÿ;ÿ;  ¾šfe ref_clkphy_clkå <„ órstdwmmc1@ff37f000hisilicon,hi3660-dw-mshcTÿ7ð+ ¾‹šK ciubiu,0Ô <”óresetÿ9È[okay-7HUbo} ˆ@Cdefault QABC‘D�Edwmmc2@ff3ff000hisilicon,hi3660-dw-mshcTÿ?ð+ ¾ŒšL ciubiu <”óresetÈ[okay-ª¸ÂCdefault QFGH‘Iwlcore@2 ti,wl1837T J¾watchdog@e8a06000arm,sp805arm,primecellTè ` ¾,š   wdog_clkapb_pclkwatchdog@e8a07000arm,sp805arm,primecellTè p ¾-š   wdog_clkapb_pclktsensor@fff30000hisilicon,hi3660-tsensorTÿó ¾‘ÕÞKthermal-zonescls0-thermalëèùd”!Ktripstrip-point01ýè=èOpassivetrip-point11$ø=èOpassiveÞLcooling-mapsmap0HLM0Zÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1HLM0Zÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿusb3_otg_bc@ff200000/hisilicon,hi3660-usb3-otg-bcsysconsimple-mfdTÿ usb-phyhisilicon,hi3660-usb-phyit�M¤$fäÞNusb@ff100000 snps,dwc3TÿšI refbus_earlyÀIÐ ¦C@0<����¾Ÿ¡åN êusb3-phyôotg üsuper-speed utmi4Kd}—«ÃÙéhostport+endpoint@0T´OÞendpoint@1T´PÞetm@ecc40000"arm,coresight-etm4xarm,primecellTìÄš  apb_pclkDout-portsportendpoint´QÞVetm@ecd40000"arm,coresight-etm4xarm,primecellTìÔš  apb_pclkDout-portsportendpoint´RÞWetm@ece40000"arm,coresight-etm4xarm,primecellTìäš  apb_pclkDout-portsportendpoint´SÞXetm@ecf40000"arm,coresight-etm4xarm,primecellTìôš  apb_pclkDout-portsportendpoint´TÞYfunnel@ec801000+arm,coresight-dynamic-funnelarm,primecellT쀚  apb_pclkout-portsportendpoint´UÞZin-ports+port@0Tendpoint´VÞQport@1Tendpoint´WÞRport@2Tendpoint´XÞSport@3Tendpoint´YÞTetf@ec802000 arm,coresight-tmcarm,primecellTì€ š  apb_pclkin-portsportendpoint´ZÞUout-portsportendpoint´[Þhetm@ed440000"arm,coresight-etm4xarm,primecellTíDš  apb_pclkDout-portsportendpoint´\Þaetm@ed540000"arm,coresight-etm4xarm,primecellTíTš  apb_pclkDout-portsportendpoint´]Þbetm@ed640000"arm,coresight-etm4xarm,primecellTídš  apb_pclkDout-portsportendpoint´^Þcetm@ed740000"arm,coresight-etm4xarm,primecellTítš  apb_pclkD out-portsportendpoint´_Þdfunnel@ed001000+arm,coresight-dynamic-funnelarm,primecellTíš  apb_pclkout-portsportendpoint´`Þein-ports+port@0Tendpoint´aÞ\port@1Tendpoint´bÞ]port@2Tendpoint´cÞ^port@3Tendpoint´dÞ_etf@ed002000 arm,coresight-tmcarm,primecellTí š  apb_pclkin-portsportendpoint´eÞ`out-portsportendpoint´fÞifunnelarm,coresight-static-funnelš  apb_pclkout-portsportendpoint´gÞkin-ports+port@0Tendpoint´hÞ[port@1Tendpoint´iÞffunnel@ec031000+arm,coresight-dynamic-funnelarm,primecellTìš  apb_pclkout-portsportendpoint´jÞlin-ports+port@0Tendpoint´kÞgetf@ec036000 arm,coresight-tmcarm,primecellTì`š  apb_pclkin-portsportendpoint´lÞjout-portsportendpoint´mÞnreplicator arm,coresight-static-replicatorš  apb_pclkin-portsportendpoint´nÞmout-ports+port@0Tendpoint´oÞqport@1Tendpoint´pÞretr@ec033000 arm,coresight-tmcarm,primecellTì0š  apb_pclkin-portsportendpoint´qÞotpiu@ec032000!arm,coresight-tpiuarm,primecellTì š  apb_pclkin-portsportendpoint´rÞpgpio-rangeÞspinmux@e896c000pinctrl-singleTè–Àð#2D b sstÞ4pmu-pins ™ csi0-pwd-n-pins™Dcsi1-pwd-n-pins™Lisp0-pins™Xdhisp1-pins™\lppwr-key-pins™€Þti2c3-pins™,0Þ i2c4-pins™�”pcie-perstn-pins™\usbhub5734-pins™ uart0-pins™ÌÐÞ$uart1-pins ™°´¨¬Þ'uart2-pins ™¼ÀÈÄÞ)uart3-pins ™ÜàäèÞ+uart4-pins ™ìðôøÞ-uart5-pins ™ÄȼÀÞ0uart6-pins ™ÌÐÔØÞ2cam0-rst-pins™Ècam1-rst-pins™$pinmux@ff37e000pinctrl-singleTÿ7à2#D bsÞ6sd-pins0™ ÞApinmux@ff3b6000pinctrl-singleTÿ;`0#2D bs Þ5ufs-pins™spi3-pins ™ Þ<pinmux@ff3fd000pinctrl-singleTÿ?Ð#2D bsÞ7sdio-pins0™ ÞFpinmux@fff11000pinctrl-singleTÿñ¨#2D bs*Þ8i2s2-pins ™DHLPslimbus-pins™,0i2c0-pins™Þi2c1-pins™ Þi2c7-pins™$(Þ"pcie-pins™„ˆspi2-pins ™Œ�”˜Þ:i2s0-pins ™48<@pinmux@e896c800pinconf-singleTè–È#D pmu-cfg-pins ™ ­Êå ði2c3-cfg-pins™8<­ÊåðÞ!csi0-pwd-n-cfg-pins™P­Êåðcsi1-pwd-n-cfg-pins™X­Êåðisp0-cfg-pins™dpt­Êåðisp1-cfg-pins™hx|­Êåðpwr-key-cfg-pins™Œ­ÊåðÞuuart1-cfg-pins ™´¸¼À­ÊåðÞ(uart2-cfg-pins ™ÈÌÐÔ­ÊåðÞ*uart5-cfg-pins ™ÈÌÐÔ­ÊåðÞ1cam0-rst-cfg-pins™Ô­Êåðuart0-cfg-pins™ØÜ­ÊåðÞ%uart6-cfg-pins ™ØÜàä­ÊåðÞ3uart3-cfg-pins ™èìðô­ÊåðÞ,uart4-cfg-pins ™øü­ÊåðÞ.cam1-rst-cfg-pins™0­Êåðpinmux@ff3b6800pinconf-singleTÿ;h#D ufs-cfg-pins™­Êå0ðspi3-cfg-pins ™ ­Êå ðÞ=pinmux@ff3fd800pinconf-singleTÿ?Ø#D sdio-clk-cfg-pins™­ÊåððÞGsdio-cfg-pins(™ ­Êå€ðÞHpinmux@ff37e800pinconf-singleTÿ7è#D sd-clk-cfg-pins™­ÊåððÞBsd-cfg-pins(™ ­Êå€ðÞCpinmux@fff11800pinconf-singleTÿñ¼#D i2c0-cfg-pins™ ­ÊåðÞi2c1-cfg-pins™$(­ÊåðÞi2c7-cfg-pins™,0­ÊåðÞ#slimbus-cfg-pins™48­Êåði2s0-cfg-pins ™@DHL­Êåði2s2-cfg-pins ™PTX\­Êåðpcie-cfg-pins™”˜­Êåðspi2-cfg-pins ™œ ¤¨­Êå ðÞ;usb-cfg-pins™¬­ÊåðÞaliases/soc/dwmmc1@ff37f000 /soc/dwmmc2@ff3ff000/soc/serial@fdf02000/soc/serial@fdf00000/soc/serial@fdf03000'/soc/serial@ffd74000//soc/serial@fdf010007/soc/serial@fdf05000?/soc/serial@fff32000chosenGserial6:115200n8memory@0HmemoryTreserved-memory+Üramoops@32000000ramoopsT2S_lreboot-mode-syscon@32100000sysconsimple-mfdT2reboot-modesyscon-reboot-modexwfU‹wfU›wfUkeys gpio-keysCdefaultQtukey-power© èv bGPIO Power·tleds gpio-ledsled-user-1 bgreen:user1 è> Âheartbeatled-user-2 bgreen:user2 è>Ânoneled-user-3 bgreen:user3 èwÂmmc0led-user-4 bgreen:user4 èwØÂnoneled-wlan byellow:wlan è@Âphy0txèoffled-btbblue:bt è@ Âhci0-powerèoffpmic@fff34000hisilicon,hi6421v530-pmicTÿó@©˜regulatorsLDO3 öVOUT3_1V85 w@ !‘À 5xLDO9öVOUT9_1V8_2V95 ³ð 2Z  5ðÞELDO11öVOUT11_1V8_2V95 ³ð 2Z  5ðLDO15 öVOUT15_3V0 ³ð -ÆÀ Q c 5xLDO16 öVOUT16_2V95 ³ð -ÆÀ 5hÞDwlan-en-1-8vregulator-fixedöwlan-en-regulator w@ w@ wx |p �ÞIfirmwareopteelinaro,optee-tz=smc compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachecpu-idle-statescapacity-dmips-mhzclocksoperating-points-v2#cooling-cellsdynamic-power-coefficientphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinityranges#clock-cells#reset-cellshisi,rst-syscon#mbox-cellsmboxesclock-namesclock-frequencyresetspinctrl-namespinctrl-0statuslabeldata-rolepower-roletry-power-rolesource-pdossink-pdosop-sink-microwattremote-endpointadi,dsi-lanesdma-namesdmasenable-gpiosmax-speed#dma-cellsdma-channelsdma-requestsdma-channel-maskdma-no-ccidma-typeinterrupt-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namesnum-cscs-gpiosreg-namesbus-rangenum-lanesinterrupt-map-maskinterrupt-mapreset-gpiosfreq-table-hzreset-nameshisilicon,peripheral-sysconcard-detect-delaybus-widthcap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104disable-wpcd-gpiosvmmc-supplyvqmmc-supplynon-removablebroken-cdcap-power-off-card#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcontributioncooling-device#phy-cellshisilicon,pericrg-sysconhisilicon,pctrl-sysconhisilicon,eye-diagram-paramassigned-clocksassigned-clock-ratesphysphy-namesdr_modemaximum-speedphy_typesnps,dis-del-phy-power-chg-quirksnps,lfps_filter_quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirksnps,tx_de_emphasis_quirksnps,tx_de_emphasissnps,dis_enblslpm_quirksnps,gctl-reset-quirkusb-role-switchrole-switch-default-mode#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathrecord-sizeconsole-sizeftrace-sizeoffsetmode-normalmode-bootloadermode-recoverywakeup-sourcelinux,codelinux,default-triggerpanic-indicatordefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-boot-onregulator-always-ongpiostartup-delay-usenable-active-high