Ð þíj08d4(ücü ARM Juno development board (r0)arm,junoarm,vexpress"1clock-7372800 fixed-clock=Jp€ Zjuno:uartclkmBclock-48000000 fixed-clock=JÜl Zclk48mhzmFclock-50000000 fixed-clock=Júð€Zsmc_clkm clock-100000000 fixed-clock=Jõá Zapb_pclkm clock-400000000 fixed-clock=Jׄ Zfaxi_clkm<clock-24000000 fixed-clock=Jn6Zjuno_mb:clk24mhzmclock-25000000 fixed-clock=J}x@Zjuno_mb:clk25mhzmclock-1000000 fixed-clock=JB@Zjuno_mb:refclk1mhzmclock-32768 fixed-clock=J€Zjuno_mb:refclk32khzmregulator-3v3regulator-fixed uMCC_SB_3V3„2Z œ2Z ´mgpio-keys gpio-keyspower-buttonÈ2ÚètóPOWER ùhome-buttonÈ2ÚèfóHOME ùrlock-buttonÈ2Úè˜óRLOCK ùvol-up-buttonÈ2ÚèsóVOL+ ùvol-down-buttonÈ2ÚèróVOL- ùnmi-buttonÈ2ÚècóNMI ùbus@8000000 simple-bus"1ÿ  *DEF ¡¢£¤¥ ¦ § ¨ ©motherboard-bus@8000000arm,vexpress,v2p-p1simple-bus"1xÿ 8R@flash@0arm,vexpress-flashcfi-flash RV adisabledpartitionsarm,arm-firmware-suiteethernet@200000000smsc,lan9118smsc,lan9115 Rhsmii|‰ž±¸Æiofpga-bus@300000000 simple-bus"1ÿ sysctl@20000arm,sp810arm,primecellR ±Örefclktimclkapb_pclk=0Ztimerclken0timerclken1timerclken2timerclken3 âòmapbregs@10000)arm,juno-fpga-apb-regssysconsimple-mfdR ÿ"1led@8,0register-bit-ledR % óvexpress:0 heartbeat&onled@8,1register-bit-ledR % óvexpress:1mmc0&offled@8,2register-bit-ledR % óvexpress:2cpu0&offled@8,3register-bit-ledR % óvexpress:3cpu1&offled@8,4register-bit-ledR % óvexpress:4cpu2&offled@8,5register-bit-ledR %  óvexpress:5cpu3&offled@8,6register-bit-ledR %@ óvexpress:6&offled@8,7register-bit-ledR %€ óvexpress:7&offmmc@50000arm,pl180arm,primecellRh4·B± Ömclkapb_pclkkmi@60000arm,pl050arm,primecellRh± ÖKMIREFCLKapb_pclkkmi@70000arm,pl050arm,primecellRh± ÖKMIREFCLKapb_pclkwatchdog@f0000arm,sp805arm,primecellRh± Öwdog_clkapb_pclktimer@110000arm,sp804arm,primecellRh ±Ötimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellRh ±Ötimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellRh±  Öapb_pclkgpio@1d0000arm,pl061arm,primecellRh±  Öapb_pclkN^jmtimer@2a810000arm,armv7-timer-memR*�Júð€"1ÿ*‚ adisabledframe@2a830000 h<Rmhu@2b1f0000arm,mhu-doorbellarm,primecellR+$h$#%Œ±  Öapb_pclkmKiommu@2b400000arm,mmu-400arm,smmu-v1R+@h&&˜¥¸ Æ adisablediommu@2b500000arm,mmu-401arm,smmu-v1R+Ph((˜¥Æ adisabledm9iommu@2b600000arm,mmu-401arm,smmu-v1R+`h**˜¥Æ¸ minterrupt-controller@2c010000arm,gic-400arm,cortex-a15-gic@R,,ð ,ð ,ð "1j h ?ÿ,mv2m@0arm,gic-v2m-frameÓRm8v2m@10000arm,gic-v2m-frameÓRv2m@20000arm,gic-v2m-frameÓRv2m@30000arm,gic-v2m-frameÓRtimerarm,armv8-timer0h ?? ? ?etf@20010000 arm,coresight-tmcarm,primecellR ±  Öapb_pclk¸ m4in-portsportendpointâ mout-portsportendpointâ mtpiu@20030000!arm,coresight-tpiuarm,primecellR ±  Öapb_pclk¸ m6in-portsportendpointâmfunnel@20040000+arm,coresight-dynamic-funnelarm,primecellR ±  Öapb_pclk¸ out-portsportendpointâm in-ports"1port@0Rendpointâmport@1Rendpointâm%port@2Rendpointâmetr@20070000 arm,coresight-tmcarm,primecellR ò±  Öapb_pclk¸ ùm3in-portsportendpointâmstm@20100000 arm,coresight-stmarm,primecell R ( stm-basestm-stimulus-base±  Öapb_pclk¸ m5out-portsportendpointâmreplicator@20120000/arm,coresight-dynamic-replicatorarm,primecellR ±  Öapb_pclk¸ out-ports"1port@0Rendpointâmport@1Rendpointâmin-portsportendpointâm cpu-debug@22010000&arm,coresight-cpu-debugarm,primecellR"±  Öapb_pclk¸ etm@22040000"arm,coresight-etm4xarm,primecellR"±  Öapb_pclk¸ mout-portsportendpointâmcti@22020000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR"±  Öapb_pclk¸ funnel@220c0000+arm,coresight-dynamic-funnelarm,primecellR" ±  Öapb_pclk¸ out-portsportendpointâmin-ports"1port@0Rendpointâmport@1Rendpointâm cpu-debug@22110000&arm,coresight-cpu-debugarm,primecellR"±  Öapb_pclk¸ etm@22140000"arm,coresight-etm4xarm,primecellR"±  Öapb_pclk¸ m!out-portsportendpointâ mcti@22120000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR"±  Öapb_pclk¸ !cpu-debug@23010000&arm,coresight-cpu-debugarm,primecellR#±  Öapb_pclk¸ "etm@23040000"arm,coresight-etm4xarm,primecellR#±  Öapb_pclk¸ "m$out-portsportendpointâ#m&cti@23020000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR#±  Öapb_pclk¸ $"funnel@230c0000+arm,coresight-dynamic-funnelarm,primecellR# ±  Öapb_pclk¸ out-portsportendpointâ%min-ports"1port@0Rendpointâ&m#port@1Rendpointâ'm+port@2Rendpointâ(m.port@3Rendpointâ)m1cpu-debug@23110000&arm,coresight-cpu-debugarm,primecellR#±  Öapb_pclk¸ *etm@23140000"arm,coresight-etm4xarm,primecellR#±  Öapb_pclk¸ *m,out-portsportendpointâ+m'cti@23120000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR#±  Öapb_pclk¸ ,*cpu-debug@23210000&arm,coresight-cpu-debugarm,primecellR#!±  Öapb_pclk¸ -etm@23240000"arm,coresight-etm4xarm,primecellR#$±  Öapb_pclk¸ -m/out-portsportendpointâ.m(cti@23220000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR#"±  Öapb_pclk¸ /-cpu-debug@23310000&arm,coresight-cpu-debugarm,primecellR#1±  Öapb_pclk¸ 0etm@23340000"arm,coresight-etm4xarm,primecellR#4±  Öapb_pclk¸ 0m2out-portsportendpointâ1m)cti@23320000:arm,coresight-cti-v8-archarm,coresight-ctiarm,primecellR#2±  Öapb_pclk¸ 20cti@20020000 arm,coresight-ctiarm,primecellR ±  Öapb_pclk¸ "1trig-conns@0R+< N`3trig-conns@1R+< N`4trig-conns@2R+<N`5trig-conns@3RN`6cti@20110000 arm,coresight-ctiarm,primecellR ±  Öapb_pclk¸ "1trig-conns@0R+<N` ssys_profilertrig-conns@1RN` swatchdogtrig-conns@2RN` sg_countergpu@2d000000arm,juno-maliarm,mali-t624R-$h!"  †jobmmugpu±7¸ Æsram@2e000000arm,juno-sram-nsmmio-sramR.€"1ÿ.€scp-sram@0arm,scmi-shmemR€mLscp-sram@80arm,scmi-shmemR€€mMscp-sram@100arm,scmi-shmemR€mNscp-sram@180arm,scmi-shmemR€€mOpcie@40000000<arm,juno-r1-pcieplda,xpressrich3-axipci-host-ecam-generic–pciR@¢ÿ¬"1ÆTÿ_€€PPB@@8½€€€C�*ˆ‰Š‹È8 adisabledÓâ9thermal-zonespmic-thermalìèúd:tripstrip0 _�,Ð �criticalsoc-thermalìèúd:tripstrip0 8€,Ð �criticalbig-cl-thermalìèúd: adisabledlittle-cl-thermalìèúd: adisabledgpu0-thermalìèúd: adisabledgpu1-thermalìèúd: adisablediommu@7fb00000arm,mmu-401arm,smmu-v1R°h__˜¥Æm;iommu@7fb10000arm,mmu-401arm,smmu-v1R±hcc˜¥m=iommu@7fb20000arm,mmu-401arm,smmu-v1R²haa˜¥m@iommu@7fb30000arm,mmu-401arm,smmu-v1R³hee˜¥ÆmEdma-controller@7ff00000arm,pl330arm,primecellRð7lhXYZ[\lmnoHò;;;;;;;;;±< Öapb_pclkhdlcd@7ff50000 arm,hdlcdRõ h]ò=±>Öpxlclkportendpointâ?mDhdlcd@7ff60000 arm,hdlcdRö hUò@±>ÖpxlclkportendpointâAmCserial@7ff80000arm,pl011arm,primecellRø hS±B Öuartclkapb_pclki2c@7ffa0000snps,designware-i2cRú"1 hhJ€Bô± hdmi-transmitter@70 nxp,tda998xRpportendpointâCmAhdmi-transmitter@71 nxp,tda998xRqportendpointâDm?usb@7ffb0000 generic-ohciRû htòE±Fusb@7ffc0000 generic-ehciRü huòE±Fmemory-controller@7ffd0000arm,pl354arm,primecellRýhVW±  Öapb_pclkmemory@80000000–memory R€€€tlx-bus@60000000 simple-bus"1ÿ`*¨aliasesW/serial@7ff80000chosen_serial0:115200n8psci arm,psci-0.2ksmccpus"1cpu-mapcluster0core0core1cluster1core0"core1*core2-core30idle-statesrpscicpu-sleep-0arm,idle-state–§,¸°ÈÐmHcluster-sleep-0arm,idle-state–§�¸°È ÄmIcpu@0arm,cortex-a57R–cpuÙpsciçÀô@€ @2?G±7PHI`smcpu@1arm,cortex-a57R–cpuÙpsciçÀô@€ @2?G±7PHI`smcpu@100arm,cortex-a53R–cpuÙpsciç€ô@€ @2€?J±7PHI`BsŒm"cpu@101arm,cortex-a53R–cpuÙpsciç€ô@€ @2€?J±7PHI`BsŒm*cpu@102arm,cortex-a53R–cpuÙpsciç€ô@€ @2€?J±7PHI`BsŒm-cpu@103arm,cortex-a53R–cpuÙpsciç€ô@€ @2€?J±7PHI`BsŒm0l2-cache0cache�é ö@›mGl2-cache1cache�éö@›mJpmu-a57arm,cortex-a57-pmuh§pmu-a53arm,cortex-a53-pmu0h§"*-0firmwarescmi arm,scmiºtxrxÅKKÌLM"1protocol@11RÒm protocol@13R=ºtxrxÅKKÌNOm7protocol@14R=m>protocol@15Ræm: modelcompatibleinterrupt-parent#address-cells#size-cells#clock-cellsclock-frequencyclock-output-namesphandleregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ondebounce-intervalwakeup-sourcelinux,codelabelgpiosranges#interrupt-cellsinterrupt-map-maskinterrupt-maparm,hbiarm,vexpress,siteregbank-widthstatusinterruptsphy-modereg-io-widthsmsc,irq-active-highsmsc,irq-push-pullclocksvdd33a-supplyvddvario-supplyclock-namesassigned-clocksassigned-clock-parentsoffsetlinux,default-triggerdefault-statemax-frequencyvmmc-supplygpio-controller#gpio-cellsinterrupt-controllerframe-number#mbox-cells#iommu-cells#global-interruptspower-domainsdma-coherentmsi-controllerremote-endpointiommusarm,scatter-gatherreg-namescpuarm,cs-dev-assocarm,trig-in-sigsarm,trig-in-typesarm,trig-out-sigsarm,trig-out-typesarm,trig-conn-nameinterrupt-namesdevice_typebus-rangelinux,pci-domaindma-rangesmsi-parentiommu-map-maskiommu-mappolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresis#dma-cellsi2c-sda-hold-time-nsserial0stdout-pathmethodentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-idle-statescapacity-dmips-mhzdynamic-power-coefficientcache-unifiedcache-levelinterrupt-affinitymbox-namesmboxesshmem#power-domain-cells#thermal-sensor-cells