Ð þíñp8åä( Œå¬ ),rockchip,rk3568-evb1-v10rockchip,rk3568$7Rockchip RK3568 EVB1 DDR4 V10 Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe2a0000ç/ethernet@fe010000ñ/mmc@fe2b0000ö/mmc@fe310000cpus cpu@0ûcpu,arm,cortex-a55 !psci/C€P@b€o€|@Ž€›¬· cpu@100ûcpu,arm,cortex-a55!psci/C€P@b€o€|@Ž€›¬· cpu@200ûcpu,arm,cortex-a55!psci/C€P@b€o€|@Ž€›¬· cpu@300ûcpu,arm,cortex-a55!psci/C€P@b€o€|@Ž€›¬· l3-cache,cache¿ËER@d·opp-table-0,operating-points-v2Ù·opp-408000000äQ– ë »  » Œ0ùœ@opp-600000000ä#ÃF ë »  » Œ0opp-816000000ä0£, ë »  » Œ0 opp-1104000000äAÍ´ ë »  » Œ0opp-1416000000äTfr ë »  » Œ0opp-1608000000ä_Ø" ëà˜à˜Œ0opp-1800000000äkIÒ ë��Œ0opp-1992000000äv»‚ ëŒ0Œ0Œ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc‚' protocol@14-·opp-table-1,operating-points-v2·Gopp-200000000ä ëÂ ë øP øPB@opp-300000000äá£ ë øP øPB@opp-400000000äׄ ë øP øPB@opp-600000000ä#ÃF ë »  » B@opp-700000000ä)¹' ë~ð~ðB@opp-800000000ä/¯ ëB@B@B@hdmi-sound,simple-audio-card:HDMIQi2sj„okaysimple-audio-card,codec‹simple-audio-card,cpu‹ pmu,arm,cortex-a55-pmu0•äåæç  psci ,arm,psci-1.0(smctimer,arm,armv8-timer0•   ³xin24m ,fixed-clockÊn6Úxin24m-·xin32k ,fixed-clockÊ€Úxin32kí÷default-sram@10f000 ,mmio-sramð ðsram@0,arm,scmi-shmem·sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@ ›œ� satapmaliverxoob •_ sata-phy'9 „disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€  ¡¢ satapmaliverxoob •` sata-phy'9 „disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ •© ¦§¥ ref_clksuspend_clkbus_clkGotg Outmi_wide9X”_„okay usb2-phyusb3-phyxusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ •ª ©ª¨ ref_clksuspend_clkbus_clkGhost usb2-phyusb3-phy Outmi_wide9X•_„okayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF • ”¥ýA¯(º·usb@fd800000 ,generic-ehciý€ •‚ ½¾¼usb„okayusb@fd840000 ,generic-ohciý„ •ƒ ½¾¼usb„okayusb@fd880000 ,generic-ehciýˆ •… ¿À¼usb„okayusb@fd8c0000 ,generic-ohciýŒ •† ¿À¼usb„okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý·`io-domains&,rockchip,rk3568-pmu-io-voltage-domain„okayÉ×åó+9syscon@fdc50000ýÅ ,rockchip,rk3568-pipe-grfsyscon·´syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýÆ· syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýÈ·µsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýÉ·¶syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€··syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€·ºclock-controller@fdd00000,rockchip,rk3568-pmucruýÐ-G·clock-controller@fdd20000,rockchip,rk3568-cruýÒ  xin24m-GT d€G†Œ ëÂy� ·i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ •. -  i2cpclkí!÷default „okayregulator@1c ,tcs,tcs4525�ºvdd_cpuÉÝï 5Œ0ü4"·regulator-state-mem?pmic@20,rockchip,rk809 #•THy–- mclk H÷defaultí$%XyŠ&–&¢&®&º&Æ&Ò&Þ&ê&ö·ØregulatorsDCDC_REG1 ºvdd_logicÉÝï¡ ™pqregulator-state-mem?DCDC_REG2ºvdd_gpuÉï¡ ™pq·Hregulator-state-mem?DCDC_REG3ºvcc_ddrÉÝregulator-state-memDCDC_REG4ºvdd_npuï¡ ™pqregulator-state-mem?DCDC_REG5ºvcc_1v8ÉÝïw@w@·regulator-state-mem?LDO_REG1ºvdda0v9_imageï »  » ·\regulator-state-mem?LDO_REG2 ºvdda_0v9ÉÝï »  » regulator-state-mem?LDO_REG3 ºvdda0v9_pmuÉÝï »  » regulator-state-mem3 » LDO_REG4 ºvccio_acodecÉï2Z 2Z ·regulator-state-mem?LDO_REG5 ºvccio_sdïw@2Z ·regulator-state-mem?LDO_REG6 ºvcc3v3_pmuÉÝï2Z 2Z ·regulator-state-mem32Z LDO_REG7 ºvcca_1v8ÉÝïw@w@·§regulator-state-mem?LDO_REG8 ºvcca1v8_pmuÉÝïw@w@regulator-state-mem3w@LDO_REG9ºvcca1v8_imageïw@w@·]regulator-state-mem?SWITCH_REG1ºvcc_3v3ÉÝ·regulator-state-mem?SWITCH_REG2 ºvcc3v3_sd·fregulator-state-mem?codecOserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ •t  , baudclkapb_pclkl''í(÷defaultq~ „disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkí)÷defaultˆ „disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0  pwmpclkí*÷defaultˆ „disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0  pwmpclkí+÷defaultˆ „disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0  pwmpclkí,÷defaultˆ „disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controller“ ·power-domain@7 §-“power-domain@8 ÌÍ §./0“power-domain@9  ÚÛÜ §123“power-domain@10  ñò§456789“power-domain@11  í§:“power-domain@13  §;“power-domain@14  §<=>“power-domain@15  §?@ABCDEF“gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$•()' ®jobmmugpu  gpubus/G9„okay¾H·¤video-codec@fdea0400,rockchip,rk3568-vpuýê •‹®vdpu îï  aclkhclkÊI9 iommu@fdea0800,rockchip,rk3568-iommuýê@ •Š  aclkiface îï9 Ñ·Irga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ •Z óôõ aclkhclksclkX&$% Þcoreaxiahb9 video-codec@fdee0000,rockchip,rk3568-vepuýî •@ ýþ  aclkhclkÊJ9 iommu@fdee0800,rockchip,rk3568-iommuýî@ •? ýþ  aclkiface9 Ñ·Jmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ •d  ÁÂŽ� biuciuciu-driveciu-sampleêõðÑ€XëÞreset „disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ• ®macirqeth_wake_irq@ †‰‰ÇÃĉÈW stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refXì Þstmmaceth� K$L7MJ„okayT‰†y‡dsY@Soutput`N krgmii-id÷defaultíOPQRSmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22tN „†  –T·Nstmmac-axi-config¢¬¼·Krx-queues-configÌ·Lqueue0tx-queues-configâ·Mqueue0vop@fe040000 þ0þ@øvopgamma-lut •”( ÝÞßàá% aclkhclkdclk_vp0dclk_vp1dclk_vp2ÊU9 � „okay,rockchip,rk3568-vopTßàyports ·port@0 endpoint@2V·^port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? •” ÝÞ  aclkifaceÑ9 „okay·Udsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ •D pclk èdphyW9 ÞapbX�  „disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ •E pclk édphyX9 ÞapbX�  „disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  •-( æç“(Ú iahbisfrcecref÷default íYZ[9 q� y„okay\"]·ports port@0endpoint^·Vport@1endpoint_·Õqos@fe128000,rockchip,rk3568-qossysconþ€ ·-qos@fe138080,rockchip,rk3568-qossysconþ€€ ·<qos@fe138100,rockchip,rk3568-qossysconþ� ·=qos@fe138180,rockchip,rk3568-qossysconþ�€ ·>qos@fe148000,rockchip,rk3568-qossysconþ€ ·.qos@fe148080,rockchip,rk3568-qossysconþ€€ ·/qos@fe148100,rockchip,rk3568-qossysconþ� ·0qos@fe150000,rockchip,rk3568-qossysconþ ·:qos@fe158000,rockchip,rk3568-qossysconþ€ ·4qos@fe158100,rockchip,rk3568-qossysconþ� ·5qos@fe158180,rockchip,rk3568-qossysconþ�€ ·6qos@fe158200,rockchip,rk3568-qossysconþ‚ ·7qos@fe158280,rockchip,rk3568-qossysconþ‚€ ·8qos@fe158300,rockchip,rk3568-qossysconþƒ ·9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ·?qos@fe190280,rockchip,rk3568-qossysconþ€ ·Cqos@fe190300,rockchip,rk3568-qossysconþ ·Dqos@fe190380,rockchip,rk3568-qossysconþ€ ·Eqos@fe190400,rockchip,rk3568-qossysconþ ·Fqos@fe198000,rockchip,rk3568-qossysconþ€ ·;qos@fe1a8000,rockchip,rk3568-qossysconþ€ ·1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ·2qos@fe1a8100,rockchip,rk3568-qossysconþ� ·3dfi@fe230000,rockchip,rk3568-dfiþ# • 2`pcie@fe260000,rockchip,rk3568-pcie0À@þ&ôødbiapbconfig<•KJIHG®syspmcmsglegacyerr?( �‚ƒ„…$ aclk_mstaclk_slvaclk_dbipclkauxûpci”I`\aaaaj{Š™¨° pcie-phy9Tôôô ô à@X¡Þpipe  „disabledlegacy-interrupt-controller” •H·ammc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ •b  °±Š‹ biuciuciu-driveciu-sampleêõðÑ€XÔÞreset„okayºÄ Õ#Þ÷defaultíbcdeé÷f mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ •c  ²³Œ� biuciuciu-driveciu-sampleêõðÑ€XÖÞreset „disabledspi@fe300000 ,rockchip,sfcþ0@ •e xv clk_sfchclk_sfcíg÷default „disabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 •T{}d ëÂn6( |zy{} corebusaxiblocktimer„okayºõ ë ÷defaultíhijkrng@fe388000,rockchip,rk3568-rngþ8€@ po  coreahbXm„okayi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ •4T=AdFÏqFÏq ?C9 mclk_txmclk_rxhclkll txXPQ Þtx-mrx-m� y„okay· i2s@fe410000,rockchip,rk3568-i2s-tdmþA •5TEIdFÏqFÏq GK: mclk_txmclk_rxhclklll rxtxXRS Þtx-mrx-m� ÷default0ímnopqrstuvwxy„okay (·×i2s@fe420000,rockchip,rk3568-i2s-tdmþB •6TMdFÏq OO; mclk_txmclk_rxhclklll txrxXTÞtx-m� ÷defaultíyz{|y „disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC •7 SW< mclk_txmclk_rxhclklll txrxXUV Þtx-mrx-m� y „disabledpdm@fe440000,rockchip,rk3568-pdmþD •L ZY pdm_clkpdm_hclkll  rxí}~€�‚÷defaultXXÞpdm-my „disabledspdif@fe460000,rockchip,rk3568-spdifþF •f  mclkhclk _\ll tx÷defaultíƒy „disableddma-controller@fe530000,arm,pl330arm,primecellþS@•  C    apb_pclk Z·'dma-controller@fe550000,arm,pl330arm,primecellþU@• C    apb_pclk Z·li2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ •/ HG  i2cpclkí„÷default „okaygoodix@14,goodix,gt1151#•  e… s# ÷default톇 –# }…i2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ •0 JI  i2cpclkíˆ÷default  „disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ •1 LK  i2cpclkí‰÷default  „disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] •2 NM  i2cpclkíŠ÷default  „disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ •3 PO  i2cpclkí‹÷default  „disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` ••   tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa •g RQ spiclkapb_pclkl'' txrx÷default íŒ�Ž  „disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb •h TS spiclkapb_pclkl'' txrx÷default í��‘  „disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc •i VU spiclkapb_pclkl'' txrx÷default í’“”  „disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd •j XW spiclkapb_pclkl'' txrx÷default í•–—  „disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe •u  baudclkapb_pclkl''í˜÷defaultq~ „disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf •v #  baudclkapb_pclkl''í™÷defaultq~„okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg •w '$ baudclkapb_pclkl''íš÷defaultq~ „disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh •x +( baudclkapb_pclkl'' í›÷defaultq~ „disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi •y /, baudclkapb_pclkl' ' íœ÷defaultq~ „disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj •z 30 baudclkapb_pclkl' ' í�÷defaultq~ „disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk •{ 74 baudclkapb_pclkl''íž÷defaultq~ „disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl •| ;8 baudclkapb_pclkl''íŸ÷defaultq~ „disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm •} ?< baudclkapb_pclkl''í ÷defaultq~ „disabledthermal-zonescpu-thermal Šd  è ®¡tripscpu_alert0 ¾p ÊÐpassive·¢cpu_alert1 ¾$ø ÊÐpassivecpu_crit ¾s ÊÐ criticalcooling-mapsmap0 Õ¢0 Ú ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal Š  è ®¡tripsgpu-threshold ¾p ÊÐpassivegpu-target ¾$ø ÊÐpassive·£gpu-crit ¾s ÊÐ criticalcooling-mapsmap0 Õ£ Ú¤ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq •sTdf@ ®`  tsadcapb_pclkX�‚×�  és÷defaultsleepí¥ ¦ „okay  7·¡saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr •]  saradcapb_pclkX€ Þsaradc-apb R„okay d§pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkí¨÷defaultˆ „disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY  pwmpclkí©÷defaultˆ „disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  ZY  pwmpclkíª÷defaultˆ „disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY  pwmpclkí«÷defaultˆ „disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkí¬÷defaultˆ „disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\  pwmpclkí­÷defaultˆ „disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ]\  pwmpclkí®÷defaultˆ „disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\  pwmpclkí¯÷defaultˆ „disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkí°÷defaultˆ „disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_  pwmpclkí±÷defaultˆ „disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  `_  pwmpclkí²÷defaultˆ „disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_  pwmpclkí³÷defaultˆ „disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "}  refapbpipeT"dõáXÇÞphy p´ ‚µ ˜„okay·phy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~  refapbpipeT%dõáXÉÞphy p´ ‚¶ ˜ „disabled·phy@fe870000,rockchip,rk3568-csi-dphyþ‡ y pclk ˜XºÞapb�  „disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ…  refpclk z ˜9 ÞapbX» „disabled·Wmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ†  refpclk { ˜9 ÞapbX¼ „disabled·Xusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ  phyclkÚclk_usbphy0_480m •‡ £·-„okay·host-port ˜„okay ³¸·otg-port ˜„okay ³¹·usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹  phyclkÚclk_usbphy1_480m •ˆ £º-„okayhost-port ˜„okay ³¸·otg-port ˜„okay ³¸·pinctrl,rockchip,rk3568-pinctrl� 2` ·»gpio@fdd60000,rockchip,gpio-bankýÖ •! .  ¾ λ  Ú”·#gpio@fe740000,rockchip,gpio-bankþt •" cd ¾ λ  Ú”gpio@fe750000,rockchip,gpio-bankþu •# ef ¾ λ@  Ú”·Tgpio@fe760000,rockchip,gpio-bankþv •$ gh ¾ λ`  Ú”gpio@fe770000,rockchip,gpio-bankþw •% ij ¾ λ€  Ú”pcfg-pull-up æ·¾pcfg-pull-none ó·¼pcfg-pull-none-drv-level-1 ó ·Àpcfg-pull-none-drv-level-2 ó ·¿pcfg-pull-none-drv-level-3 ó ·Ãpcfg-pull-up-drv-level-1 æ ·Âpcfg-pull-up-drv-level-2 æ ·½pcfg-pull-none-smt ó ·Áacodecaudiopwmbt656bt1120camcan0can0m0-pins $ ¼ ¼·Ñcan1can1m0-pins $¼¼·Òcan2can2m0-pins $ ¼ ¼·Ócifclk32kclk32k-out0 $¼·cpuebcedpdpemmcemmc-bus8€ $ ½ ½½½½½½½·hemmc-clk $½·iemmc-cmd $½·jemmc-datastrobe $¼·keth0eth1flashfspifspi-pins` $¼¼¼¼¼¼·ggmac0gmac0-miim $¼¼·Ìgmac0-rx-bus20 $¼¼¼·Îgmac0-tx-bus20 $ ¿ ¿ ¼·Ígmac0-rgmii-clk $¼À·Ïgmac0-rgmii-bus@ $¼¼¿¿·Ðgmac1gmac1m1-miim $¼¼·Ogmac1m1-rx-bus20 $¼¼ ¼·Qgmac1m1-tx-bus20 $¿¿¼·Pgmac1m1-rgmii-clk $¼À·Rgmac1m1-rgmii-bus@ $¼¼¿¿·Sgpuhdmitxhdmitxm0-cec $¼·[hdmitx-scl $¼·Yhdmitx-sda $¼·Zi2c0i2c0-xfer $ Á Á·!i2c1i2c1-xfer $ Á Á·„i2c2i2c2m0-xfer $ ÁÁ·ˆi2c3i2c3m0-xfer $ÁÁ·‰i2c4i2c4m0-xfer $ Á Á·Ši2c5i2c5m0-xfer $ Á Á·‹i2s1i2s1m0-lrckrx $¼·pi2s1m0-lrcktx $¼·oi2s1m0-mclk $¼·%i2s1m0-sclkrx $¼·ni2s1m0-sclktx $¼·mi2s1m0-sdi0 $ ¼·qi2s1m0-sdi1 $ ¼·ri2s1m0-sdi2 $ ¼·si2s1m0-sdi3 $¼·ti2s1m0-sdo0 $¼·ui2s1m0-sdo1 $¼·vi2s1m0-sdo2 $ ¼·wi2s1m0-sdo3 $ ¼·xi2s2i2s2m0-lrcktx $¼·zi2s2m0-sclktx $¼·yi2s2m0-sdi $¼·{i2s2m0-sdo $¼·|i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk $¼·}pdmm0-clk1 $¼·~pdmm0-sdi0 $ ¼·pdmm0-sdi1 $ ¼·€pdmm0-sdi2 $ ¼·�pdmm0-sdi3 $¼·‚pmicpmic_int $¾·$pmupwm0pwm0m0-pins $¼·)pwm1pwm1m0-pins $¼·*pwm2pwm2m0-pins $¼·+pwm3pwm3-pins $¼·,pwm4pwm4-pins $¼·¨pwm5pwm5-pins $¼·©pwm6pwm6-pins $¼·ªpwm7pwm7-pins $¼·«pwm8pwm8m0-pins $ ¼·¬pwm9pwm9m0-pins $ ¼·­pwm10pwm10m0-pins $ ¼·®pwm11pwm11m0-pins $¼·¯pwm12pwm12m0-pins $¼·°pwm13pwm13m0-pins $¼·±pwm14pwm14m0-pins $¼·²pwm15pwm15m0-pins $¼·³refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ $½½½½·bsdmmc0-clk $½·csdmmc0-cmd $½·dsdmmc0-det $¾·esdmmc1sdmmc2spdifspdifm0-tx $¼·ƒspi0spi0m0-pins0 $ ¼¼¼·Žspi0m0-cs0 $¼·Œspi0m0-cs1 $¼·�spi1spi1m0-pins0 $ ¼¼¼·‘spi1m0-cs0 $¼·�spi1m0-cs1 $¼·�spi2spi2m0-pins0 $¼¼¼·”spi2m0-cs0 $¼·’spi2m0-cs1 $¼·“spi3spi3m0-pins0 $ ¼¼ ¼·—spi3m0-cs0 $¼·•spi3m0-cs1 $¼·–tsadctsadc-shutorg $¼·¥tsadc-pin $¼·¦uart0uart0-xfer $¾¾·(uart1uart1m0-xfer $ ¾ ¾·˜uart2uart2m0-xfer $¾¾·™uart3uart3m0-xfer $¾¾·šuart4uart4m0-xfer $¾¾·›uart5uart5m0-xfer $¾¾·œuart6uart6m0-xfer $¾¾·�uart7uart7m0-xfer $¾¾·žuart8uart8m0-xfer $¾¾·Ÿuart9uart9m0-xfer $¾¾· vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2displayvcc3v3_lcd0_n_en $¼·Ývcc3v3_lcd1_n_en $¼·Þledsled_work_en $¼·Ötouchscreentouch_int $ ¾·†touch_rst $¼·‡usbvcc5v0_usb_host_en $¼·Úvcc5v0_usb_otg_en $¼·Üsata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü –—˜ satapmaliverxoob •^ sata-phy'9 „disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconýÇ·Ôqos@fe190080,rockchip,rk3568-qossysconþ€ ·@qos@fe190100,rockchip,rk3568-qossysconþ ·Aqos@fe190200,rockchip,rk3568-qossysconþ ·Bsyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconýË€·Äphy@fe8c0000,rockchip,rk3568-pcie3-phyþŒ ˜ &'w refclk_mrefclk_npclkX¾Þphy 2Ä „disabled·Æpcie@fe270000,rockchip,rk3568-pcie ?( ˆ‰Š‹Œ$ aclk_mstaclk_slvaclk_dbipclkauxûpci<• Ÿž�œ®syspmcmsglegacyerr”I`\ÅÅÅÅj{Š™¨°Æ pcie-phy90À@@þ'òTòòò ò à@@@ødbiapbconfigX±Þpipe „disabledlegacy-interrupt-controller” •�·Åpcie@fe280000,rockchip,rk3568-pcie ?( ��‘’“$ aclk_mstaclk_slvaclk_dbipclkauxûpci<•¥¤£¢¡®syspmcmsglegacyerr”I`\ÇÇÇÇj{Š™¨ °Æ pcie-phy90À€@þ(ðTððð ð à€€@ødbiapbconfigXÁÞpipe „disabledlegacy-interrupt-controller” •¢·Çethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ*•®macirqeth_wake_irq@ ‚……¸´µ…¹W stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refX× Þstmmaceth� È$É7ÊJ„okayT…‚yƒdsY@Soutput`Ë krgmii-id÷defaultíÌÍÎÏÐmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22tN „†  –T·Ëstmmac-axi-config¢¬¼·Èrx-queues-configÌ·Équeue0tx-queues-configâ·Êqueue0can@fe570000,rockchip,rk3568v2-canfdþW • A@  baudpclkXUT Þcoreapb÷defaultíÑ „disabledcan@fe580000,rockchip,rk3568v2-canfdþX • CB  baudpclkXWV Þcoreapb÷defaultíÒ „disabledcan@fe590000,rockchip,rk3568v2-canfdþY • ED  baudpclkXYX Þcoreapb÷defaultíÓ „disabledphy@fe820000,rockchip,rk3568-naneng-combphyþ‚ |  refapbpipeTdõáXÅÞphy p´ ‚Ô ˜„okay·chosen Cserial2:1500000n8dc-12v,regulator-fixedºdc_12vÉÝï···Ùhdmi-con,hdmi-connectoraportendpointÕ·_leds ,gpio-ledsled-0 œ# Oheartbeat X ^heartbeat÷defaultíÖrk809-sound,simple-audio-cardQi2s :Analog RK809jsimple-audio-card,cpu‹×simple-audio-card,codec‹Øvcc3v3-sys,regulator-fixed ºvcc3v3_sysÉÝï2Z 2Z 4Ù·&vcc5v0-sys,regulator-fixed ºvcc5v0_sysÉÝïLK@LK@4Ù·"vcc5v0-usb,regulator-fixed ºvcc5v0_usbÉÝïLK@LK@4Ù·Ûvcc5v0-usb-host,regulator-fixed t ‡#÷defaultíÚºvcc5v0_usb_hostïLK@LK@4Û·¸vcc5v0-usb-otg,regulator-fixed t ‡#÷defaultíܺvcc5v0_usb_otgïLK@LK@4Û·¹vcc3v3-lcd0-n,regulator-fixedºvcc3v3_lcd0_nï2Z 2Z  t ‡#4&÷defaultíÝ·…regulator-state-mem?vcc3v3-lcd1-n,regulator-fixedºvcc3v3_lcd1_nï2Z 2Z  t ‡#4&÷defaultíÞregulator-state-mem? interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controller#sound-dai-cellsvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltrockchip,mic-in-differentialdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsAVDD28-supplyirq-gpiosVDDIO-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfstdout-pathfunctioncolorlinux,default-triggerenable-active-highgpio