Ð þíÚã8ÎH( ›Î ",pine64,quartz64-brockchip,rk35667Pine64 Quartz64 Model Baliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe010000ç/mmc@fe2b0000ì/mmc@fe310000ñ/mmc@fe2c0000cpus cpu@0öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@100öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@200öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² cpu@300öcpu,arm,cortex-a55 psci*>€K@]€j€w@‰€–§² l3-cache,cacheºÆ@M@_²opp-table-0,operating-points-v2Ô²opp-408000000ßQ– æ »  » Œ0ôœ@opp-600000000ß#ÃF æ »  » Œ0opp-816000000ß0£, æ »  » Œ0opp-1104000000ßAÍ´ æ »  » Œ0opp-1416000000ßTfr æ »  » Œ0opp-1608000000ß_Ø" æà˜à˜Œ0opp-1800000000ßkIÒ æ��Œ0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc‚" protocol@14(²opp-table-1,operating-points-v2²Dopp-200000000ß ëÂ æ øP øPB@opp-300000000ßá£ æ øP øPB@opp-400000000ßׄ æ øP øPB@opp-600000000ß#ÃF æ »  » B@opp-700000000ß)¹' æ~ð~ðB@opp-800000000ß/¯ æB@B@B@hdmi-sound,simple-audio-card5HDMILi2seokaysimple-audio-card,codec†simple-audio-card,cpu† pmu,arm,cortex-a55-pmu0�äåæç› psci ,arm,psci-1.0#smctimer,arm,armv8-timer0�   ®xin24m ,fixed-clockÅn6Õxin24m(²xin32k ,fixed-clockÅ€Õxin32kèòdefault(sram@10f000 ,mmio-sramð ðsram@0,arm,scmi-shmem²sata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@›œ�satapmaliverxoob �_ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€ ¡¢satapmaliverxoob �` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ �©¦§¥ref_clksuspend_clkbus_clkBotg Jutmi_wide4S”Zokay usb2-phys zhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ �ª©ª¨ref_clksuspend_clkbus_clkBhost usb2-phyusb3-phy Jutmi_wide4S•Zokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF � ˆ�®ýA¸(òusb@fd800000 ,generic-ehciý€ �‚½¾¼usbokayusb@fd840000 ,generic-ohciý„ �ƒ½¾¼usbokayusb@fd880000 ,generic-ehciýˆ �…¿À¼usb disabledusb@fd8c0000 ,generic-ohciýŒ �†¿À¼usb disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdý²_io-domains&,rockchip,rk3568-pmu-io-voltage-domainokayÒàîü &4Bsyscon@fdc50000ýÅ ,rockchip,rk3566-pipe-grfsyscon²±syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýƲ syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýȲ²syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýɲ³syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€²´syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€²·clock-controller@fdd00000,rockchip,rk3568-pmucruýÐ(P²clock-controller@fdd20000,rockchip,rk3568-cruýÒxin24m(P] m€G†Œ ë‚™ ²i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ �.- i2cpclkè!òdefault okayregulator@1c ,tcs,tcs4525¦Ãvdd_cpuÒ 5êŒ0ü+="²regulator-state-memHpmic@20,rockchip,rk809 #�]H‚–mclkHÕrk808-clkout1rk808-clkout2òdefaultè$%a‚“(¡&­&¹&Å&Ñ&Ý&é&õ&&²’regulatorsDCDC_REG1Ãvdd_log+Ò¡ ê™pqregulator-state-mem % » DCDC_REG2Ãvdd_gpu+Ò¡ ê™pq²Eregulator-state-memH% » DCDC_REG3Ãvcc_ddr+Aregulator-state-mem DCDC_REG4Ãvdd_npuÒ » ê™pAregulator-state-memHDCDC_REG5Ãvcc_1v8+Òw@êw@²regulator-state-mem %w@LDO_REG1Ãvdda0v9_image+Ò » ê » ²[regulator-state-mem % » LDO_REG2 Ãvdda_0v9+Ò » ê » regulator-state-mem % » LDO_REG3 Ãvdda0v9_pmu+Ò » ê » regulator-state-mem % » LDO_REG4 Ãvccio_acodec+Ò2Z ê2Z ²regulator-state-mem %2Z LDO_REG5 Ãvccio_sd+Òw@ê2Z ²regulator-state-mem %2Z LDO_REG6 Ãvcc3v3_pmu+Ò2Z ê2Z ²regulator-state-mem %2Z LDO_REG7 Ãvcca_1v8+Òw@êw@²¤regulator-state-mem %w@LDO_REG8 Ãvcca1v8_pmu+Òw@êw@²regulator-state-mem %w@LDO_REG9Ãvcca1v8_image+Òw@êw@²\regulator-state-mem %w@SWITCH_REG1+Ãvcc_3v3²SWITCH_REG2 Ãvcc3v3_sd²hserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ �t ,baudclkapb_pclkX''è(òdefault]j disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè)òdefaultt disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý× 0 pwmpclkè*òdefaultt disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 pwmpclkè+òdefaultt disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0 0 pwmpclkè,òdefaultt disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controller ²power-domain@7“-power-domain@8ÌÍ “./0power-domain@9 ÚÛÜ “123power-domain@10 ñò“456789power-domain@11 í“:power-domain@13 “;power-domain@14 “<=>power-domain@15“?@ABCgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$�()' šjobmmugpugpubus *D4okayªE²¡video-codec@fdea0400,rockchip,rk3568-vpuýê �‹švdpuîï aclkhclk¶F4 iommu@fdea0800,rockchip,rk3568-iommuýê@ �Š aclkifaceîï4 ½²Frga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rgaýë€ �ZóôõaclkhclksclkS&$% Êcoreaxiahb4 video-codec@fdee0000,rockchip,rk3568-vepuýî �@ýþ aclkhclk¶G4 iommu@fdee0800,rockchip,rk3568-iommuýî@ �?ýþ aclkiface4 ½²Gmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ �d ÁÂŽ�biuciuciu-driveciu-sampleÖáðÑ€SëÊreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ� šmacirqeth_wake_irq@†‰‰ÇÃĉÈWstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refSì Êstmmaceth™ ïHÿI#J6okay]‰‡†‚‡†K?inputLrgmiiUòdefaultèLMNOPQ `Rp †N † ›O¤$­Smdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22²Sstmmac-axi-config¸ÂÒ²Hrx-queues-configâ²Iqueue0tx-queues-configø²Jqueue0vop@fe040000 þ0þ@vopgamma-lut �”(ÝÞßàá%aclkhclkdclk_vp0dclk_vp1dclk_vp2¶T4 ™ okay,rockchip,rk3566-vop]ßà‚ports ²port@0 endpoint@2U²]port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? �”ÝÞ aclkiface½4 okay²Tdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �DpclkèdphyV4 ÊapbS™  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ �EpclkédphyW4 ÊapbS™  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  �-(æç“(Úiahbisfrcecrefòdefault èXYZ4 ]™ ‚okay([8\²ports port@0endpoint]²Uport@1endpoint^²Âqos@fe128000,rockchip,rk3568-qossysconþ€ ²-qos@fe138080,rockchip,rk3568-qossysconþ€€ ²<qos@fe138100,rockchip,rk3568-qossysconþ� ²=qos@fe138180,rockchip,rk3568-qossysconþ�€ ²>qos@fe148000,rockchip,rk3568-qossysconþ€ ².qos@fe148080,rockchip,rk3568-qossysconþ€€ ²/qos@fe148100,rockchip,rk3568-qossysconþ� ²0qos@fe150000,rockchip,rk3568-qossysconþ ²:qos@fe158000,rockchip,rk3568-qossysconþ€ ²4qos@fe158100,rockchip,rk3568-qossysconþ� ²5qos@fe158180,rockchip,rk3568-qossysconþ�€ ²6qos@fe158200,rockchip,rk3568-qossysconþ‚ ²7qos@fe158280,rockchip,rk3568-qossysconþ‚€ ²8qos@fe158300,rockchip,rk3568-qossysconþƒ ²9qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ ²?qos@fe190280,rockchip,rk3568-qossysconþ€ ²@qos@fe190300,rockchip,rk3568-qossysconþ ²Aqos@fe190380,rockchip,rk3568-qossysconþ€ ²Bqos@fe190400,rockchip,rk3568-qossysconþ ²Cqos@fe198000,rockchip,rk3568-qossysconþ€ ²;qos@fe1a8000,rockchip,rk3568-qossysconþ€ ²1qos@fe1a8080,rockchip,rk3568-qossysconþ€€ ²2qos@fe1a8100,rockchip,rk3568-qossysconþ� ²3dfi@fe230000,rockchip,rk3568-dfiþ# � H_pcie@fe260000,rockchip,rk3568-pcie0À@þ&ôdbiapbconfig<�KJIHGšsyspmcmsglegacyerrU(�‚ƒ„…$aclk_mstaclk_slvaclk_dbipclkauxöpci�_`r````€‘ ¯¾Æ pcie-phy4Tôôô ô à@S¡Êpipe okayòdefaultèa Ðb Üclegacy-interrupt-controller�ˆ �H²`mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ �b °±Š‹biuciuciu-driveciu-sampleÖáðÑ€SÔÊresetokayìö # òdefaultèdefg  (h 4mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ �c ²³Œ�biuciuciu-driveciu-sampleÖáðÑ€SÖÊresetokayìö A N di oòdefault èjkl (& 4spi@fe300000 ,rockchip,sfcþ0@ �exvclk_sfchclk_sfcèmòdefaultokay flash@0,jedec,spi-nor }n6 �  mmc@fe310000,rockchip,rk3568-dwcmshcþ1 �]{}m ëÂn6(|zy{}corebusaxiblocktimerokayì ± o ( 4rng@fe388000,rockchip,rk3568-rngþ8€@po coreahbSm disabledi2s@fe400000,rockchip,rk3568-i2s-tdmþ@ �4]=AmFÏqFÏq?C9mclk_txmclk_rxhclkXn ÀtxSPQ Êtx-mrx-m™ ‚okay² i2s@fe410000,rockchip,rk3568-i2s-tdmþA �5]EImFÏqFÏqGK:mclk_txmclk_rxhclkXnn ÀrxtxSRS Êtx-mrx-m™ òdefaultèopqr‚okay ʲÄi2s@fe420000,rockchip,rk3568-i2s-tdmþB �6]MmFÏqOO;mclk_txmclk_rxhclkXnn ÀtxrxSTÊtx-m™ òdefaultèstuv‚ disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC �7SW<mclk_txmclk_rxhclkXnn ÀtxrxSUV Êtx-mrx-m™ ‚ disabledpdm@fe440000,rockchip,rk3568-pdmþD �LZYpdm_clkpdm_hclkXn  Àrxèwxyz{|òdefaultSXÊpdm-m‚ disabledspdif@fe460000,rockchip,rk3568-spdifþF �f mclkhclk_\Xn Àtxòdefaultè}‚ disableddma-controller@fe530000,arm,pl330arm,primecellþS@�  å  apb_pclk ü²'dma-controller@fe550000,arm,pl330arm,primecellþU@� å  apb_pclk ü²ni2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ �/HG i2cpclkè~òdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ �0JI i2cpclkèòdefault okayi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ �1LK i2cpclkè€òdefault okayi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] �2NM i2cpclkè�òdefault okayi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ �3PO i2cpclkè‚òdefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` �• tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa �gRQspiclkapb_pclkX'' Àtxrxòdefault 胄…  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb �hTSspiclkapb_pclkX'' Àtxrxòdefault 膇ˆ  disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc �iVUspiclkapb_pclkX'' Àtxrxòdefault 艊‹  disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd �jXWspiclkapb_pclkX'' Àtxrxòdefault èŒ�Ž  disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe �ubaudclkapb_pclkX'' è��‘òdefault]jokay Àtxrx bluetooth,brcm,bcm4345c5’lpo #  +#  =#òdefault è“”• L& Xserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf �v# baudclkapb_pclkX''è–òdefault]jokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg �w'$baudclkapb_pclkX''è—òdefault]j disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh �x+(baudclkapb_pclkX'' è˜òdefault]j disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi �y/,baudclkapb_pclkX' ' è™òdefault]j disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj �z30baudclkapb_pclkX' ' èšòdefault]j disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk �{74baudclkapb_pclkX''è›òdefault]j disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl �|;8baudclkapb_pclkX''èœòdefault]j disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm �}?<baudclkapb_pclkX''è�òdefault]j disabledthermal-zonescpu-thermal ed {è ‰žtripscpu_alert0 ™p ¥Ðýpassive²Ÿcpu_alert1 ™$ø ¥Ðýpassivecpu_crit ™s ¥Ð ýcriticalcooling-mapsmap0 °Ÿ0 µ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal e {è ‰žtripsgpu-threshold ™p ¥Ðýpassivegpu-target ™$ø ¥Ðýpassive² gpu-crit ™s ¥Ð ýcriticalcooling-mapsmap0 °  µ¡ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq �s]mf@ ®`tsadcapb_pclkS�‚×™  Äsòdefaultsleepè¢ Û£ åokay û ²žsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr �]saradcapb_pclkS€ Êsaradc-apb -okay ?¤pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¥òdefaultt disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþnZY pwmpclkè¦òdefaultt disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY pwmpclkè§òdefaultt disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0ZY pwmpclkè¨òdefaultt disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkè©òdefaultt disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo]\ pwmpclkèªòdefaultt disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ pwmpclkè«òdefaultt disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0]\ pwmpclkè¬òdefaultt disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè­òdefaultt disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp`_ pwmpclkè®òdefaultt disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ pwmpclkè¯òdefaultt disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0`_ pwmpclkè°òdefaultt disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ"} refapbpipe]"mõáSÇÊphy K± ]² sokay²phy@fe840000,rockchip,rk3568-naneng-combphyþ„%~ refapbpipe]%mõáSÉÊphy K± ]³ sokay²phy@fe870000,rockchip,rk3568-csi-dphyþ‡ypclk sSºÊapb™  disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… refpclkz s4 ÊapbS» disabled²Vmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† refpclk{ s4 ÊapbS¼ disabled²Wusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠphyclkÕclk_usbphy0_480m �‡ ~´(okay²host-port sokayUµ²otg-port sokayU¶²usb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹phyclkÕclk_usbphy1_480m �ˆ ~·(okayhost-port s disabled²otg-port sokayUµ²pinctrl,rockchip,rk3568-pinctrl™ H_ ²¸gpio@fdd60000,rockchip,gpio-bankýÖ �!.  Ž ž¸  ªˆ�²#gpio@fe740000,rockchip,gpio-bankþt �"cd Ž ž¸  ªˆ�²bgpio@fe750000,rockchip,gpio-bankþu �#ef Ž ž¸@  ªˆ�gpio@fe760000,rockchip,gpio-bankþv �$gh Ž ž¸`  ªˆ�²Rgpio@fe770000,rockchip,gpio-bankþw �%ij Ž ž¸€  ªˆ�pcfg-pull-up ¶²»pcfg-pull-down òÁpcfg-pull-none Ò²¹pcfg-pull-none-drv-level-1 Ò ß²½pcfg-pull-none-drv-level-2 Ò ß²¼pcfg-pull-none-drv-level-3 Ò ß²Àpcfg-pull-up-drv-level-1 ¶ ß²¿pcfg-pull-up-drv-level-2 ¶ ß²ºpcfg-pull-none-smt Ò î²¾acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ¹²cpuebcedpdpemmceth0eth1flashfspifspi-pins` ¹¹¹¹¹¹²mgmac0gmac1gmac1m1-miim ¹¹²Lgmac1m1-clkinout ¹²Pgmac1m1-rx-bus20 ¹¹ ¹²Ngmac1m1-tx-bus20 ¼¼¹²Mgmac1m1-rgmii-clk ¹½²Ogmac1m1-rgmii-bus@ ¹¹¼¼²Qgpuhdmitxhdmitxm0-cec ¹²Zhdmitx-scl ¹²Xhdmitx-sda ¹²Yi2c0i2c0-xfer  ¾ ¾²!i2c1i2c1-xfer  ¾ ¾²~i2c2i2c2m1-xfer  ¾ ¾²i2c3i2c3m1-xfer  ¾¾²€i2c4i2c4m0-xfer  ¾ ¾²�i2c5i2c5m0-xfer  ¾ ¾²‚i2s1i2s1m0-lrcktx ¹²pi2s1m0-mclk ¹²%i2s1m0-sclktx ¹²oi2s1m0-sdi0  ¹²qi2s1m0-sdo0 ¹²ri2s2i2s2m0-lrcktx ¹²ti2s2m0-sclktx ¹²si2s2m0-sdi ¹²ui2s2m0-sdo ¹²vi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ¹²wpdmm0-clk1 ¹²xpdmm0-sdi0  ¹²ypdmm0-sdi1  ¹²zpdmm0-sdi2  ¹²{pdmm0-sdi3 ¹²|pmicpmic_int »²$pmupwm0pwm0m0-pins ¹²)pwm1pwm1m0-pins ¹²*pwm2pwm2m0-pins ¹²+pwm3pwm3-pins ¹²,pwm4pwm4-pins ¹²¥pwm5pwm5-pins ¹²¦pwm6pwm6-pins ¹²§pwm7pwm7-pins ¹²¨pwm8pwm8m0-pins  ¹²©pwm9pwm9m0-pins  ¹²ªpwm10pwm10m0-pins  ¹²«pwm11pwm11m0-pins ¹²¬pwm12pwm12m0-pins ¹²­pwm13pwm13m0-pins ¹²®pwm14pwm14m0-pins ¹²¯pwm15pwm15m0-pins ¹²°refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ºººº²dsdmmc0-clk º²esdmmc0-cmd º²fsdmmc0-det »²gsdmmc1sdmmc1-bus4@ ºººº²jsdmmc1-clk º²lsdmmc1-cmd º²ksdmmc2spdifspdifm0-tx ¹²}spi0spi0m0-pins0  ¹¹¹²…spi0m0-cs0 ¹²ƒspi0m0-cs1 ¹²„spi1spi1m0-pins0  ¹¹¹²ˆspi1m0-cs0 ¹²†spi1m0-cs1 ¹²‡spi2spi2m0-pins0 ¹¹¹²‹spi2m0-cs0 ¹²‰spi2m0-cs1 ¹²Šspi3spi3m0-pins0  ¹¹ ¹²Žspi3m0-cs0 ¹²Œspi3m0-cs1 ¹²�tsadctsadc-shutorg ¹²¢tsadc-pin ¹²£uart0uart0-xfer »»²(uart1uart1m0-xfer  » »²�uart1m0-ctsn ¹²�uart1m0-rtsn  ¹²‘uart2uart2m0-xfer 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Ãvcc3v3_sysÒ2Z ê2Z ="²&vcc5v0-usb30-host-regulator,regulator-fixedÃvcc5v0_usb30_host ˆ k#òdefaultèÈÒLK@êLK@="²µvcc5v0-usb-otg-regulator,regulator-fixedÃvcc5v0_usb_otg ˆ k#òdefaultèÉÒLK@êLK@="²¶ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supplyregulator-off-in-suspendrockchip,system-power-controller#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-on-in-suspendregulator-suspend-microvoltregulator-initial-modedmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlesnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr50vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablespi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathlabeldefault-statelinux,default-triggerretain-state-suspendedpost-power-on-delay-mspower-off-delay-usenable-active-high