Ð þínž8gˆ(gProckchip,r88rockchip,rk3368 + 7Rockchip R88aliases=/pinctrl/gpio@ff750000C/pinctrl/gpio@ff780000I/pinctrl/gpio@ff790000O/pinctrl/gpio@ff7a0000U/i2c@ff650000Z/i2c@ff660000_/i2c@ff140000d/i2c@ff150000i/i2c@ff160000n/i2c@ff170000s/serial@ff180000{/serial@ff190000ƒ/serial@ff690000‹/serial@ff1b0000“/serial@ff1c0000›/spi@ff110000 /spi@ff120000¥/spi@ff130000ª/ethernet@ff290000´/mmc@ff0d0000¹/mmc@ff0f0000cpus+cpu-mapcluster0core0¾core1¾core2¾core3¾cluster1core0¾core1¾core2¾core3¾ cpu@0Âcpuarm,cortex-a53ÎÒpsciàïcpu@1Âcpuarm,cortex-a53ÎÒpsciàïcpu@2Âcpuarm,cortex-a53ÎÒpsciàïcpu@3Âcpuarm,cortex-a53ÎÒpsciàï cpu@100Âcpuarm,cortex-a53ÎÒpsciàïcpu@101Âcpuarm,cortex-a53ÎÒpsciàïcpu@102Âcpuarm,cortex-a53ÎÒpsciàïcpu@103Âcpuarm,cortex-a53ÎÒpsciàïarm-pmuarm,cortex-a53-pmu`÷pqrstuvw  psci arm,psci-0.2Ùsmctimerarm,armv8-timer0÷ ÿÿ ÿ ÿoscillator fixed-clockn6%xin24m8ïDmmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÎÿ @EðÑ€ S È D r vZbiuciuciu-driveciu-samplef ÷ q €xreset „disabledmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÎÿ @EðÑ€ S É E s wZbiuciuciu-driveciu-samplef ÷!q �xreset„okay‹ E› ²¼ÍÚð û default  !-mmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÎÿ@EðÑ€ S Ë G u yZbiuciuciu-driveciu-samplef ÷#q ƒxreset„okay²:ðû default saradc@ff100000rockchip,saradcÎÿ ÷$LS I [Zsaradcapb_pclkq W xsaradc-apb„okay^spi@ff110000(rockchip,rk3368-spirockchip,rk3066-spiÎÿS A RZspiclkapb_pclk ÷, default+ „disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spiÎÿS B SZspiclkapb_pclk ÷- default+ „disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spiÎÿS C TZspiclkapb_pclk ÷) default !+ „disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ ÷>+Zi2cS N default" „disabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ ÷?+Zi2cS O default# „disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ ÷@+Zi2cS P default$ „disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2cÎÿ ÷A+Zi2cS Q default% „disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿn6S M UZbaudclkapb_pclk ÷7jt „disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿn6S N VZbaudclkapb_pclk ÷8jt „disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿn6S P XZbaudclkapb_pclk ÷:jt „disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartÎÿn6S Q YZbaudclkapb_pclk ÷;jt „disableddma-controller@ff250000arm,pl330arm,primecellÎÿ%@÷�Œ§S à Zapb_pclkthermal-zonescpu-thermal¾dÔˆâ&tripscpu_alert0ò$øþÐÉpassiveï'cpu_alert1ò8€þÐÉpassiveï(cpu_critòsþÐ Écriticalcooling-mapsmap0 '0ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1 (0ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal¾dÔˆâ&tripsgpu_alert0ò8€þÐÉpassiveï)gpu_critòÁ8þÐ Écriticalcooling-mapsmap0 )0ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3368-tsadcÎÿ( ÷%S H ZZtsadcapb_pclkq Ÿ xtsadc-apb initdefaultsleep*+'*1Gs„okay^uï&ethernet@ff290000rockchip,rk3368-gmacÎÿ) ÷�macirq ,8S  f g c € Å ]MZstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac„okay­-¸rmiiÁoutput Î. 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„disabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdÎÿspower-controller!rockchip,rk3368-power-controller(+ïHpower-domain@12Î ðS Ê Í Ì È Æ Ç ¾ Ô Õ Ö Ù Ñ Û c h g n o r s f d d h i l k j n m$<789:;<=>?(power-domain@14Î S Ð Ü o p <@AB(power-domain@16ÎS Á À @<C(syscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdÎÿs€ïIio-domains&rockchip,rk3368-pmu-io-voltage-domain„okayCNreboot-modesyscon-reboot-modeY`RBÃlRBÃzRBà ŠRBÃclock-controller@ff760000rockchip,rk3368-cruÎÿvSDZxin24m ,8–ï syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdÎÿwï,io-domains"rockchip,rk3368-io-voltage-domain„okay£°¾Îwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdtÎÿ€S p ÷O„okaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timerÎÿ�  ÷BS a U Zpclktimerspdif@ff880000rockchip,rk3368-spdifÎÿˆ ÷6S S Ð ZmclkhclkÚEßtx defaultFé „disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2sÎÿ‰ ÷(Zi2s_clki2s_hclkS T ÎÚEEßtxrxé „disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2sÎÿ‰€ ÷5Zi2s_clki2s_hclkS R ÏÚEEßtxrx defaultGé „disablediommu@ff900800rockchip,iommuÎÿ� ÷S Ê Ô ZaclkifaceúH  „disablediommu@ff914000rockchip,iommu Îÿ‘@ÿ‘P ÷S Í Õ ZaclkifaceúH  „disablediommu@ff930300rockchip,iommuÎÿ“ ÷S Æ Ñ ZaclkifaceúH  „disablediommu@ff9a0440rockchip,iommu Îÿš@@ÿš€@ ÷ S Ð Ü Zaclkiface „disablediommu@ff9a0800rockchip,iommuÎÿš÷  S Ð Ü Zaclkiface „disabledqos@ffad0000rockchip,rk3368-qossysconÎÿ­ ï7qos@ffad0080rockchip,rk3368-qossysconÎÿ­€ ï8qos@ffad0100rockchip,rk3368-qossysconÎÿ­ ï9qos@ffad0180rockchip,rk3368-qossysconÎÿ­€ ï:qos@ffad0200rockchip,rk3368-qossysconÎÿ­ ï;qos@ffad0280rockchip,rk3368-qossysconÎÿ­€ ï<qos@ffad0300rockchip,rk3368-qossysconÎÿ­ ï=qos@ffad0380rockchip,rk3368-qossysconÎÿ­€ ï>qos@ffad0400rockchip,rk3368-qossysconÎÿ­ ï?qos@ffae0000rockchip,rk3368-qossysconÎÿ® ï@qos@ffae0100rockchip,rk3368-qossysconÎÿ® ïAqos@ffae0180rockchip,rk3368-qossysconÎÿ®€ ïBqos@ffaf0000rockchip,rk3368-qossysconÎÿ¯ ïCefuse@ffb00000rockchip,rk3368-efuseÎÿ° +S q Zpclk_efusecpu-leakage@17Îtemp-adjust@1fÎinterrupt-controller@ffb71000 arm,gic-4000E@Îÿ·ÿ· ÿ·@ ÿ·`  ÷ ÿïpinctrlrockchip,rk3368-pinctrl ,VI+cgpio@ff750000rockchip,gpio-bankÎÿuS @ ÷Qjz0EïRgpio@ff780000rockchip,gpio-bankÎÿxS A ÷Rjz0Egpio@ff790000rockchip,gpio-bankÎÿyS B ÷Sjz0EïPgpio@ff7a0000rockchip,gpio-bankÎÿzS C ÷Tjz0Eï.pcfg-pull-up†ïLpcfg-pull-down“pcfg-pull-none¢ïMpcfg-pull-none-12ma¢¯ ïNemmcemmc-clk¾Jïemmc-cmd¾Kïemmc-pwr¾Lemmc-bus1¾Lemmc-bus4@¾LLLLemmc-bus8€¾KKKKKKKKïemmc-reset¾MïOgmacrgmii-pinsð¾MMMN N NNN NMMMMMMrmii-pins ¾MMMN N NMMMMï/i2c0i2c0-xfer ¾MMï0i2c1i2c1-xfer ¾MMï2i2c2i2c2-xfer ¾ MMï"i2c3i2c3-xfer ¾MMï#i2c4i2c4-xfer ¾MMï$i2c5i2c5-xfer ¾MMï%i2si2s-8ch-bus�¾ M MMMMMMMMïGpwm0pwm0-pin¾Mï3pwm1pwm1-pin¾Mï4pwm3pwm3-pin¾Mï5sdio0sdio0-bus1¾Lsdio0-bus4@¾LLLLïsdio0-cmd¾Lï sdio0-clk¾Mï sdio0-cd¾Lsdio0-wp¾Lsdio0-pwr¾Lsdio0-bkpwr¾Lsdio0-int¾Lsdmmcsdmmc-clk¾ Msdmmc-cmd¾ Lsdmmc-cd¾ Lsdmmc-bus1¾Lsdmmc-bus4@¾LLLLspdifspdif-tx¾MïFspi0spi0-clk¾Lïspi0-cs0¾Lïspi0-cs1¾Lspi0-tx¾Lïspi0-rx¾Lïspi1spi1-clk¾Lïspi1-cs0¾Lïspi1-cs1¾Lspi1-rx¾Lïspi1-tx¾Lïspi2spi2-clk¾ Lïspi2-cs0¾ Lï!spi2-rx¾ Lï spi2-tx¾ Lïtsadcotp-pin¾Mï*otp-out¾Mï+uart0uart0-xfer ¾LMuart0-cts¾Muart0-rts¾Muart1uart1-xfer ¾LMuart1-cts¾Muart1-rts¾Muart2uart2-xfer ¾LMï6uart3uart3-xfer ¾LMuart3-cts¾Muart3-rts¾Muart4uart4-xfer ¾LMuart4-cts¾Muart4-rts¾Mpcfg-pull-none-drv-8ma¢¯ïJpcfg-pull-up-drv-8ma†¯ïKirir-int¾LïTkeyspwr-key¾LïQledsstby-pwren¾ Mled-ctl¾MïSsdiowifi-reg-on¾MïWbt-rst¾MïVusbhost-vbus-drv¾MïXchosenÌserial2:115200n8memory@0ÂmemoryÎ@emmc-pwrseqmmc-pwrseq-emmcO default ØPïgpio-keys gpio-keys defaultQkey-powerä ÞR òGPIO Powerøtgpio-leds gpio-ledsled-0 Þ.òr88:green:led defaultSir-receivergpio-ir-receiver Þ. defaultTsdio-pwrseqmmc-pwrseq-simpleSU Zext_clock defaultVWØ..ï vcc18-regulatorregulator-fixedpvcc_18›w@³w@àô1ïvcc-host-regulatorregulator-fixed ÙR defaultX pvcc_hostàô1vcc-io-regulatorregulator-fixedpvcc_io›2Z ³2Z àô1ïvcc-lan-regulatorregulator-fixedpvcc_lan›2Z ³2Z àôï-vcc-sys-regulatorregulator-fixedpvcc_sys›LK@³LK@àôï1vccio-wl-regulatorregulator-fixed pvccio_wl›2Z ³2Z àôïvdd-10-regulatorregulator-fixedpvdd_10›B@³B@àô1 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusassigned-clocksassigned-clock-parentsbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeed#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qospmu-supplyvop-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsaudio-supplygpio30-supplygpio1830-supplywifi-supplydmasdma-names#sound-dai-cellspower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codeenable-active-high