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„disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2sÎÿ‰€ ÷5Zi2s_clki2s_hclkS R ÏhGGmtxrx¸defaultÆIw „disablediommu@ff900800rockchip,iommuÎÿ� ÷S Ê Ô ZaclkifaceˆJ – „disablediommu@ff914000rockchip,iommu Îÿ‘@ÿ‘P ÷S Í Õ Zaclkiface–ˆJ £ „disablediommu@ff930300rockchip,iommuÎÿ“ ÷S Æ Ñ ZaclkifaceˆJ – „disablediommu@ff9a0440rockchip,iommu Îÿš@@ÿš€@ ÷ S Ð Ü Zaclkiface– „disablediommu@ff9a0800rockchip,iommuÎÿš÷  S Ð Ü Zaclkiface– „disabledqos@ffad0000rockchip,rk3368-qossysconÎÿ­ ï9qos@ffad0080rockchip,rk3368-qossysconÎÿ­€ ï:qos@ffad0100rockchip,rk3368-qossysconÎÿ­ ï;qos@ffad0180rockchip,rk3368-qossysconÎÿ­€ ï<qos@ffad0200rockchip,rk3368-qossysconÎÿ­ ï=qos@ffad0280rockchip,rk3368-qossysconÎÿ­€ ï>qos@ffad0300rockchip,rk3368-qossysconÎÿ­ ï?qos@ffad0380rockchip,rk3368-qossysconÎÿ­€ ï@qos@ffad0400rockchip,rk3368-qossysconÎÿ­ ïAqos@ffae0000rockchip,rk3368-qossysconÎÿ® ïBqos@ffae0100rockchip,rk3368-qossysconÎÿ® ïCqos@ffae0180rockchip,rk3368-qossysconÎÿ®€ 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sdmmc-bus1LMsdmmc-bus4@LMMMMïspdifspdif-txLOïHspi0spi0-clkLNïspi0-cs0LNïspi0-cs1LNspi0-txLNïspi0-rxLNïspi1spi1-clkLNïspi1-cs0LNïspi1-cs1LNspi1-rxLNïspi1-txLNïspi2spi2-clkL Nïspi2-cs0L Nï!spi2-rxL Nï spi2-txL Nïtsadcotp-pinLOï+otp-outLOï,uart0uart0-xfer LNOuart0-ctsLOuart0-rtsLOuart1uart1-xfer LNOuart1-ctsLOuart1-rtsLOuart2uart2-xfer LNOï8uart3uart3-xfer LNOuart3-ctsLOuart3-rtsLOuart4uart4-xfer LNOï&uart4-ctsLOuart4-rtsLOpcfg-pull-none-drv-8ma0=ïLpcfg-pull-up-drv-8ma=ïMkeyspwr-keyLQïTledsstby-pwrenL OïWled-ctlLOïVusbhost-vbus-drvLOïXchosenZserial2:115200n8memory@0Âmemory΀emmc-pwrseqmmc-pwrseq-emmcÆR¸default fSïexternal-gmac-clock fixed-clock8sY@ %ext_gmacï.gpio-keys gpio-keys¸defaultÆTkey-powerr lU €GPIO Power†tgpio-leds gpio-ledsled-0 l1€orion:red:led¸defaultÆV‘onled-1 lU €orion:blue:led¸defaultÆW‘offvcc18-regulatorregulator-fixedKvcc_18vw@Žw@»Ïá3ïvcc-host-regulatorregulator-fixed ´U¸defaultÆX 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compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusbus-widthcap-sd-highspeedcard-detect-delaypinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-pwrseqmmc-hs200-1_2vmmc-hs200-1_8vnon-removable#io-channel-cellsvref-supplyreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-tempinterrupt-namesrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-enable-ramp-delayregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onvin-supply#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cellspower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathreset-gpioswakeup-sourcelabellinux,codedefault-state