Ð þíqì8kL( k,rockchip,rk3368-evb-act8846rockchip,rk3368 +&7Rockchip RK3368 EVB with ACT8846 pmicaliases=/pinctrl/gpio@ff750000C/pinctrl/gpio@ff780000I/pinctrl/gpio@ff790000O/pinctrl/gpio@ff7a0000U/i2c@ff650000Z/i2c@ff660000_/i2c@ff140000d/i2c@ff150000i/i2c@ff160000n/i2c@ff170000s/serial@ff180000{/serial@ff190000ƒ/serial@ff690000‹/serial@ff1b0000“/serial@ff1c0000›/spi@ff110000 /spi@ff120000¥/spi@ff130000ª/ethernet@ff290000´/mmc@ff0f0000cpus+cpu-mapcluster0core0¹core1¹core2¹core3¹cluster1core0¹core1¹core2¹core3¹ cpu@0½cpuarm,cortex-a53ÉÍpsciÛêcpu@1½cpuarm,cortex-a53ÉÍpsciÛêcpu@2½cpuarm,cortex-a53ÉÍpsciÛêcpu@3½cpuarm,cortex-a53ÉÍpsciÛê cpu@100½cpuarm,cortex-a53ÉÍpsciÛêcpu@101½cpuarm,cortex-a53ÉÍpsciÛêcpu@102½cpuarm,cortex-a53ÉÍpsciÛêcpu@103½cpuarm,cortex-a53ÉÍpsciÛêarm-pmuarm,cortex-a53-pmu`òpqrstuvw ý psci arm,psci-0.2Ôsmctimerarm,armv8-timer0ò ÿÿ ÿ ÿoscillator fixed-clockn6 xin24m3ê?mmc@ff0c00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÉÿ @@ðÑ€ N È D r vUbiuciuciu-driveciu-samplea ò l €sreset disabledmmc@ff0d00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÉÿ @@ðÑ€ N É E s wUbiuciuciu-driveciu-samplea ò!l �sreset disabledmmc@ff0f00000rockchip,rk3368-dw-mshcrockchip,rk3288-dw-mshcÉÿ@@ðÑ€ N Ë G u yUbiuciuciu-driveciu-samplea ò#l ƒsresetokay†�¢ ­»default É saradc@ff100000rockchip,saradcÉÿ ò$ÓN I [Usaradcapb_pclkl W ssaradc-apb disabledspi@ff110000(rockchip,rk3368-spirockchip,rk3066-spiÉÿN A RUspiclkapb_pclk ò,»defaultÉ+ disabledspi@ff120000(rockchip,rk3368-spirockchip,rk3066-spiÉÿN B SUspiclkapb_pclk ò-»defaultÉ+ disabledspi@ff130000(rockchip,rk3368-spirockchip,rk3066-spiÉÿN C TUspiclkapb_pclk ò)»defaultÉ+ disabledi2c@ff140000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿ ò>+Ui2cN N»defaultÉ disabledi2c@ff150000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿ ò?+Ui2cN O»defaultÉ disabledi2c@ff160000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿ ò@+Ui2cN P»defaultÉ disabledi2c@ff170000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿ òA+Ui2cN Q»defaultÉ disabledserial@ff180000&rockchip,rk3368-uartsnps,dw-apb-uartÉÿn6N M UUbaudclkapb_pclk ò7åï disabledserial@ff190000&rockchip,rk3368-uartsnps,dw-apb-uartÉÿn6N N VUbaudclkapb_pclk ò8åï disabledserial@ff1b0000&rockchip,rk3368-uartsnps,dw-apb-uartÉÿn6N P XUbaudclkapb_pclk ò:åï disabledserial@ff1c0000&rockchip,rk3368-uartsnps,dw-apb-uartÉÿn6N Q YUbaudclkapb_pclk ò;åï disableddma-controller@ff250000arm,pl330arm,primecellÉÿ%@òü"N à Uapb_pclkthermal-zonescpu-thermal9dOˆ]tripscpu_alert0m$øyÐÄpassiveê cpu_alert1m8€yÐÄpassiveê!cpu_critmsyÐ Äcriticalcooling-mapsmap0„ 0‰ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿmap1„!0‰ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal9dOˆ]tripsgpu_alert0m8€yÐÄpassiveê"gpu_critmÁ8yÐ Äcriticalcooling-mapsmap0„"0‰ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿtsadc@ff280000rockchip,rk3368-tsadcÉÿ( ò%N H ZUtsadcapb_pclkl Ÿ stsadc-apb»initdefaultsleepÉ#˜$¢#¬ÂsokayÙðêethernet@ff290000rockchip,rk3368-gmacÉÿ) ò macirq%8N  f g c € Å ]MUstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macokay(&3rmiiP*syr828@41silergy,syr828ÉAÎëvdd_gpuú øP™p*P*act8846@5aactive-semi,act8846ÉZokay[*f*q*|*‡+“*Ÿ,regulatorsREG1ëVCC_DDRúO€O€*REG2ëVCC_IOú2Z 2Z *ê+REG3ëVDD_LOGú ®`ã`*REG4ëVCC_20ú„€„€*ê,REG5 ëVCCIO_SDúw@2Z *REG6 ëVDD10_LCDúB@B@*REG7 ëVCCA_CODECú2Z 2Z *REG8ëVCCA_TPú2Z 2Z *REG9 ëVCCIO_PMUú2Z 2Z *REG10ëVDD_10úB@B@*REG11ëVCC_18úw@w@*REG12 ëVCC18_LCDúw@w@*i2c@ff660000(rockchip,rk3368-i2crockchip,rk3288-i2cÉÿf ò=+Ui2cN M»defaultÉ- disabledpwm@ff680000(rockchip,rk3368-pwmrockchip,rk3288-pwmÉÿh«»defaultÉ.N _okayêLpwm@ff680010(rockchip,rk3368-pwmrockchip,rk3288-pwmÉÿh«»defaultÉ/N _ disabledpwm@ff680020(rockchip,rk3368-pwmrockchip,rk3288-pwmÉÿh «N _ disabledpwm@ff680030(rockchip,rk3368-pwmrockchip,rk3288-pwmÉÿh0«»defaultÉ0N _ disabledserial@ff690000&rockchip,rk3368-uartsnps,dw-apb-uartÉÿiN O WUbaudclkapb_pclk ò9»defaultÉ1åïokaymbox@ff6b0000rockchip,rk3368-mailboxÉÿk0ò’“”•N E Upclk_mailbox¶ disabledpower-management@ff730000&rockchip,rk3368-pmusysconsimple-mfdÉÿspower-controller!rockchip,rk3368-power-controllerÂ+êCpower-domain@12É ðN Ê Í Ì È Æ Ç ¾ Ô Õ Ö Ù Ñ Û c h g n o r s f d d h i l k j n m$Ö23456789:Âpower-domain@14É N Ð Ü o p Ö;<=Âpower-domain@16ÉN Á À @Ö>Âsyscon@ff738000)rockchip,rk3368-pmugrfsysconsimple-mfdÉÿs€êDio-domains&rockchip,rk3368-pmu-io-voltage-domain disabledreboot-modesyscon-reboot-modeÝäRBÃðRBÃþRBà RBÃclock-controller@ff760000rockchip,rk3368-cruÉÿvN?Uxin24m%3ê syscon@ff770000&rockchip,rk3368-grfsysconsimple-mfdÉÿwê%io-domains"rockchip,rk3368-io-voltage-domain disabledwatchdog@ff800000 rockchip,rk3368-wdtsnps,dw-wdtÉÿ€N p òOokaytimer@ff810000,rockchip,rk3368-timerrockchip,rk3288-timerÉÿ�  òBN a U Upclktimerspdif@ff880000rockchip,rk3368-spdifÉÿˆ ò6N S Ð Umclkhclk'@,tx»defaultÉA6 disabledi2s-2ch@ff890000(rockchip,rk3368-i2srockchip,rk3066-i2sÉÿ‰ ò(Ui2s_clki2s_hclkN T Î'@@,txrx6 disabledi2s-8ch@ff898000(rockchip,rk3368-i2srockchip,rk3066-i2sÉÿ‰€ ò5Ui2s_clki2s_hclkN R Ï'@@,txrx»defaultÉB6 disablediommu@ff900800rockchip,iommuÉÿ� òN Ê Ô UaclkifaceGC U disablediommu@ff914000rockchip,iommu Éÿ‘@ÿ‘P òN Í Õ UaclkifaceUGC b disablediommu@ff930300rockchip,iommuÉÿ“ òN Æ Ñ UaclkifaceGC U disablediommu@ff9a0440rockchip,iommu Éÿš@@ÿš€@ ò N Ð Ü UaclkifaceU disablediommu@ff9a0800rockchip,iommuÉÿšò  N Ð Ü UaclkifaceU disabledqos@ffad0000rockchip,rk3368-qossysconÉÿ­ ê2qos@ffad0080rockchip,rk3368-qossysconÉÿ­€ ê3qos@ffad0100rockchip,rk3368-qossysconÉÿ­ ê4qos@ffad0180rockchip,rk3368-qossysconÉÿ­€ ê5qos@ffad0200rockchip,rk3368-qossysconÉÿ­ ê6qos@ffad0280rockchip,rk3368-qossysconÉÿ­€ ê7qos@ffad0300rockchip,rk3368-qossysconÉÿ­ ê8qos@ffad0380rockchip,rk3368-qossysconÉÿ­€ ê9qos@ffad0400rockchip,rk3368-qossysconÉÿ­ ê:qos@ffae0000rockchip,rk3368-qossysconÉÿ® ê;qos@ffae0100rockchip,rk3368-qossysconÉÿ® ê<qos@ffae0180rockchip,rk3368-qossysconÉÿ®€ ê=qos@ffaf0000rockchip,rk3368-qossysconÉÿ¯ ê>efuse@ffb00000rockchip,rk3368-efuseÉÿ° +N q Upclk_efusecpu-leakage@17Étemp-adjust@1fÉinterrupt-controller@ffb71000 arm,gic-400}’@Éÿ·ÿ· ÿ·@ ÿ·`  ò ÿêpinctrlrockchip,rk3368-pinctrl%£D+°gpio@ff750000rockchip,gpio-bankÉÿuN @ òQ·Ç}’êJgpio@ff780000rockchip,gpio-bankÉÿxN A òR·Ç}’gpio@ff790000rockchip,gpio-bankÉÿyN B òS·Ç}’êNgpio@ff7a0000rockchip,gpio-bankÉÿzN C òT·Ç}’ê'pcfg-pull-upÓêGpcfg-pull-downàpcfg-pull-noneïêHpcfg-pull-none-12maïü êIemmcemmc-clk Eê emmc-cmd Fê emmc-pwr Gemmc-bus1 Gemmc-bus4@ GGGGemmc-bus8€ FFFFFFFFêemmc-reset HêMgmacrgmii-pinsð HHHI I III IHHHHHHrmii-pins  HHHI I IHHHHê(i2c0i2c0-xfer  HHê)i2c1i2c1-xfer  HHê-i2c2i2c2-xfer  HHêi2c3i2c3-xfer  HHêi2c4i2c4-xfer  HHêi2c5i2c5-xfer  HHêi2si2s-8ch-bus�  H HHHHHHHHêBpwm0pwm0-pin Hê.pwm1pwm1-pin Hê/pwm3pwm3-pin Hê0sdio0sdio0-bus1 Gsdio0-bus4@ GGGGsdio0-cmd Gsdio0-clk Hsdio0-cd Gsdio0-wp Gsdio0-pwr Gsdio0-bkpwr Gsdio0-int Gsdmmcsdmmc-clk  Hsdmmc-cmd  Gsdmmc-cd  Gsdmmc-bus1 Gsdmmc-bus4@ GGGGspdifspdif-tx HêAspi0spi0-clk Gêspi0-cs0 Gêspi0-cs1 Gspi0-tx Gêspi0-rx Gêspi1spi1-clk Gêspi1-cs0 Gêspi1-cs1 Gspi1-rx Gêspi1-tx Gêspi2spi2-clk Gêspi2-cs0 Gêspi2-rx Gêspi2-tx Gêtsadcotp-pin Hê#otp-out Hê$uart0uart0-xfer  GHuart0-cts Huart0-rts Huart1uart1-xfer  GHuart1-cts Huart1-rts Huart2uart2-xfer  GHê1uart3uart3-xfer  GHuart3-cts Huart3-rts Huart4uart4-xfer  GHuart4-cts Huart4-rts Hpcfg-pull-none-drv-8maïüêEpcfg-pull-up-drv-8maÓüêFbacklightbl-en HêKkeyspwr-key GêOpmicpmic-int Gsdiowifi-reg-on Hbt-rst Husbhost-vbus-drv HêPchosenserial2:115200n8memory@0½memoryÉ@backlightpwm-backlight%  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€�‚ƒ„…†‡ˆ‰Š‹Œ�Ž��‘’“”•–—˜™š›œ�žŸ ¡¢£¤¥¦§¨©ª«¬­®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖרÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ7€ PJ»defaultÉK]LB@emmc-pwrseqmmc-pwrseq-emmcÉM»default bNê gpio-keys gpio-keys»defaultÉOkey-powern WJ |GPIO Power‚tvcc-host-regulatorregulator-fixed� TJ»defaultÉP ëvcc_host*>P*vcc-lan-regulatorregulator-fixedëvcc_lanú2Z 2Z *>P+ê&vcc-sys-regulatorregulator-fixedëvcc_sysúLK@LK@*>ê* compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0cpudevice_typeregenable-method#cooling-cellsphandleinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsmax-frequencyclocksclock-namesfifo-depthresetsreset-namesstatusbus-widthcap-mmc-highspeedmmc-pwrseqnon-removablepinctrl-namespinctrl-0#io-channel-cellsreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesrockchip,grfphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaydr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplyvp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#mbox-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsdmasdma-names#sound-dai-cellspower-domains#iommu-cellsrockchip,disable-mmu-resetinterrupt-controller#interrupt-cellsrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsstdout-pathbrightness-levelsdefault-brightness-levelenable-gpiospwmsreset-gpioswakeup-sourcelabellinux,codeenable-active-high