Ð þí–"8‹$( þŠì,friendlyarm,nanopi-r2s-plusrockchip,rk3328 +7FriendlyElec NanoPi R2S Plusaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000�/ethernet@ff540000‹/usb@ff600000/device@2•/mmc@ff500000š/mmc@ff520000cpus+cpu@0Ÿcpuarm,cortex-a53«¯¶ÅÕxïpsciý€@0=€J@\€iz… cpu@1Ÿcpuarm,cortex-a53«¯¶ÅÕxïpsciý€@0=€J@\€iz… cpu@2Ÿcpuarm,cortex-a53«¯¶ÅÕxïpsciý€@0=€J@\€iz… cpu@3Ÿcpuarm,cortex-a53«¯¶ÅÕxïpsciý€@0=€J@\€iz… idle-states�pscicpu-sleeparm,idle-stateš«ÂxÓúã„…l2-cachecacheô @2…opp-table-0operating-points-v2…opp-408000000Q– ~ð.œ@?opp-600000000#ÃF ~ð.œ@opp-8160000000£, B@.œ@opp-1008000000<Ü Èà.œ@opp-1200000000G†Œ ±(.œ@opp-1296000000M?d Ö .œ@analog-soundsimple-audio-cardKi2sd~Analog •disabledsimple-audio-card,cpuœsimple-audio-card,codecœarm-pmuarm,cortex-a53-pmu0¦defg± display-subsystemrockchip,display-subsystemÄ  •disabledhdmi-soundsimple-audio-cardKi2sd€~HDMI •disabledsimple-audio-card,cpuœsimple-audio-card,codecœpsciarm,psci-1.0arm,psci-0.2ösmctimerarm,armv8-timer0¦   xin24m fixed-clockÊ×n6çxin24m…Ei2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s«ÿ ¦¯)7úi2s_clki2s_hclk   txrx •disabled…i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s«ÿ ¦¯*8úi2s_clki2s_hclk txrx •disabled…i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s«ÿ ¦¯+9úi2s_clki2s_hclk txrx •disabledspdif@ff030000rockchip,rk3328-spdif«ÿ ¦¯.: úmclkhclk  tx&default4 •disabledpdm@ff040000 rockchip,pdm«ÿ¯=Rúpdm_clkpdm_hclk rx&defaultsleep4> •disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd«ÿ…:io-domains"rockchip,rk3328-io-voltage-domain•okayHUcq�›gpiorockchip,rk3328-grf-gpio©¹power-controller!rockchip,rk3328-power-controllerÅ+…<power-domain@6«¯DÅpower-domain@5« ¯‹BABÅpower-domain@8«¯�FÅreboot-modesyscon-reboot-modeÙÈàRBÃìRBÃúRBà  RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart«ÿ ¦7¯&Òúbaudclkapb_pclk txrx&default 4 !"# •disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart«ÿ ¦8¯'Óúbaudclkapb_pclk txrx&default 4#$%# •disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart«ÿ ¦9¯(Ôúbaudclkapb_pclk txrx&default4&#•okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c«ÿ ¦$+¯7Í úi2cpclk&default4' •disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c«ÿ ¦%+¯8Î úi2cpclk&default4(•okaypmic@18rockchip,rk805« )¦Êçxin32krk805-clkout2©¹4*&default-N\+h+t+€+Œ˜+regulatorsDCDC_REG1¤vdd_log³ÇÙ ß4ñ  0Ôregulator-state-mem6B@DCDC_REG2¤vdd_arm³ÇÙ ß4ñ  0Ô…regulator-state-mem6~ðDCDC_REG3¤vcc_ddr³Çregulator-state-memDCDC_REG4 ¤vcc_io_33³ÇÙ2Z ñ2Z …regulator-state-mem62Z LDO_REG1¤vcc_18³ÇÙw@ñw@…regulator-state-mem6w@LDO_REG2 ¤vcc18_emmc³ÇÙw@ñw@…regulator-state-mem6w@LDO_REG3¤vdd_10³ÇÙB@ñB@regulator-state-mem6B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c«ÿ ¦&+¯9Ï úi2cpclk&default4, •disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c«ÿ ¦'+¯:Ð úi2cpclk&default4- •disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi«ÿ ¦1+¯ Ñúspiclkapb_pclk  txrx&default4./01 •disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt«ÿ ¦(¯ìpwm@ff1b0000rockchip,rk3328-pwm«ÿ¯<Ö úpwmpclk&default42R •disabledpwm@ff1b0010rockchip,rk3328-pwm«ÿ¯<Ö úpwmpclk&default43R •disabledpwm@ff1b0020rockchip,rk3328-pwm«ÿ ¯<Ö úpwmpclk&default44R•okaypwm@ff1b0030rockchip,rk3328-pwm«ÿ0¯<Ö úpwmpclk&default45R •disableddma-controller@ff1f0000arm,pl330arm,primecell«ÿ@¦]¯† úapb_pclkt…thermal-zonessoc-thermal•è£èµ6tripstrip-point0ÅpÑЦpassivetrip-point1ÅLÑЦpassive…7soc-critÅsÑÐ ¦criticalcooling-mapsmap0Ü70á ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿðtsadc@ff250000rockchip,rk3328-tsadc«ÿ% ¦:ý$ ÃP¯$Õútsadcapb_pclk&initdefaultsleep48>9"8,B 3tsadc-apb?:L† c•okayy�…6efuse@ff260000rockchip,rk3328-efuse«ÿ&P+¯> úpclk_efuse« id@7«cpu-leakage@17«logic-leakage@19«cpu-version@1a«¿…Fadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc«ÿ( ¦Pį%êúsaradcapb_pclk,V 3saradc-apb •disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450«ÿ0T¦ZW]XY[\"Ögpgpmmupppp0ppmmu0pp1ppmmu1¯‡‡ úbuscore,fiommu@ff330200rockchip,iommu«ÿ3 ¦`¯“Ý úaclkifaceæ •disablediommu@ff340800rockchip,iommu«ÿ4@ ¦b¯�F úaclkifaceæ •disabledvideo-codec@ff350000rockchip,rk3328-vpu«ÿ5 ¦ Övdpu¯�F úaclkhclkó;ú<iommu@ff350800rockchip,iommu«ÿ5@ ¦ ¯�F úaclkifaceæú<…;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec«ÿ6€ ¦ ¯‹BABúaxiahbcabaccoreý‹AB  ׄׄá£ó=ú<iommu@ff360480rockchip,iommu «ÿ6€@ÿ6À@ ¦J¯‹B úaclkifaceæú<…=vop@ff370000rockchip,rk3328-vop«ÿ7>ü ¦ ¯‘x;úaclk_vopdclk_vophclk_vop,…†‡ 3axiahbdclkó> •disabledport+… endpoint@0«?…Diommu@ff373f00rockchip,iommu«ÿ7? ¦ ¯‘; úaclkifaceæ •disabled…>hdmi@ff3c0000rockchip,rk3328-dw-hdmi«ÿ< ¦#¯çFúiahbisfrcec@hdmi&default 4ABC?: •disabled…ports+port@0«endpointD…?port@1«codec@ff410000rockchip,rk3328-codec«ÿA¯ë* úpclkmclk?: •disabled…phy@ff430000rockchip,rk3328-hdmi-phy«ÿC ¦S¯äEyúsysclkrefoclkrefpclk çhdmi_phyÊ'F 3cpu-versionD •disabled…@clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon«ÿD?:ÊOøýx=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$\zEEE| ©€n6n6n6äáÀäáÀá£õáׄõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€…syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd«ÿE+usb2phy@100rockchip,rk3328-usb2phy«¯Eúphyclk çusb480m_phyÊý{\G•okay…Gotg-portD$¦;<=Öotg-bvalidotg-idlinestate•okay…Whost-portD ¦> Ölinestate•okay…Xmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc«ÿP@ ¦  ¯=!JNúbiuciuciu-driveciu-samples~ðÑ€,m3reset•okayŒ–§4HIJK&default²¿ÌÙçLómmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc«ÿQ@ ¦  ¯>"KOúbiuciuciu-driveciu-samples~ðÑ€,n3reset •disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc«ÿR@ ¦ ¯?#LPúbiuciuciu-driveciu-samples~ðÑ€,o3reset•okayŒ§!&default 4MNOethernet@ff540000rockchip,rk3328-gmac«ÿT ¦Ömacirq8¯dWXZY–ßMústmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac,c 3stmmaceth?:/=K•okayýdf\PPVinputcQnrgmiiw4R&default‚‹”$mdiosnps,dwmac-mdio+ethernet-phy@1«4S&default�'­ÃP ¿)…Qethernet@ff550000rockchip,rk3328-gmac«ÿU?: ¦Ömacirq8¯TSSU•ÞVIústmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy,b 3stmmacethnrmiicT/=KVoutput •disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22«¯V,d&default4UVË…Tusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2«ÿX ¦¯MúotgÝhostå÷ €€@ W usb2-phy•okayusb@ff5c0000 generic-ehci«ÿ\ ¦ ¯NGXusb•okayusb@ff5d0000 generic-ohci«ÿ] ¦ ¯NGXusb•okaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc«ÿ_@ ¦ ¯@MQúbiuciuciu-driveciu-samples~ðÑ€,h3reset •disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3«ÿ` ¦C¯`a„úref_clksuspend_clkbus_clkÝhost utmi_wide  ? W y 𠳕okay+device@2 usbbda,8153«interrupt-controller@ff811000 arm,gic-400 Ì Ý@«ÿ�ÿ� ÿ�@ ÿ�`  ¦ …crypto@ff060000rockchip,rk3328-crypto«ÿ@ ¦¯PQ;úhclk_masterhclk_slavesclk,D 3crypto-rstpinctrlrockchip,rk3328-pinctrl?:+ ògpio@ff210000rockchip,gpio-bank«ÿ! ¦3¯È©¹ Ý Ì…egpio@ff220000rockchip,gpio-bank«ÿ" ¦4¯É©¹ Ý Ì…)gpio@ff230000rockchip,gpio-bank«ÿ# ¦5¯Ê©¹ Ý Ì…igpio@ff240000rockchip,gpio-bank«ÿ$ ¦6¯Ë©¹ Ý Ìpcfg-pull-up ù…[pcfg-pull-down …cpcfg-pull-none …Ypcfg-pull-none-2ma  "…bpcfg-pull-up-2ma ù "pcfg-pull-up-4ma ù "…\pcfg-pull-none-4ma  "…_pcfg-pull-down-4ma  "pcfg-pull-none-8ma  "…]pcfg-pull-up-8ma ù "…^pcfg-pull-none-12ma  " …`pcfg-pull-up-12ma ù " …apcfg-output-high 1pcfg-output-low =pcfg-input-high ù H…Zpcfg-input Hi2c0i2c0-xfer UYY…'i2c1i2c1-xfer UYY…(i2c2i2c2-xfer U YY…,i2c3i2c3-xfer UYY…-i2c3-pins UYYhdmi_i2chdmii2c-xfer UYY…Bpdm-0pdmm0-clk UY…pdmm0-fsync UYpdmm0-sdi0 UY…pdmm0-sdi1 UY…pdmm0-sdi2 UY…pdmm0-sdi3 UY…pdmm0-clk-sleep UZ…pdmm0-sdi0-sleep UZ…pdmm0-sdi1-sleep UZ…pdmm0-sdi2-sleep UZ…pdmm0-sdi3-sleep UZ…pdmm0-fsync-sleep UZtsadcotp-pin U Y…8otp-out U Y…9uart0uart0-xfer U Y[… uart0-cts U Y…!uart0-rts U Y…"uart0-rts-pin U Yuart1uart1-xfer UY[…#uart1-cts UY…$uart1-rts UY…%uart1-rts-pin UYuart2-0uart2m0-xfer UY[uart2-1uart2m1-xfer UY[…&spi0-0spi0m0-clk U[spi0m0-cs0 U [spi0m0-tx U [spi0m0-rx U [spi0m0-cs1 U [spi0-1spi0m1-clk U[spi0m1-cs0 U[spi0m1-tx U[spi0m1-rx U[spi0m1-cs1 U[spi0-2spi0m2-clk U[….spi0m2-cs0 U[…1spi0m2-tx U[…/spi0m2-rx U[…0i2s1i2s1-mclk UYi2s1-sclk UYi2s1-lrckrx UYi2s1-lrcktx UYi2s1-sdi UYi2s1-sdo UYi2s1-sdio1 UYi2s1-sdio2 UYi2s1-sdio3 UYi2s1-sleep� UZZZZZZZZZi2s2-0i2s2m0-mclk UYi2s2m0-sclk UYi2s2m0-lrckrx UYi2s2m0-lrcktx UYi2s2m0-sdi UYi2s2m0-sdo UYi2s2m0-sleep` UZZZZZZi2s2-1i2s2m1-mclk UYi2s2m1-sclk UYi2sm1-lrckrx UYi2s2m1-lrcktx UYi2s2m1-sdi UYi2s2m1-sdo UYi2s2m1-sleepP UZZZZZspdif-0spdifm0-tx UYspdif-1spdifm1-tx UYspdif-2spdifm2-tx UY…sdmmc0-0sdmmc0m0-pwren U\sdmmc0m0-pin U\sdmmc0-1sdmmc0m1-pwren U\sdmmc0m1-pin U\…ksdmmc0sdmmc0-clk U]…Hsdmmc0-cmd U^…Isdmmc0-dectn U\…Jsdmmc0-wrprt U\sdmmc0-bus1 U^sdmmc0-bus4@ U^^^^…Ksdmmc0-pins€ U\\\\\\\\sdmmc0extsdmmc0ext-clk U_sdmmc0ext-cmd U\sdmmc0ext-wrprt U\sdmmc0ext-dectn U\sdmmc0ext-bus1 U\sdmmc0ext-bus4@ U\\\\sdmmc0ext-pins€ U\\\\\\\\sdmmc1sdmmc1-clk U ]sdmmc1-cmd U ^sdmmc1-pwren U^sdmmc1-wrprt U^sdmmc1-dectn U^sdmmc1-bus1 U^sdmmc1-bus4@ U^^^^sdmmc1-pins� U \ \\\\\\\\emmcemmc-clk U`…Memmc-cmd Ua…Nemmc-pwren UYemmc-rstnout UYemmc-bus1 Uaemmc-bus4@ Uaaaaemmc-bus8€ Uaaaaaaaa…Opwm0pwm0-pin UY…2pwm1pwm1-pin UY…3pwm2pwm2-pin UY…4pwmirpwmir-pin UY…5gmac-1rgmiim1-pins` U ] __]___ _ _] ]__]]] ]_]]]]…Rrmiim1-pins Ub`bbbb b b` ` Y YYYYYgmac2phyfephyled-speed10 UYfephyled-duplex UYfephyled-rxm1 UY…Ufephyled-txm1 UYfephyled-linkm1 UY…Vtsadc_pintsadc-int U Ytsadc-pin U Yhdmi_pinhdmi-cec UY…Ahdmi-hpd Uc…Ccif-0dvp-d2d9-m0À UYYYYY Y Y YYYYYcif-1dvp-d2d9-m1À UYYYYYYYYYYYYbuttonreset-button-pin UY…dgmac2ioeth-phy-reset-pin Uc…Sledslan-led-pin UY…fsys-led-pin UY…gwan-led-pin UY…hlanlan-vdd-pin UY…lpmicpmic-int-l U[…*sdsdio-vcc-pin U[…jchosen cserial2:1500000n8gmac-clock fixed-clock×sY@ çgmac_clkinÊ…Pkeys gpio-keys4d&defaultkey-reset oreset Åe u˜ €2leds gpio-leds 4fgh&defaultled-0 Åi onanopi-r2s:green:lanled-1 Åe onanopi-r2s:red:sys ’onled-2 Åi onanopi-r2s:green:wansdmmcio-regulatorregulator-gpio   Å)4j&default ¤vcc_io_sdio³Ùw@ñ2Z  ³ˆ Îvoltage ÝÐÎw@2Z  î…sdmmc-regulatorregulator-fixed ùe4k&default¤vcc_sdÇÙ2Z ñ2Z  î…Lvdd-5vregulator-fixed¤vdd_5v³ÇÙLK@ñLK@…+vdd-5v-lanregulator-fixed   ùi4l&default ¤vdd_5v_lan³Ç î+ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-hs200-1_8vnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio