Ð þí�¦8„ ( †ƒè$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000�/ethernet@ff550000‹/mmc@ff500000�/mmc@ff510000•/mmc@ff520000cpus+cpu@0šcpuarm,cortex-a53¦ª±ÀÐxêpsciø €@+8€E@W€du€ cpu@1šcpuarm,cortex-a53¦ª±ÀÐxêpsciø €@+8€E@W€du€ cpu@2šcpuarm,cortex-a53¦ª±ÀÐxêpsciø €@+8€E@W€du€ cpu@3šcpuarm,cortex-a53¦ª±ÀÐxêpsciø €@+8€E@W€du€ idle-statesˆpscicpu-sleeparm,idle-state•¦½xÎúÞ„€l2-cachecacheïû@-€opp-table-0operating-points-v2 €opp-408000000Q–~ð)œ@:opp-600000000#ÃF~ð)œ@opp-8160000000£,B@)œ@opp-1008000000<ÜÈà)œ@opp-1200000000G†Œ±()œ@opp-1296000000M?dÖ )œ@analog-soundsimple-audio-cardFi2s_yAnalog �disabledsimple-audio-card,cpu—simple-audio-card,codec—arm-pmuarm,cortex-a53-pmu0¡defg¬ display-subsystemrockchip,display-subsystem¿ hdmi-soundsimple-audio-cardFi2s_€yHDMI �disabledsimple-audio-card,cpu—simple-audio-card,codec—psciarm,psci-1.0arm,psci-0.2ñsmctimerarm,armv8-timer0¡   xin24m fixed-clockÅÒn6âxin24m€Bi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s¦ÿ ¡ª)7õi2s_clki2s_hclk  txrx �disabled€i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s¦ÿ ¡ª*8õi2s_clki2s_hclktxrx �disabled€i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s¦ÿ ¡ª+9õi2s_clki2s_hclktxrx �disabledspdif@ff030000rockchip,rk3328-spdif¦ÿ ¡ª.: õmclkhclk tx!default/ �disabledpdm@ff040000 rockchip,pdm¦ÿª=Rõpdm_clkpdm_hclkrx!defaultsleep/9 �disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd¦ÿ€7io-domains"rockchip,rk3328-io-voltage-domain �disabledgpiorockchip,rk3328-grf-gpioCSpower-controller!rockchip,rk3328-power-controller_+€9power-domain@6¦ªD_power-domain@5¦ ª‹BAB_power-domain@8¦ª�F_reboot-modesyscon-reboot-modesÈzRBÆRBÔRBà ¤RBÃserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart¦ÿ ¡7ª&Òõbaudclkapb_pclktxrx!default /°½ �disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart¦ÿ ¡8ª'Óõbaudclkapb_pclktxrx!default / !°½ �disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart¦ÿ ¡9ª(Ôõbaudclkapb_pclktxrx!default/"°½�okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c¦ÿ ¡$+ª7Í õi2cpclk!default/# �disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c¦ÿ ¡%+ª8Î õi2cpclk!default/$�okaypmic@18rockchip,rk805¦ %¡Åâxin32krk805-clkout2CS!default/&Çèö''''&(2(regulatorsDCDC_REG1 >vdd_logicM ß4e }‘regulator-state-mem£»B@DCDC_REG2>vdd_armM ß4e }‘€regulator-state-mem£»~ðDCDC_REG3>vcc_ddr}‘regulator-state-mem£DCDC_REG4>vcc_ioM2Z e2Z }‘€(regulator-state-mem£»2Z LDO_REG1>vcc_18Mw@ew@}‘regulator-state-mem£»w@LDO_REG2 >vcc18_emmcMw@ew@}‘regulator-state-mem£»w@LDO_REG3>vdd_10MB@eB@}‘regulator-state-mem£»B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c¦ÿ ¡&+ª9Ï õi2cpclk!default/) �disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c¦ÿ ¡'+ª:Ð õi2cpclk!default/* �disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi¦ÿ ¡1+ª Ñõspiclkapb_pclk txrx!default/+,-. �disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt¦ÿ ¡(ªìpwm@ff1b0000rockchip,rk3328-pwm¦ÿª<Ö õpwmpclk!default//× �disabledpwm@ff1b0010rockchip,rk3328-pwm¦ÿª<Ö õpwmpclk!default/0× �disabledpwm@ff1b0020rockchip,rk3328-pwm¦ÿ ª<Ö õpwmpclk!default/1× �disabledpwm@ff1b0030rockchip,rk3328-pwm¦ÿ0ª<Ö õpwmpclk!default/2× �disableddma-controller@ff1f0000arm,pl330arm,primecell¦ÿ@¡âª† õapb_pclkù€thermal-zonessoc-thermalè(è:3tripstrip-point0JpVСpassivetrip-point1JLVСpassive€4soc-critJsVÐ ¡criticalcooling-mapsmap0a40f ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿutsadc@ff250000rockchip,rk3328-tsadc¦ÿ% ¡:‚$’ÃPª$Õõtsadcapb_pclk!initdefaultsleep/596§5±B ¸tsadc-apbÄ7ц è�okay€3efuse@ff260000rockchip,rk3328-efuse¦ÿ&P+ª> õpclk_efuseþ id@7¦cpu-leakage@17¦logic-leakage@19¦cpu-version@1a¦€Cadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc¦ÿ( ¡Pª%êõsaradcapb_pclk±V ¸saradc-apb �disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450¦ÿ0T¡ZW]XY[\")gpgpmmupppp0ppmmu0pp1ppmmu1ª‡‡ õbuscore±fiommu@ff330200rockchip,iommu¦ÿ3 ¡`ª“Ý õaclkiface9 �disablediommu@ff340800rockchip,iommu¦ÿ4@ ¡bª�F õaclkiface9 �disabledvideo-codec@ff350000rockchip,rk3328-vpu¦ÿ5 ¡ )vdpuª�F õaclkhclkF8M9iommu@ff350800rockchip,iommu¦ÿ5@ ¡ ª�F õaclkiface9M9€8video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec¦ÿ6€ ¡ ª‹BABõaxiahbcabaccore‚‹AB ’ׄׄá£F:M9iommu@ff360480rockchip,iommu ¦ÿ6€@ÿ6À@ ¡Jª‹B õaclkiface9M9€:vop@ff370000rockchip,rk3328-vop¦ÿ7>ü ¡ ª‘x;õaclk_vopdclk_vophclk_vop±…†‡ ¸axiahbdclkF; �disabledport+€ endpoint@0¦[<€Aiommu@ff373f00rockchip,iommu¦ÿ7? ¡ ª‘; õaclkiface9 �disabled€;hdmi@ff3c0000rockchip,rk3328-dw-hdmi¦ÿ<° ¡#ªçFõiahbisfrceck=phdmi!default />?@Ä7 �disabled€ports+port@0¦endpoint[A€<port@1¦codec@ff410000rockchip,rk3328-codec¦ÿAªë* õpclkmclkÄ7 �disabled€phy@ff430000rockchip,rk3328-hdmi-phy¦ÿC ¡SªäByõsysclkrefoclkrefpclk âhdmi_phyÅzC †cpu-version— �disabled€=clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon¦ÿDÄ7Å¢ø‚x=&'(ˆ‰Ž…ƒŠŒ�ABDC"\5ˆH؉4æ$¯zBBB|’©€n6n6n6äáÀäáÀá£õáׄõáúð€õáõáõáúð€úð€úð€úð€n6#ÃFLG†ŒðÑ€xhÀxhÀðÑ€xhÀxhÀ€€syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd¦ÿE+usb2phy@100rockchip,rk3328-usb2phy¦ªBõphyclk âusb480m_phyÅ‚{¯D�okay€Dotg-port—$¡;<=)otg-bvalidotg-idlinestate�okay€Uhost-port— ¡> )linestate�okay€Vmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿP@ ¡  ª=!JNõbiuciuciu-driveciu-sampleÆÑðÑ€±m¸reset�okayßéû !default/EFGHImmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿQ@ ¡  ª>"KOõbiuciuciu-driveciu-sampleÆÑðÑ€±n¸reset�okayßû#0FJQ!default /KLMmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿR@ ¡ ª?#LPõbiuciuciu-driveciu-sampleÆÑðÑ€±o¸reset�okayßéQ!default /NOPethernet@ff540000rockchip,rk3328-gmac¦ÿT ¡)macirq8ªdWXZY–ßMõstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac±c ¸stmmacethÄ7_m{ �disabledethernet@ff550000rockchip,rk3328-gmac¦ÿUÄ7 ¡)macirq8ªTSSU•ÞVIõstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy±b ¸stmmaceth†rmii�Q_m{šoutput�okay§R²úð€‚e¯Tmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22¦ªV±d!default/STÆ€Qusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2¦ÿX ¡ªMõotgØotgàò€€@ kU pusb2-phy�okayusb@ff5c0000 generic-ehci¦ÿ\ ¡ ªNDkVpusb�okayusb@ff5d0000 generic-ohci¦ÿ] ¡ ªNDkVpusb�okaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc¦ÿ_@ ¡ ª@MQõbiuciuciu-driveciu-sampleÆÑðÑ€±h¸reset �disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3¦ÿ` ¡Cª`a„õref_clksuspend_clkbus_clkØotg utmi_wide:Rt•® �disabledinterrupt-controller@ff811000 arm,gic-400ÇØ@¦ÿ�ÿ� ÿ�@ ÿ�`  ¡ €crypto@ff060000rockchip,rk3328-crypto¦ÿ@ ¡ªPQ;õhclk_masterhclk_slavesclk±D ¸crypto-rstpinctrlrockchip,rk3328-pinctrlÄ7+ígpio@ff210000rockchip,gpio-bank¦ÿ! ¡3ªÈCSØÇ€dgpio@ff220000rockchip,gpio-bank¦ÿ" ¡4ªÉCSØÇ€cgpio@ff230000rockchip,gpio-bank¦ÿ# ¡5ªÊCSØÇ€%gpio@ff240000rockchip,gpio-bank¦ÿ$ ¡6ªËCSØÇpcfg-pull-upô€Ypcfg-pull-down €apcfg-pull-none €Wpcfg-pull-none-2ma  €`pcfg-pull-up-2maô pcfg-pull-up-4maô €Zpcfg-pull-none-4ma  €]pcfg-pull-down-4ma  pcfg-pull-none-8ma  €[pcfg-pull-up-8maô €\pcfg-pull-none-12ma   €^pcfg-pull-up-12maô  €_pcfg-output-high ,pcfg-output-low 8pcfg-input-highô C€Xpcfg-input Ci2c0i2c0-xfer PWW€#i2c1i2c1-xfer PWW€$i2c2i2c2-xfer P WW€)i2c3i2c3-xfer PWW€*i2c3-pins PWWhdmi_i2chdmii2c-xfer PWW€?pdm-0pdmm0-clk PW€pdmm0-fsync PWpdmm0-sdi0 PW€pdmm0-sdi1 PW€pdmm0-sdi2 PW€pdmm0-sdi3 PW€pdmm0-clk-sleep PX€pdmm0-sdi0-sleep PX€pdmm0-sdi1-sleep PX€pdmm0-sdi2-sleep PX€pdmm0-sdi3-sleep PX€pdmm0-fsync-sleep PXtsadcotp-pin P W€5otp-out P W€6uart0uart0-xfer P WY€uart0-cts P W€uart0-rts P W€uart0-rts-pin P Wuart1uart1-xfer PWY€uart1-cts PW€ uart1-rts PW€!uart1-rts-pin PWuart2-0uart2m0-xfer PWYuart2-1uart2m1-xfer PWY€"spi0-0spi0m0-clk PYspi0m0-cs0 P Yspi0m0-tx P Yspi0m0-rx P Yspi0m0-cs1 P Yspi0-1spi0m1-clk PYspi0m1-cs0 PYspi0m1-tx PYspi0m1-rx PYspi0m1-cs1 PYspi0-2spi0m2-clk PY€+spi0m2-cs0 PY€.spi0m2-tx PY€,spi0m2-rx PY€-i2s1i2s1-mclk PWi2s1-sclk PWi2s1-lrckrx PWi2s1-lrcktx PWi2s1-sdi PWi2s1-sdo PWi2s1-sdio1 PWi2s1-sdio2 PWi2s1-sdio3 PWi2s1-sleep� PXXXXXXXXXi2s2-0i2s2m0-mclk PWi2s2m0-sclk PWi2s2m0-lrckrx PWi2s2m0-lrcktx PWi2s2m0-sdi PWi2s2m0-sdo PWi2s2m0-sleep` PXXXXXXi2s2-1i2s2m1-mclk PWi2s2m1-sclk PWi2sm1-lrckrx PWi2s2m1-lrcktx PWi2s2m1-sdi PWi2s2m1-sdo PWi2s2m1-sleepP PXXXXXspdif-0spdifm0-tx PWspdif-1spdifm1-tx PWspdif-2spdifm2-tx PW€sdmmc0-0sdmmc0m0-pwren PZsdmmc0m0-pin PZsdmmc0-1sdmmc0m1-pwren PZsdmmc0m1-pin PZ€esdmmc0sdmmc0-clk P[€Esdmmc0-cmd P\€Fsdmmc0-dectn PZ€Gsdmmc0-wrprt PZsdmmc0-bus1 P\sdmmc0-bus4@ P\\\\€Hsdmmc0-pins€ PZZZZZZZZsdmmc0extsdmmc0ext-clk P]sdmmc0ext-cmd PZsdmmc0ext-wrprt PZsdmmc0ext-dectn PZsdmmc0ext-bus1 PZsdmmc0ext-bus4@ PZZZZsdmmc0ext-pins€ PZZZZZZZZsdmmc1sdmmc1-clk P [€Msdmmc1-cmd P \€Lsdmmc1-pwren P\sdmmc1-wrprt P\sdmmc1-dectn P\sdmmc1-bus1 P\sdmmc1-bus4@ P\\\\€Ksdmmc1-pins� P Z ZZZZZZZZemmcemmc-clk P^€Nemmc-cmd P_€Oemmc-pwren PWemmc-rstnout PWemmc-bus1 P_emmc-bus4@ P____emmc-bus8€ P________€Ppwm0pwm0-pin PW€/pwm1pwm1-pin PW€0pwm2pwm2-pin PW€1pwmirpwmir-pin PW€2gmac-1rgmiim1-pins` P [ ]][]]] ] ][ []][[[ [][[[[rmiim1-pins P`^```` ` `^ ^ W WWWWWgmac2phyfephyled-speed10 PWfephyled-duplex PWfephyled-rxm1 PW€Sfephyled-txm1 PWfephyled-linkm1 PW€Ttsadc_pintsadc-int P Wtsadc-pin P Whdmi_pinhdmi-cec PW€>hdmi-hpd Pa€@cif-0dvp-d2d9-m0À PWWWWW W W WWWWWcif-1dvp-d2d9-m1À PWWWWWWWWWWWWpmicpmic-int-l PY€&sdio-pwrseqwifi-enable-h PW€bchosen ^serial2:1500000n8dc-12vregulator-fixed>dc_12v}‘M·e·€fsdio-pwrseqmmc-pwrseq-simple!default/b jc€Jsdmmc-regulatorregulator-fixed vd!default/e>vcc_sdM2Z e2Z  {(€Ivcc-sysregulator-fixed>vcc_sys}‘MLK@eLK@ {f€'vcc-phy-regulatorregulator-fixed>vcc_phy}‘€R compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblphy-modephy-handleclock_in_outphy-supplyassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply