Ð þí‚“8|$(o{ì&firefly,roc-rk3308-ccrockchip,rk3308 +7Firefly ROC-RK3308-CC boardaliases=/pinctrl/gpio@ff220000C/pinctrl/gpio@ff230000I/pinctrl/gpio@ff240000O/pinctrl/gpio@ff250000U/pinctrl/gpio@ff260000[/i2c@ff040000`/i2c@ff050000e/i2c@ff060000j/i2c@ff070000o/serial@ff0a0000w/serial@ff0b0000/serial@ff0c0000‡/serial@ff0d0000�/serial@ff0e0000—/spi@ff120000œ/spi@ff130000¡/spi@ff140000¦/mmc@ff480000«/mmc@ff490000cpus+cpu@0°cpuarm,cortex-a35¼ÀpsciÎÕäZþ"3>cpu@1°cpuarm,cortex-a35¼Àpsciþ">cpu@2°cpuarm,cortex-a35¼Àpsciþ"> cpu@3°cpuarm,cortex-a35¼Àpsciþ"> idle-statesFpscicpu-sleeparm,idle-stateSd{xŒúœ„>l2-cachecache­¹>opp-table-0operating-points-v2Ç>opp-408000000ÒQ– Ù~ð~ðr`çœ@øopp-600000000Ò#ÃF Ù~ð~ðr`çœ@opp-816000000Ò0£, Ù£è£èr`çœ@opp-1008000000Ò<Ü Ù*ˆ*ˆr`çœ@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock"úð€ 2mac_clkinEpsci arm,psci-1.0Çsmctimerarm,armv8-timer0   xin24m fixed-clockE"n62xin24m>Rgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd¼ÿ€>5io-domains"rockchip,rk3308-io-voltage-domain Rdisabledreboot-modesyscon-reboot-modeY`RBÃpRBÃ|RBÈRBÖRBà syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd¼ÿ€@+usb2phy@100rockchip,rk3308-usb2phy¼¤´ ÎHËphyclk 2usb480m_phyE Rdisabled> otg-port$CDE×otg-bvalidotg-idlinestateç Rdisabled>;host-port J ×linestateç Rdisabled><syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd¼ÿ°+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd¼ÿÀ+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c¼ÿÎÊ Ëi2cpclk  òdefault + Rdisabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c¼ÿÎË Ëi2cpclk  òdefault +Rokay"€rtc@51 nxp,pcf8563¼QEi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c¼ÿÎÌ Ëi2cpclk  òdefault+ Rdisabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c¼ÿÎÍ Ëi2cpclk òdefault+ Rdisabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt¼ÿÎÖ   Rdisabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart¼ÿ  ÎÅËbaudclkapb_pclk òdefault  Rdisabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart¼ÿ  ÎÆËbaudclkapb_pclk òdefault  Rdisabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart¼ÿ  ÎÇËbaudclkapb_pclk òdefaultRokayserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart¼ÿ  ÎÈËbaudclkapb_pclk òdefault Rdisabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart¼ÿ ÎÉËbaudclkapb_pclk òdefault  Rdisabledspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi¼ÿ +ÎÏËspiclkapb_pclk!&txrxòdefault Rdisabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi¼ÿ +ÎÐËspiclkapb_pclk!&txrxòdefault !"# Rdisabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi¼ÿ +ÎÑËspiclkapb_pclk!$$&txrxòdefault%&'( Rdisabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿÎyè Ëpwmpclkòdefault)0 Rdisabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿÎyè Ëpwmpclkòdefault*0 Rdisabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿ Îyè Ëpwmpclkòdefault+0 Rdisabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿ0Îyè Ëpwmpclkòdefault,0 Rdisabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿÎxç Ëpwmpclkòdefault-0 Rdisabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿÎxç Ëpwmpclkòactive.0Rokay>`pwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿ Îxç Ëpwmpclkòdefault/0 Rdisabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿ0Îxç Ëpwmpclkòdefault00 Rdisabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿÎÎ Ëpwmpclkòdefault10Rokay>epwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿÎÎ Ëpwmpclkòdefault20 Rdisabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿ ÎÎ Ëpwmpclkòdefault30 Rdisabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm¼ÿ0ÎÎ Ëpwmpclkòdefault40 Rdisabledrktimer@ff1a0000rockchip,rk3288-timer¼ÿ  ÎÔ Ëpclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc¼ÿ %Î%ÒËsaradcapb_pclk;MF Tsaradc-apb Rdisabledefuse@ff210000rockchip,rk3308-otp¼ÿ!@+Î'ÕåËotpapb_pclkphyMTTphyid@7¼cpu-leakage@17¼logic-leakage@18¼dma-controller@ff2c0000arm,pl330arm,primecell¼ÿ,@`Ί Ëapb_pclkw>dma-controller@ff2d0000arm,pl330arm,primecell¼ÿ-@`΋ Ëapb_pclkw>$i2s@ff320000rockchip,rk3308-i2s-tdm¼ÿ2 2Ëmclk_txmclk_rxhclkÎTV¦!$$&rxtxM�� Ttx-mrx-m‚5 Rdisabledi2s@ff330000rockchip,rk3308-i2s-tdm¼ÿ3 3Ëmclk_txmclk_rxhclkÎXZ§!$&rxM’“ Ttx-mrx-m‚5 Rdisabledi2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s¼ÿ5 4Î\¨Ëi2s_clki2s_hclk!$$ &txrxM•”Treset-mreset-hòdefault6789 Rdisabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s¼ÿ6 5Î^©Ëi2s_clki2s_hclk!$ &rxM—–Treset-mreset-h Rdisabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif¼ÿ: 7Îb¢ Ëmclkhclk!$ &txòdefault: Rdisabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2¼ÿ@ BΞËotg�otg—©¸€€@ Ç; Ìusb2-phy Rdisabledusb@ff440000 generic-ehci¼ÿD GΟ  Ç<Ìusb Rdisabledusb@ff450000 generic-ohci¼ÿE HΟ  Ç<Ìusb Rdisabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc¼ÿH@ LÖ Îš012Ëbiuciuciu-driveciu-sampleàëðÑ€òdefault=>?@Rokayù ,.;HVAbBmmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc¼ÿI@ MÖ Îœ:;<Ëbiuciuciu-driveciu-sampleàëðÑ€Rokayùo~mmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshc¼ÿJ@ NÖ Î›567Ëbiuciuciu-driveciu-sampleàëðÑ€òdefault CDE Rdisablednand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfc¼ÿK@ QΙ-Ëahbnfc¤-ŒðÑ€FGHIJKLòdefault Rdisabledethernet@ff4e0000rockchip,rk3308-gmac¼ÿN @×macirq@Î@BBA@†ÃC[Ëstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed¡rmiiòdefaultMNM} Tstmmaceth‚5 Rdisabledspi@ff4c0000 rockchip,sfc¼ÿL@ RÎ=�Ëclk_sfchclk_sfc OPQòdefault Rdisabledclock-controller@ff500000rockchip,rk3308-cru¼ÿPÎRËxin24m‚5Eª¤Œ€>codec@ff560000rockchip,rk3308-codec¼ÿV‚5Ëmclk_txmclk_rxhclkÎUWÄTcodecM™· Rdisabledinterrupt-controller@ff580000 arm,gic-400@¼ÿXÿX ÿX@ ÿX`   ÈÙ>sram@fff80000 mmio-sram¼ÿøîÿø+ddr-sram@0¼€vad-sram@8000¼€€pinctrlrockchip,rk3308-pinctrl‚5+îòdefaultSgpio@ff220000rockchip,gpio-bank¼ÿ" (Î×õÙÈ>^gpio@ff230000rockchip,gpio-bank¼ÿ# )ÎØõÙÈgpio@ff240000rockchip,gpio-bank¼ÿ$ *ÎÙõÙÈgpio@ff250000rockchip,gpio-bank¼ÿ% +ÎÚõÙÈgpio@ff260000rockchip,gpio-bank¼ÿ& ,ÎÛõÙÈ>cpcfg-pull-up>]pcfg-pull-down>Zpcfg-pull-none->Vpcfg-pull-none-2ma-:pcfg-pull-up-2ma:pcfg-pull-up-4ma:>\pcfg-pull-none-4ma-:>[pcfg-pull-down-4ma:pcfg-pull-none-8ma-:>Tpcfg-pull-up-8ma:>Upcfg-pull-none-12ma-: >Xpcfg-pull-up-12ma: >Wpcfg-pull-none-smt-I>Ypcfg-output-high^pcfg-output-lowjpcfg-input-highupcfg-inputuemmcemmc-clk‚ Temmc-cmd‚Uemmc-pwren‚ Vemmc-rstn‚ Vemmc-bus1‚Uemmc-bus4@‚UUUUemmc-bus8€‚UUUUUUUUflashflash-csn0‚ V>Iflash-rdy‚ V>Kflash-ale‚ V>Fflash-cle‚ V>Hflash-wrn‚V>Lflash-rdn‚ V>Jflash-bus8€‚WWWWWWWW>Gsfcsfc-bus4@‚VVVV>Qsfc-bus2 ‚VVsfc-cs0‚V>Psfc-clk‚V>Ogmacrmii-pins�‚XXXVVVVV V>Mmac-refclk-12ma‚ X>Nmac-refclk‚ Vgmac-m1rmiim1-pins�‚XXXVVVVV Vmacm1-refclk-12ma‚ Xmacm1-refclk‚ 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Vpdm-m0-sdi3‚Vpdm_m1pdm-m1-clk‚Vpdm-m1-sdi0‚Vpdm-m1-sdi1‚Vpdm-m1-sdi2‚Vpdm-m1-sdi3‚Vpdm_m2pdm-m2-clkm‚Vpdm-m2-clk‚Vpdm-m2-sdi0‚ Vpdm-m2-sdi1‚Vpdm-m2-sdi2‚Vpdm-m2-sdi3‚Vpwm0pwm0-pin‚ Vpwm0-pin-pull-down‚ Z>1pwm1pwm1-pin‚V>2pwm1-pin-pull-down‚Zpwm2pwm2-pin‚V>3pwm2-pin-pull-down‚Zpwm3pwm3-pin‚V>4pwm3-pin-pull-down‚Zpwm4pwm4-pin‚V>-pwm4-pin-pull-down‚Zpwm5pwm5-pin‚Vpwm5-pin-pull-down‚Z>.pwm6pwm6-pin‚V>/pwm6-pin-pull-down‚Zpwm7pwm7-pin‚V>0pwm7-pin-pull-down‚Zpwm8pwm8-pin‚ V>)pwm8-pin-pull-down‚ Zpwm9pwm9-pin‚ V>*pwm9-pin-pull-down‚ Zpwm10pwm10-pin‚ V>+pwm10-pin-pull-down‚ Zpwm11pwm11-pin‚V>,pwm11-pin-pull-down‚Zrtcrtc-32k‚V>Ssdmmcsdmmc-clk‚[>=sdmmc-cmd‚\>>sdmmc-det‚\>?sdmmc-pwren‚[sdmmc-bus1‚\sdmmc-bus4@‚\\\\>@sdiosdio-clk‚T>Esdio-cmd‚U>Dsdio-pwren‚Tsdio-wrpt‚Tsdio-intn‚Tsdio-bus1‚Usdio-bus4@‚UUUU>Cspdif_inspdif-in‚Vspdif_outspdif-out‚V>:spi0spi0-clk‚\>spi0-csn0‚\>spi0-miso‚\>spi0-mosi‚\>spi1spi1-clk‚ \> spi1-csn0‚ \>!spi1-miso‚ \>"spi1-mosi‚ \>#spi1-m1spi1m1-miso‚\spi1m1-mosi‚\spi1m1-clk‚\spi1m1-csn0‚ \spi2spi2-clk‚\>%spi2-csn0‚\>&spi2-miso‚\>'spi2-mosi‚\>(tsadctsadc-otp-pin‚ Vtsadc-otp-out‚ Vuart0uart0-xfer ‚]]>uart0-cts‚V>uart0-rts‚V>uart0-rts-pin‚Vuart1uart1-xfer ‚]]>uart1-cts‚V>uart1-rts‚V>uart2-m0uart2m0-xfer ‚]]>uart2-m1uart2m1-xfer ‚]]uart3uart3-xfer ‚ ] ]>uart3-m1uart3m1-xfer ‚]]uart4uart4-xfer ‚ ]]>uart4-cts‚V>uart4-rts‚V>uart4-rts-pin‚Vir-receiverir-recv-pin‚V>_buttonspwr-key‚]chosen�serial2:1500000n8ir-receivergpio-ir-receiver œ^òdefault_ir_tx pwm-ir-tx¢`a¨leds gpio-ledsled-0§firefly:red:power ­default-onÃon œ^led-1§firefly:blue:user ­rc-feedbackÃoff œ^ typec-vcc5vregulator-fixed Ñtypec_vcc5vàLK@øLK@$>avcc5v0-sysregulator-fixed Ñvcc5v0_sysàLK@øLK@$6a>bvcc-ioregulator-fixedÑvcc_ioà2Z ø2Z $6b>dvcc-sdmmcregulator-gpio Ñvcc_sdmmcàw@ø2Z  œ^w@2Z 6b>Bvcc-sdregulator-fixed AcÑvcc_sdà2Z ø2Z $6d>Avdd-corepwm-regulator¢eˆ Ñvdd_coreà žxør`Fú$db>vdd-logregulator-fixedÑvdd_logà�ø�$6b compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsstatusoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesarm,pl330-periph-burst#dma-cellsrockchip,grfdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removableassigned-clock-ratesphy-mode#reset-cells#sound-dai-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathgpiospwmslabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioregulator-settling-time-up-uspwm-supply