Ð þíCû89x( ƒ9@%mediatek,mt8195-demomediatek,mt8195 +7MediaTek MT8195 demo boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000ƒ/soc/vpp-merge@1c10f000Š/soc/vpp-merge@1c110000‘/soc/dma-controller@1c104000œ/soc/dma-controller@1c105000§/soc/dma-controller@1c106000²/soc/dma-controller@1c107000½/soc/dma-controller@1c108000È/soc/dma-controller@1c109000Ó/soc/dma-controller@1c10a000Þ/soc/dma-controller@1c10b000é/soc/serial@11001100cpus+cpu@0ñcpuarm,cortex-a55ýpsci#ec3@34FV€c@u€‚€�@¡€®¿Î cpu@100ñcpuarm,cortex-a55ýpsci#ec3@34FV€c@u€‚€�@¡€®¿Î cpu@200ñcpuarm,cortex-a55ýpsci#ec3@34FV€c@u€‚€�@¡€®¿Î cpu@300ñcpuarm,cortex-a55ýpsci#ec3@34FV€c@u€‚€�@¡€®¿Î cpu@400ñcpuarm,cortex-a78ýpsci#�fÔÀ3FVc@u‚�@¡®¿Î cpu@500ñcpuarm,cortex-a78ýpsci#�fÔÀ3FVc@u‚�@¡®¿Îcpu@600ñcpuarm,cortex-a78ýpsci#�fÔÀ3FVc@u‚�@¡®¿Îcpu@700ñcpuarm,cortex-a78ýpsci#�fÔÀ3FVc@u‚�@¡®¿Îcpu-mapcluster0core0Ö core1Ö core2Ö core3Ö core4Ö core5Öcore6Öcore7Öidle-statesÚpscicpu-retention-larm,idle-stateçþ2 _0DÎcpu-retention-barm,idle-stateçþ- Œ0äÎcpu-off-larm,idle-stateçþ7 ›0HÎcpu-off-barm,idle-stateçþ2 È0èÎl2-cache0cacheAXe@w®MÎl2-cache1cacheAXe@w®MÎl3-cachecacheAX e@wMÎdsu-pmu arm,dsu-pmu[ f kfaildmic-codec dmic-codecr2mt8195-sound� kdisabledfixed-factor-clock-13mfixed-factor-clock¡®µ¿Êclk13mÎ(oscillator-26m fixed-clock¡#Œº€Êclk26mÎoscillator-32k fixed-clock¡#€Êclk32kperformance-controller@11bc10mediatek,cpufreq-hw ý¼ ½0 ÝÎopp-table-gpuoperating-points-v2÷Î`opp-390000000>í€ ‰hopp-410000000p€ ¡Òopp-431000000°‰À ¡Òopp-4730000001h@ º<opp-515000000²FÀ º<opp-556000000!#ã Ò¦opp-598000000#¤Á€ ëopp-640000000&%  ëopp-670000000'ïc€ äopp-700000000)¹' L¸opp-730000000+‚ê€ }Œopp-760000000-L® ®`opp-790000000/q€ ß4opp-8200000000à5 opp-8500000002©ø€ @Üopp-8800000004s¼ q°pmu-a55arm,cortex-a55-pmu [pmu-a78arm,cortex-a78-pmu [psci arm,psci-1.0smctimerarm,armv8-timer @[   soc+ simple-businterrupt-controller@c000000 arm,gic-v3): Q ý   [ Îppi-partitionsinterrupt-partition-0f Îinterrupt-partition-1f Îsyscon@10000000 mediatek,mt8195-topckgensysconý¡Îsyscon@10001000#mediatek,mt8195-infracfg_aosysconý¡oÎsyscon@10003000mediatek,mt8195-pericfgsysconý0¡Î;pinctrl@10005000mediatek,mt8195-pinctrl€ýPÑÓÔâëô°B|iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint†–¢�Q[ë)Îeth-default-pinsÎ7pins-txd®MNOPµpins-cc®UXWVµpins-rxd®QRSTpins-mdio®YZÄpins-power®[\Ñeth-sleep-pinsÎ8pins-txd®MNOPpins-cc®UXWVpins-rxd®QRSTpins-mdio®YZÝëgpio-keys-pinsΟpins®jÄi2c6-pinsÎOpins®ømmc0-default-pinsÎ>pins-clk®zµfpins-cmd-dat$®~}|{wvutyĵøepins-rst®xµøemmc0-uhs-pinsÎ?pins-clk®zµfpins-cmd-dat$®~}|{wvutyĵøepins-ds®µfpins-rst®xµøemmc1-default-pinsÎBpins-clk®oµfpins-cmd-dat®npqrsĵøepins-insert®�ømmc1-uhs-pinsÎCpins-clk®oµfpins-cmd-dat®npqrsĵøeuart0-pinsÎ.pins®bcuart1-pinsÎ/pins®fgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfdý`power-controller!mediatek,mt8195-power-controller+Î*power-domain@8ý+power-domain@9ý ®(mfgalt4+power-domain@10ý power-domain@11ý power-domain@12ý power-domain@13ý power-domain@14ýpower-domain@15ýØ® @AKà   (vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-184+power-domain@16ý8®â$%&'()D(vdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-54+power-domain@17ý®á(vppsys1vppsys1-0vppsys1-14power-domain@22ý ®$(wepsys-0wepsys-1wepsys-2wepsys-34power-domain@23ý®(vdec0-04+power-domain@24ý®(vdec1-04power-domain@25ý® (vdec2-04power-domain@26ý®! (venc0-larb4+power-domain@27ý®" (venc1-larb4power-domain@18ý ®ã###&(vdosys1vdosys1-0vdosys1-1vdosys1-24+power-domain@19ý4power-domain@20ý4power-domain@21ý®Q(hdmi_txpower-domain@28ý®$$  (img-0img-14+power-domain@29ýpower-domain@30ý®$%(ipeipe-0ipe-14power-domain@31ý(®&&&&&(cam-0cam-1cam-2cam-3cam-44+power-domain@32ý power-domain@33ý!power-domain@34ý"power-domain@0ý4power-domain@1ý4power-domain@2ýpower-domain@3ýpower-domain@4ý®57(csi_rx_topcsi_rx_top1power-domain@5ý®' (etherpower-domain@6ý®Xn (adspadsp1+4power-domain@7ý ®g"n2(audioaudio1audio2audio34watchdog@10007000mediatek,mt8195-wdtFýpoÎ-syscon@1000c000"mediatek,mt8195-apmixedsyssysconýÀ¡Îtimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerýp[ ®(pwrap@10024000mediatek,mt8195-pwrapsysconý@|pwrap[ó® (spiwrap^$nËpmicmediatek,mt6359Q) …Þadcmediatek,mt6359-auxadc™mt6359codecregulatorsmediatek,mt6359-regulatorbuck_vs1«vs1º 5Ò!‘Àêbuck_vgpu11«vgpu11º€Ò7ˆêÈ /buck_vmodem«vmodemº€ÒÈà*êÈbuck_vpu«vpuº€Ò7ˆêÈ /buck_vcore«vcoreº€ÒÖ ˆêÈ /buck_vs2«vs2º 5Òjêbuck_vpa«vpaº¡ Ò7±Ðê,buck_vproc2«vproc2º€Ò7LêÈ /buck_vproc1«vproc1º€Ò7LêÈ /buck_vcore_sshub «vcore_sshubº€Ò7buck_vgpu11_sshub «vgpu11_sshubº€Ò7ldo_vaud18«vaud18ºw@Òw@êðldo_vsim1«vsim1ºð Ò/M`ldo_vibr«vibrºO€Ò2Z ldo_vrf12«vrf12ºÈàÒÖ ldo_vusb«vusbº-ÆÀÒ-ÆÀêÀÎ<ldo_vsram_proc2 «vsram_proc2º¡ Ò½¶Lêðldo_vio18«vio18ºð ÒýàêÀldo_vcamio«vcamioºð Òýàldo_vcn18«vcn18ºw@Òw@êðldo_vfe28«vfe28º*¹€Ò*¹€êxldo_vcn13«vcn13º » ÒÖ ldo_vcn33_1_bt «vcn33_1_btº*¹€Ò5gàldo_vcn33_1_wifi «vcn33_1_wifiº*¹€Ò5gàldo_vaux18«vaux18ºw@Òw@êðldo_vsram_others «vsram_othersº¡ Ò½¶ˆêðldo_vefuse«vefuseºð Ò„€ldo_vxo22«vxo22ºw@Ò!‘Àldo_vrfck«vrfckºã`Òð ldo_vrfck_1«vrfckºëÀÒjldo_vbif28«vbif28º*¹€Ò*¹€êðldo_vio28«vio28º*¹€Ò2Z ldo_vemc«vemcº,@ Ò2Z ldo_vemc_1«vemcº&% Ò2Z Î@ldo_vcn33_2_bt «vcn33_2_btº*¹€Ò5gàldo_vcn33_2_wifi «vcn33_2_wifiº*¹€Ò5gàldo_va12«va12ºO€ÒÖ ldo_va09«va09º 5ÒO€ldo_vrf18«vrf18ºð ÒžPldo_vsram_md «vsram_mdº¡ Ò½¶*êðldo_vufs«vufsºð ÒýàÎAldo_vm18«vm18ºð Òýàldo_vbbck«vbbckºÈàÒO€ldo_vsram_proc1 «vsram_proc1º¡ Ò½¶Lêðldo_vsim2«vsim2ºð Ò/M`ldo_vsram_others_sshub«vsram_others_sshubº¡ Ò½¶rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi ýp� |pmifspmimst®E((pmif_sys_ckpmif_tmr_ckspmimst_clk_mux^$nËinfra-iommu@10315000mediatek,mt8195-iommu-infraý1PPP[GÎJmailbox@10320000mediatek,mt8195-gceý2@[âT®΃mailbox@10330000mediatek,mt8195-gceý3@[äT®Îascp@10500000mediatek,mt8195-scp0ýPrp€|sramcfgl1tcm[Î kdisabledÎbclock-controller@10720000mediatek,mt8195-scp_adspýr¡Î)dsp@10803000mediatek,mt8195-dsp ý€0„ |cfgsram,®XnŠ)#K(adsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h`*nrxtxy+, kdisabledmailbox@10816000mediatek,mt8195-adsp-mboxTý�`[¾Î+mailbox@10817000mediatek,mt8195-adsp-mboxTý�p[¿Î,mt8195-afe-pcm@10890000mediatek,mt8195-audioý‰€`*[6’- ™audiosys”®ÚÛÜÝßg"#neabcd2)ó(clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp kdisabledÎserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uartý[� ® (baudbuskokay¥default³.serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uartý[Ž ® (baudbuskokay¥default³/serial@11001300*mediatek,mt8195-uartmediatek,mt6577-uartý[� ® (baudbus kdisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uartý[Ó ® (baudbus kdisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uartý[Ô ® (baudbus kdisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uartý[Õ ® (baudbus kdisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadcý ®(main™ kdisabledsyscon@11003000"mediatek,mt8195-pericfg_aosysconý0¡Î'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+ý [¿®™(parent-clksel-clkspi-clk kdisabledthermal-sensor@1100b000mediatek,mt8195-lvts-apý° [©®’½01$Élvts-calib-data-1lvts-calib-data-2ÚΞsvs@1100bc00mediatek,mt8195-svsý¼[Ç®(main½20(Ésvs-calibration-datat-calibration-data’™svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmýà[Ë`*ð®*0(mainmm kdisabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwmýð[ð®+N(mainmm kdisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+ý[À®™3(parent-clksel-clkspi-clk kdisabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ý [Á®™4(parent-clksel-clkspi-clk kdisabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+ý0[®™5(parent-clksel-clkspi-clk kdisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+ý€[î™<(parent-clksel-clkspi-clk kdisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+ý�[Ä®™=(parent-clksel-clkspi-clk kdisabledspi@1101d000mediatek,mt8195-spi-slaveýÐ[Å®R(spi^n˜ kdisabledspi@1101e000mediatek,mt8195-spi-slaveýà[Æ®S(spi^n˜ kdisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10aý@[Ìûmacirq.(axiapbmac_mainptp_refrmii_internalmac_cg0®''RST' ^RSTnÂÃÄ`* 3,4?5R]hkokay urgmii-id~6 ‰] ™'8€¥defaultsleep³7®8mdiosnps,dwmac-mdio+ethernet-phy@1ýÎ6stmmac-axi-config¸ÈØÎ3rx-queues-configâøÎ4queue0 queue1 queue2 queue3 tx-queues-config4JÎ5queue0\ hqueue1\ hqueue2\ hqueue3\ husb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 ý -ÿ > |macippc ?+[€®/íB(sys_ckref_ckmcu_ckv9:{ ‰;gkokay <usb@0'mediatek,mt8195-xhcimediatek,mtk-xhciý|mac[�^,-n––$®/íB$(sys_ckref_ckmcu_ckdma_ckxhci_ckkokay®=mmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc ý#õ[ƒ®(sourcehclksource_cgkokay¥defaultstate_uhs³>®?ºÄ ëÂÒäó!L0@<AImmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc ý$Ç[‡®$(sourcehclksource_cg^n¿kokay¥defaultstate_uhs³B®C W�ºÄ ëÂ`q~0D<Emmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc ý%æ[ˆ® I(sourcehclksource_cg^ n¿ kdisabledthermal-sensor@11278000mediatek,mt8195-lvts-mcuý'€[ª®’½01$Élvts-calib-data-1lvts-calib-data-2ÚΕusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ý))> |macippc[vFG^./n––$®'ï'$(sys_ckref_ckmcu_ckdma_ckxhci_ck ‰;h{kokay <usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 ý*-ÿ*> |macippc*?+[^0n–®'ñ'(sys_ckref_ckmcu_ckvH{ ‰;ikokay <usb@0'mediatek,mt8195-xhcimediatek,mtk-xhciý|mac[^1n–®'(sys_ckkokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 ý+-ÿ+> |macippc+?+[^2n–®'ó' (sys_ckref_ckmcu_ckvI{ ‰;jkokay <usb@0'mediatek,mt8195-xhcimediatek,mtk-xhciý|mac[^3n–®' (sys_ckkokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcieñpci+ý/@ |pcie-mac[Œÿ8� ‚ à–J 0®V#&+K'/(pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem^GnvK ¯pcie-phy`*)¹`ÌLLLL kdisabledinterrupt-controllerQ)ÎLpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcieñpci+ý/€@ |pcie-mac[Œÿ8�$$ ‚$ $ à–J (®WXQ'/(pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem^HnvG ¯pcie-phy`*)¹`ÌMMMM kdisabledinterrupt-controllerQ)ÎMspi@1132c000(mediatek,mt8195-normediatek,mt8173-norý2À[9®o'' (spisfaxi+ kdisabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuseýÁ+usb3-tx-imp@184,1ý„ÚÎWusb3-rx-imp@184,2ý„ÚÎVusb3-intr@185ý…ÚÎUusb3-tx-imp@186,1ý†ÚÎTusb3-rx-imp@186,2ý†ÚÎSusb3-intr@187ý‡ÚÎRusb2-intr-p0@188,1ýˆÚusb2-intr-p1@188,2ýˆÚusb2-intr-p2@189,1ý‰Úusb2-intr-p3@189,2ý‰Úpciephy-rx-ln1@190,1ý�ÚÎ^pciephy-tx-ln1-nmos@190,2ý�ÚÎ]pciephy-tx-ln1-pmos@191,1ý‘ÚÎ\pciephy-rx-ln0@191,2ý‘ÚÎ[pciephy-tx-ln0-nmos@192,1ý’ÚÎZpciephy-tx-ln0-pmos@192,2ý’ÚÎYpciephy-glb-intr@193ý“ÚÎXdp-data@1acý¬Δlvts1-calib@1bcý¼Î0lvts2-calib@1d0ýÐ8Î1svs-calib@580ý€dÎ2socinfo-data1@7a0ý t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Äkokayusb-phy@0ý®ò(refßÎHt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Åkokayusb-phy@0ý®ô(refßÎIdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txýÈ® Êmipi_tx0_pll¡ß kdisabled΄dsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-txýÉ® Êmipi_tx1_pll¡ß kdisabledÎ…i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýÐ"€€[šµ®N; (maindma+ kdisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýÐ"€[›µ®N; (maindma+kokay#€³O¥defaultpmic@34mediatek,mt6360ý4Q) …eûIRQBchargermediatek,mt6360-chgêÝ@ usb-otg-vbus-regulator «usb-otg-vbusºC…(ÒXáèÎ=regulatormediatek,mt6360-regulator Pbuck1 «mt6360,buck1º“àÒÖ  /buck2 «mt6360,buck2º“àÒÖ  /ÎPldo1 «mt6360,ldo1ºO€Ò6î€/ldo2 «mt6360,ldo2ºO€Ò6î€/ldo3 «mt6360,ldo3ºO€Ò6î€/ÎEldo5 «mt6360,ldo5º)2àÒ6î€/ÎDldo6 «mt6360,ldo6º¡ Ò /ldo7 «mt6360,ldo7º¡ Ò /i2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýÐ "€€[œµ®N; (maindma+ kdisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_sýÐ0¡ÎNi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýà"€€[�µ®Q; (maindma+ kdisabledi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýà"€[“µ®Q; (maindma+ kdisabledi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ýà "€€[–µ®Q; (maindma+ kdisabledi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 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