Ð þí¾�8µ$( ]´ì(mediatek,mt8183-pumpkinmediatek,mt8183 +7Pumpkin MT8183aliases=/soc/i2c@11007000B/soc/i2c@11011000G/soc/i2c@11009000L/soc/i2c@1100f000Q/soc/i2c@11008000V/soc/i2c@11016000[/soc/i2c@11005000`/soc/i2c@1101a000e/soc/i2c@1101b000j/soc/i2c@11014000o/soc/i2c@11015000u/soc/i2c@11017000{/soc/ovl@14008000€/soc/ovl@14009000ˆ/soc/ovl@1400a000�/soc/rdma@1400b000–/soc/rdma@1400c000œ/soc/serial@11002000opp-table-cluster0operating-points-v2¤¯opp0-793000000·/D8@¾ ëÌopp0-910000000·6=€¾ }ŒÌopp0-1014000000·Ìopp0-1417000000·Tu´@¾ øPÌopp0-1508000000·YâA¾ AŽÌ opp0-1586000000·^ˆp€¾ £6Ì opp0-1625000000·`Ûˆ@¾ Ô Ì opp0-1677000000·côý@¾5²Ì opp0-1716000000·fH¾f†Ì opp0-1781000000·j'ç@¾à˜Ìopp0-1846000000·n¹€¾B@Ìopp0-1924000000·r­é¾£èÌopp0-1989000000·v�»@¾�Ìopp-table-cluster1operating-points-v2¤¯$opp1-793000000·/D8@¾ ®`Ìopp1-910000000·6=€¾ Ìopp1-1014000000·¯opp-689000000·)N@¾ øP¯opp-767000000·-·}À¾ Aޝ opp-845000000·2]­@¾ £6¯ opp-871000000·3êgÀ¾ Ô ¯ opp-923000000·7ÜÀ¾5²¯ opp-962000000·9Vô€¾f†¯ opp-1027000000·=6ÆÀ¾à˜¯opp-1092000000·A™¾B@¯opp-1144000000·D0¾£è¯opp-1196000000·GIƒ¾�¯ccimediatek,mt8183-cciÚ�ácciintermediateí¯!cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3cpu@0cpuarm,cortex-a53psci#å6Ú�ácpuintermediateíFT`€m@Œ€™@«€¸ ÉØ!å"¯cpu@1cpuarm,cortex-a53psci#å6Ú�ácpuintermediateíFT`€m@Œ€™@«€¸ ÉØ!å"¯cpu@2cpuarm,cortex-a53psci#å6Ú�ácpuintermediateíFT`€m@Œ€™@«€¸ ÉØ!å"¯cpu@3cpuarm,cortex-a53psci#å6Ú�ácpuintermediateíFT`€m@Œ€™@«€¸ ÉØ!å"¯cpu@100cpuarm,cortex-a73psci#6#Ú�ácpuintermediateí$FÓ`m@Œ™@«¸%ÉØ!å&¯cpu@101cpuarm,cortex-a73psci#6#Ú�ácpuintermediateí$FÓ`m@Œ™@«¸%ÉØ!å&¯cpu@102cpuarm,cortex-a73psci#6#Ú�ácpuintermediateí$FÓ`m@Œ™@«¸%ÉØ!å&¯cpu@103cpuarm,cortex-a73psci#6#Ú�ácpuintermediateí$FÓ`m@Œ™@«¸%ÉØ!å&¯idle-statesñpscicpu-sleeparm,idle-stateþ&È7ÈG ¯cluster-sleep-0arm,idle-stateþ&ú7�Gè¯cluster-sleep-1arm,idle-stateþ&ú7�G¯#l2-cache0cacheXbo@�d¯ l2-cache1cacheXbo@�d¯%opp-table-0operating-points-v2¤¯_opp-300000000·á£¾ ‰hopp-320000000·Ð¾ ¡Òopp-340000000·Cý¾ º<opp-360000000·u*¾ Ò¦opp-380000000·¦W¾ ëopp-400000000·ׄ¾ zopp-420000000·±¾ äopp-460000000·k ¾ L¸opp-500000000·Íe¾ }Œopp-540000000· /¿¾ ®`opp-580000000·"’¾ ß4opp-620000000·$ôs¾ opp-653000000·&ëý@¾ YFopp-698000000·)𢀾 ºîopp-743000000·,IGÀ¾ –opp-800000000·/¯¾ –¨pmu-a53arm,cortex-a53-pmu 'r(pmu-a73arm,cortex-a73-pmu 'r)psci arm,psci-1.0smcfixed-factor-clock-13mfixed-factor-clock}Ú*Š”Ÿclk13m¯6oscillator fixed-clock}²Œº€Ÿclk26m¯*timerarm,armv8-timer '@r   soc+ simple-busÂefuse@8000000%mediatek,mt8183-efusemediatek,efuse+ Édisabledinterrupt-controller@c000000 arm,gic-v3Ð 'áP   @ A B r ¯'ppi-partitionsinterrupt-partition-0ö¯(interrupt-partition-1ö¯)syscon@c530000mediatek,mt8183-mcucfgsyscon S}¯interrupt-controller@c530a80.mediatek,mt8183-sysirqmediatek,mt6577-sysirqáÐ ' S €P¯cpu-debug@d410000&arm,coresight-cpu-debugarm,primecell AÚ+. áapb_pclkcpu-debug@d510000&arm,coresight-cpu-debugarm,primecell QÚ+. áapb_pclkcpu-debug@d610000&arm,coresight-cpu-debugarm,primecell aÚ+. áapb_pclkcpu-debug@d710000&arm,coresight-cpu-debugarm,primecell qÚ+. áapb_pclkcpu-debug@d810000&arm,coresight-cpu-debugarm,primecell �Ú+. áapb_pclkcpu-debug@d910000&arm,coresight-cpu-debugarm,primecell ‘Ú+. áapb_pclkcpu-debug@da10000&arm,coresight-cpu-debugarm,primecell ¡Ú+. áapb_pclkcpu-debug@db10000&arm,coresight-cpu-debugarm,primecell ±Ú+. áapb_pclksyscon@10000000 mediatek,mt8183-topckgensyscon}¯syscon@10001000 mediatek,mt8183-infracfgsyscon}ÿ¯+syscon@10003000mediatek,mt8183-pericfgsyscon0}¯Rpinctrl@10005000mediatek,mt8183-pinctrl PòèçéÓÒÅó°D iocfg0iocfg1iocfg2iocfg3iocfg4iocfg5iocfg6iocfg7iocfg8eint&2,Àá r±Ð¯,i2c0¯Epins_i2c>RSEi2c1¯Npins_i2c>QTEi2c2¯Gpins_i2c>ghEi2c3¯Mpins_i2c>23Ei2c4¯Fpins_i2c>ijEi2c5¯Opins_i2c>01Ei2c6¯>pins_cmd_dat>qrEkeyboard¯4pins_keyboard >[\]mmc0-pins-default¯Upins_cmd_dat$>{€}„~�‚zZgEpins_clk>|gv pins_rst>…gvmmc0-pins-uhs¯Vpins_cmd_dat$>{€}„~�‚zZgEpins_clk>|gv pins_ds>ƒgv pins_rst>…gEmmc1-pins-default¯Ypins_cmd_dat> "!ZE pins_clk>Zv pins_pmu>²�mmc1-pins-uhs¯Zpins_cmd_dat> "!gZE pins_clk>gv Zite-pins¯?pins-irq>Z™pins-rst> �dpi-func-pins¯cpins-dpiL> ./ dpi-idle-pins¯dpins-idleL> ./ syscon@10006000)mediatek,mt8183-scpsyssysconsimple-mfd`power-controller!mediatek,mt8183-power-controller+¦¯Lpower-domain@0Ú +/+7áaudioaudio1audio2¦power-domain@1º+¦power-domain@2+¦power-domain@3+¦Ì-power-domain@4¦power-domain@5¦power-domain@6º+¦power-domain@7XÚ.......... 5ámmmm-0mm-1mm-2mm-3mm-4mm-5mm-6mm-7mm-8mm-9º+Ú/+¦power-domain@8@Ú00 00000.ácamcam-0cam-1cam-2cam-3cam-4cam-5cam-6º+Ú/¦power-domain@9 Ú"1 1áispisp-0isp-1º+Ú/¦power-domain@10 Ú/¦power-domain@11 Ú/¦power-domain@12 @Ú&#222222-ávpuvpu1vpu-0vpu-1vpu-2vpu-3vpu-4vpu-5º+Ú/+¦power-domain@13 Ú$ávpu2º+¦power-domain@14Ú%ávpu3º+¦watchdog@10007000mediatek,mt8183-wdtpÿ¯Ssyscon@1000c000"mediatek,mt8183-apmixedsyssysconÀ}¯Ipwrap@1000d000mediatek,mt8183-pwrapÐ pwrap r¹Ú)+ áspiwrappmicmediatek,mt6358áÐ ç,¶adcmediatek,mt6358-auxadcûaudio-codecmediatek,mt6358-sound regulatorsmediatek,mt6358-regulatorbuck_vdram1 vdram1/¡ GÚL_0Ôt�¤buck_vcore vcore/¡ G½¶_jtÈ�¤buck_vpa vpa/¡ G7±Ð_ÃPtú¤buck_vproc11 vproc11/¡ G½¶_jtÈ�¤¯&buck_vproc12 vproc12/¡ G½¶_jtÈ�¤¯"buck_vgpu vgpu/ ‰hG » _jtȤ¼3Ó† ¯-buck_vs2 vs2/¡ GÚL_0Ôt�buck_vmodem vmodem/¡ G½¶_jt„�¤buck_vs1 vs1/B@G'{l_0Ôt�ldo_vdram2 vdram2/ 'ÀGw@t äldo_vsim1 vsim1/ð G/M`tldo_vibr vibr/O€G2Z t<ldo_vrf12 vrf12/O€GO€tx¯Bldo_vio18 vio18/w@Gw@t Œ�¯Xldo_vusb vusb/-ÆÀG/M`t�ldo_vcamio vcamio/w@Gw@tEldo_vcamd vcamd/ » Gw@tEldo_vcn18 vcn18/w@Gw@t¯Aldo_vfe28 vfe28/*¹€G*¹€tldo_vsram_proc11  vsram_proc11/¡ G½¶_jtð�ldo_vcn28 vcn28/*¹€G*¹€tldo_vsram_others  vsram_others/¡ G½¶_jtð�ldo_vsram_gpu  vsram_gpu/ øPGB@_jtð¼-Ó† ¯3ldo_vxo22 vxo22/!‘ÀG!‘Àtx�ldo_vefuse vefuse/ð Gýàtldo_vaux18 vaux18/w@Gw@tldo_vmch vmch/,@ G2Z t<¯[ldo_vbif28 vbif28/*¹€G*¹€tldo_vsram_proc12  vsram_proc12/¡ G½¶_jtð�ldo_vcama1 vcama1/w@G-ÆÀtEldo_vemc vemc/,@ G2Z t<¯Wldo_vio28 vio28/*¹€G*¹€tldo_va12 va12/O€GO€t�ldo_vrf18 vrf18/w@Gw@txldo_vcn33 vcn33/2Z G5gàt¯@ldo_vcama2 vcama2/w@G-ÆÀtEldo_vmc vmc/w@G2Z t<¯\ldo_vldo28 vldo28/*¹€G-ÆÀtldo_vaud28 vaud28/*¹€G*¹€tldo_vsim2 vsim2/ð G/M`trtcmediatek,mt6358-rtckeysmediatek,mt6358-keyspowerðtÿhomeðfkeyboard@10010000.mediatek,mt8183-keypadmediatek,mt6779-keypad rºÚ*ákpdÉokay default4%rs2BU gscp@10500000mediatek,mt8183-scp P\�€  sramcfg r®Ú+ámain5Éokay¯ftimer@10017000,mediatek,mt8183-timermediatek,mt6765-timerp rÈÚ6iommu@10205000mediatek,mt8183-m4u P r¦�789:;<=œ¯amailbox@10238000mediatek,mt8183-gce#€@ r¢©Ú+ágce¯`auxadc@11001000.mediatek,mt8183-auxadcmediatek,mt8173-auxadcÚ+#ámainûÉokay¯Hserial@11002000*mediatek,mt8183-uartmediatek,mt6577-uart  r[ Ú*+ ábaudbusÉokayserial@11003000*mediatek,mt8183-uartmediatek,mt6577-uart0 r\ Ú*+ ábaudbus Édisabledserial@11004000*mediatek,mt8183-uartmediatek,mt6577-uart@ r] Ú*+ ábaudbus Édisabledi2c@11005000mediatek,mt8183-i2c P€ rWÚ+W+* ámaindmaŠ+Éokay default>²† hdmitx@4c ite,it66121L default? µ,  ,rÁ@ÎAÛBports+port@0endpointè òC¯eport@1endpointòD¯ki2c@11007000mediatek,mt8183-i2c p€€ rQÚ+ +* ámaindmaŠ+Éokay defaultE²† i2c@11008000mediatek,mt8183-i2c €€ rRÚ+ +*+G ámaindmaarbŠ+Éokay defaultF²† i2c@11009000mediatek,mt8183-i2c �€€ rSÚ+ +*+I ámaindmaarbŠ+Éokay defaultG²† spi@1100a000mediatek,mt8183-spi+  rxÚ6+áparent-clksel-clkspi-clk Édisabledthermal-sensor@1100b000mediatek,mt8183-thermal° Ú+ +# áthermauxadc+ rLH/ICJOcalibration-data¯isvs@1100bc00mediatek,mt8183-svs¼ rÚ+ ámainCKJ(Osvs-calibration-datat-calibration-datapwm@1100e000mediatek,mt8183-disp-pwmà r€`LnÚ+5ámainmmpwm@11006000mediatek,mt8183-pwm`n0Ú++++++átopmainpwm1pwm2pwm3pwm4i2c@1100f000mediatek,mt8183-i2c ð€ rTÚ+ +* ámaindmaŠ+Éokay defaultM²† spi@11010000mediatek,mt8183-spi+ r|Ú6+8áparent-clksel-clkspi-clk Édisabledi2c@11011000mediatek,mt8183-i2c €€ rUÚ+9+* ámaindmaŠ+Éokay defaultN²† spi@11012000mediatek,mt8183-spi+  r�Ú6+;áparent-clksel-clkspi-clk Édisabledspi@11013000mediatek,mt8183-spi+0 r‚Ú6+<áparent-clksel-clkspi-clk Édisabledi2c@11014000mediatek,mt8183-i2c @€€ rƒÚ+H+*+G ámaindmaarbŠ+ Édisabledi2c@11015000mediatek,mt8183-i2c P€ r„Ú+J+*+I ámaindmaarbŠ+ Édisabledi2c@11016000mediatek,mt8183-i2c `€ rVÚ+D+*+E ámaindmaarbŠ+Éokay defaultO²† i2c@11017000mediatek,mt8183-i2c p€€ r…Ú+F+*+E ámaindmaarbŠ+ Édisabledspi@11018000mediatek,mt8183-spi+€ r†Ú6+Káparent-clksel-clkspi-clk Édisabledspi@11019000mediatek,mt8183-spi+� r‡Ú6+Láparent-clksel-clkspi-clk Édisabledi2c@1101a000mediatek,mt8183-i2c  €€ rXÚ+b+* ámaindmaŠ+ Édisabledi2c@1101b000mediatek,mt8183-i2c °€ rYÚ+c+* ámaindmaŠ+ Édisabledusb@11201000#mediatek,mt8183-mtu3mediatek,mtu3  . >  macippc rHyPQÚ+=+Zásys_ckref_ck ~R e+ Édisabledusb@11200000'mediatek,mt8183-xhcimediatek,mtk-xhci  mac rIÚ+=+Zásys_ckref_ck Édisabledaudio-controller@11220000 mediatek,mt8183-audiosyssyscon"}¯Tmt8183-afe-pcmmediatek,mt8183-audio r¡S •audiosys`LDÚTTTTT TTTTT T T T TT+/+7  0HLKOtuvwxyz{|}~*wáaud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adc_adda6_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_i2s1_bclk_swaud_i2s2_bclk_swaud_i2s3_bclk_swaud_i2s4_bclk_swaud_tdm_clkaud_tml_clkaud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_aud_intbustop_syspll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_clk26m_clkmmc@11230000mediatek,mt8183-mmc #õ rMÚ++ásourcehclksource_cgÉokay defaultstate_uhsU¡Vè« ë¹ËÚéú(W#X0@UWmmc@11240000mediatek,mt8183-mmc $á rNÚ ++(ásourcehclksource_cgÉokay defaultstate_uhsY¡Zè« ëÂevƒ‘ž[#\¥ÿWdsi-phy@11e50000mediatek,mt8183-mipi-txåÚI}» Ÿmipi_tx0_pllC]Ocalibration-data¯befuse@11f10000%mediatek,mt8183-efusemediatek,efuseñ+socinfo-data1@4cLsocinfo-data2@60`calib@180€ ¯Jcalib@190� ¯]calib@580€d¯Kt-phy@11f40000.mediatek,mt8183-tphymediatek,generic-tphy-v2+ÂôÉokayusb-phy@0Ú*áref»ÆÉokay¯Pusb-phy@700 Ú*áref»Éokay¯Qsyscon@13000000mediatek,mt8183-mfgcfgsyscon}`L¯^gpu@13040000'mediatek,mt8183b-maliarm,mali-bifrost@$r ÖjobmmugpuÚ^`LLLæcore0core1core2í_ù-syscon@14000000mediatek,mt8183-mmsyssyscon}ÿ`` `¯.dma-controller0@14001000mediatek,mt8183-mdp3-rdma `$`LÚ. .8a ``?mdp3-rsz0@14003000mediatek,mt8183-mdp3-rsz0 `0$Ú.mdp3-rsz1@14004000mediatek,mt8183-mdp3-rsz@ `@$Ú.dma-controller@14005000mediatek,mt8183-mdp3-wrotP `P$!`LÚ.8a?mdp3-wdma@14006000mediatek,mt8183-mdp3-wdma` ``$"`LÚ.)8aovl@14008000mediatek,mt8183-disp-ovl€ rá`LÚ.8a `€ovl@14009000mediatek,mt8183-disp-ovl-2l� râ`LÚ.8a `�ovl@1400a000mediatek,mt8183-disp-ovl-2l  rã`LÚ.8a ` rdma@1400b000mediatek,mt8183-disp-rdma° rä`LÚ.8aJ `°rdma@1400c000mediatek,mt8183-disp-rdmaÀ rå`LÚ.8aJ `Àcolor@1400e0006mediatek,mt8183-disp-colormediatek,mt8173-disp-colorà rç`LÚ. `àccorr@1400f000mediatek,mt8183-disp-ccorrð rè`LÚ. `ðaal@14010000mediatek,mt8183-disp-aal ré`LÚ. `gamma@14011000mediatek,mt8183-disp-gamma rê`LÚ. `dither@14012000mediatek,mt8183-disp-dither  rë`LÚ. ` dsi@14014000mediatek,mt8183-dsi@ rì`LÚ.. báenginedigitalhs.ybbdphy Édisabledportendpointdpi@14015000mediatek,mt8183-dpiP rí`LÚ.".!IápixelenginepllÉokay defaultsleepc¡dportendpointòe¯Cmutex@14016000mediatek,mt8183-disp-mutex` rÙ`L$‚ƒ ``larb@14017000mediatek,mt8183-smi-larbpÚ/Ú..`Láapbsmi¯7smi@14019000mediatek,mt8183-smi-common� Ú....áapbsmigals0gals1`L¯/mdp3-ccorr@1401c000mediatek,mt8183-mdp3-ccorrÀ `À$1Ú.+syscon@15020000mediatek,mt8183-imgsyssyscon}¯1larb@15021000mediatek,mt8183-smi-larbÚ/Ú1 1 . áapbsmigals`L ¯<larb@1502f000mediatek,mt8183-smi-larbðÚ/Ú11.  áapbsmigals`L ¯9syscon@16000000mediatek,mt8183-vdecsyssyscon}¯gvideo-codec@16020000mediatek,mt8183-vcodec-dec° 0@Phpx„( miscldtopcmadavpphwdhwqhwbhwg rú88a a!a"a#a$a%a&lfyg`L Úgávdeclarb@16010000mediatek,mt8183-smi-larbÚ/Úggáapbsmi`L ¯8syscon@17000000mediatek,mt8183-vencsyssyscon}¯hlarb@17010000mediatek,mt8183-smi-larbÚ/Úhháapbsmi`L ¯;jpeg-encoder@17030000+mediatek,mt8183-jpgencmediatek,mtk-jpgenc rù8a…a†`L Úhájpgencsyscon@19000000 mediatek,mt8183-ipu_connsyscon}¯2syscon@19010000mediatek,mt8183-ipu_adlsyscon}syscon@19180000!mediatek,mt8183-ipu_core0syscon}syscon@19280000!mediatek,mt8183-ipu_core1syscon(}syscon@1a000000mediatek,mt8183-camsyssyscon}¯0larb@1a001000mediatek,mt8183-smi-larbÚ/Ú00. áapbsmigals`L¯=larb@1a002000mediatek,mt8183-smi-larb Ú/Ú0 0 . áapbsmigals`L¯:thermal-zonescpu-thermalŠd ô®i¾ˆtripstrip-point0Ð  ÜÐ passivetrip-point1Ð8€ÜÐ passive¯jcpu-critÐÁ8ÜÐ  criticalcooling-mapsmap0çj0ìÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿû map1çj0ìÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿûsoc-thermal èŠú®i¾ˆtripstrip-alertÐLÜÐ passivetrip-critІ ÜÐ  criticalgpu-thermal èŠú®i¾ˆtripstrip-alertÐLÜÐ passivetrip-critІ ÜÐ  criticalmd1-thermal èŠú®i¾ˆtripstrip-alertÐLÜÐ passivetrip-critІ ÜÐ  criticalcpu-little-thermal èŠú®i¾ˆtripstrip-alertÐLÜÐ passivetrip-critІ ÜÐ  criticalcpu-big-thermal èŠú®i¾ˆtripstrip-alertÐLÜÐ passivetrip-critІ ÜÐ  criticaltsabb-thermal èŠú®i¾ˆtripstrip-alertÐLÜÐ passivetrip-critІ ÜÐ  criticalmemory@40000000memory@€chosen serial0:921600n8reserved-memory+Âscp-mem@50000000shared-dma-poolP� ¯5leds gpio-ledsled-red red »,› !offled-green green »,œ !offthermistormurata,ncp03wf104 /w@ 9óp D QHconnectorhdmi-connector hdmi dportendpointòk¯D compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11ovl0ovl-2l0ovl-2l1rdma0rdma1serial0opp-sharedphandleopp-hzopp-microvoltrequired-oppsclocksclock-namesoperating-points-v2cpudevice_typeregenable-methodcapacity-dmips-mhzcpu-idle-statesdynamic-power-coefficienti-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,cciproc-supplyentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterrupts#clock-cellsclock-divclock-multclock-output-namesclock-frequencyrangesstatus#interrupt-cellsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxmediatek,pull-up-advinput-enabledrive-strengthmediatek,pull-down-advoutput-highbias-pull-up#power-domain-cellsmediatek,infracfgdomain-supplymediatek,smiinterrupts-extended#io-channel-cellsmediatek,dmic-moderegulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-always-onregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadlinux,keycodeswakeup-sourcepinctrl-namespinctrl-0linux,keymapkeypad,num-rowskeypad,num-columnsdebounce-delay-msmediatek,keys-per-groupmemory-regionmediatek,larbs#iommu-cells#mbox-cellsreset-gpiosvcn33-supplyvcn18-supplyvrf12-supplybus-widthremote-endpoint#thermal-sensor-cellsresetsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namespower-domains#pwm-cellsphysmediatek,syscon-wakeupreset-namespinctrl-1max-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplyassigned-clocksassigned-clock-parentsnon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104cap-sdio-irqno-mmckeep-power-in-suspend#phy-cellsmediatek,discthinterrupt-namespower-domain-namesmali-supplymboxesmediatek,gce-client-regmediatek,gce-eventsiommus#dma-cellsmediatek,rdma-fifo-sizephy-namesmediatek,scpmediatek,vdecsyspolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionstdout-pathno-maplabeldefault-statepullup-uvpullup-ohmpulldown-ohmio-channels