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#address-cells#size-cellsmodelcompatibleserial0serial1gpio0spi0gpio1gpio2spi1spi2spi3spi4ethernet0ethernet1ethernet2methodrangesregno-mapinterrupt-parentdma-coherent#iommu-cells#global-interruptsstatusphandle#interrupt-cellsinterrupt-controllermsi-controllerarm,msi-base-spiarm,msi-num-spismarvell,odmi-framesmarvell,spi-basemarvell,spi-rangesmsi-parentclocksreg-shiftreg-io-widthpinctrl-0pinctrl-namesclock-namesmarvell,xenon-phy-slow-modebus-widthno-1-8-vno-sdno-sdionon-removablevqmmc-supplymarvell,pinsmarvell,functionoffsetngpiosgpio-controller#gpio-cellsgpio-rangesmarvell,pwm-offset#pwm-cells#clock-cells#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistypetripcooling-devicedevice_typeenable-method#cooling-cellsi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecache-levelcache-unifiedmarvell,system-controllerinterrupt-namesport-idgop-port-idphy-modemanagedphyssfp#phy-cellsreg-namesgpio-hogoutput-highoutput-lowinterrupts-extendediommusclock-frequencybroken-cdbus-rangeinterrupt-map-maskinterrupt-mapnum-lanesiommu-mapiommu-map-maskreset-gpiosphy-namesphyphy-supplymarvell,reg-initreset-assert-usreset-deassert-uslabelphy-handleethernetspi-max-frequencystdout-pathcooling-levelspwmsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-ongpioi2c-busmod-def0-gpiostx-disable-gpiosmaximum-power-milliwattdefault-statelinux,can-disablelinux,code