Ð þíà²8×|( 6×D ',TQ-Systems i.MX8DXP TQMa8XDP on MBa8Xx;2tq,imx8dxp-tqma8xdp-mba8xxtq,imx8dxp-tqma8xdpfsl,imx8dxpaliases =/bus@5b000000/ethernet@5b040000 G/bus@5b000000/ethernet@5b050000Q/bus@5d000000/gpio@5d080000W/bus@5d000000/gpio@5d090000]/bus@5d000000/gpio@5d0a0000c/bus@5d000000/gpio@5d0b0000i/bus@5d000000/gpio@5d0c0000o/bus@5d000000/gpio@5d0d0000u/bus@5d000000/gpio@5d0e0000{/bus@5d000000/gpio@5d0f0000�/bus@5a000000/i2c@5a800000†/bus@5a000000/i2c@5a810000‹/bus@5a000000/i2c@5a820000�/bus@5a000000/i2c@5a830000•/bus@5b000000/mmc@5b010000š/bus@5b000000/mmc@5b020000Ÿ/bus@5b000000/mmc@5b030000¤/bus@5d000000/mailbox@5d1b0000¨/bus@5d000000/mailbox@5d1c0000¬/bus@5d000000/mailbox@5d1d0000°/bus@5d000000/mailbox@5d1e0000´/bus@5d000000/mailbox@5d1f0000¸/bus@5a000000/serial@5a060000À/bus@5a000000/serial@5a070000È/bus@5a000000/serial@5a080000Ð/bus@5a000000/serial@5a090000 Ø/vpu@2c000000/vpu-core@2d080000 â/vpu@2c000000/vpu-core@2d090000"ì/bus@5a000000/i2c@5a810000/rtc@51ñ/system-controller/rtccpus cpu@0öcpu2arm,cortex-a35psci€!@3@€M@_€l }û„˜§cpu@1öcpu2arm,cortex-a35psci€!@3@€M@_€l }û„˜§ l2-cache02cache¯»#@5§opp-table2operating-points-v2ɧopp-900000000Ô5¤éÛB@éIðopp-1200000000ÔG†ŒÛÈàéIðúinterrupt-controller@51a00000 2arm,gic-v3 Q Q°  , §reserved-memory 7decoder-boot@84000000„>§encoder-boot@86000000† >§decoder-rpc@92000000’>§dsp@92400000’@> Edisabledencoder-rpc@94400000”@p>§linux,cma2shared-dma-poolL U–0bpmu2arm,cortex-a35-pmu ,psci 2arm,psci-1.0 smcsystem-controller 2fsl,imx-scu ttx0rx0gip3$power-controller2fsl,imx8qxp-scu-pdfsl,scu-pd†§ clock-controller2fsl,imx8qxp-clkfsl,scu-clkš§pinctrl2fsl,imx8qxp-iomuxc§�flexspi0grp´§œM�MžMŸM M¡M£M¥M¦M§M¨M©MªM«M¬M§�lpi2c1grp§v!w!§Wlpi2c1gpiogrp§v!w!§Xusdhc1grp„§ A ! ! ! !!!!!!A§nusdhc1-100mhzgrp„§ @      @§ousdhc1-200mhzgrp„§ @      @§padc0grp0§d`c`f`e`§dadmapwmgrp §`!§Sbllvdsgrp §y!§’can0grp§o!p!§gcan1grp§r!q!§hethphy0grp§”@’@§{ethphy3grp§•@“@§}fec1grp¨§5A4A&@%@'@(@)@*@-@,@.@/@0@1@§yfec2grp�§9@7@?@@@8@:@;@B@A@>@=@<@§gpiobuttonsgrp§g h §•lpi2c2grp§z!{!§_lpi2c2gpiogrp§z!{!§`lpuart1grp§N M §Nlpuart3grp§m n §Qlsgpio3grp §¢!§Žpca9538grp § §\pcieagrp$§AAAregpcie1v5grp §W!§—regpcie3v3grp §X!§˜sai1grp<§LAiAjAkAlA§$spi1grp<§SARAUAT!V!§Espi2grp0§\A[AZAY!§Hspi3grp<§EAGAFAH!I!§Kusbotg1grp§!!§lusdhc2gpiogrp§!!§susdhc2grpT§A! !!!"!#!!§rusdhc2-100mhzgrpT§@ ! " #  §tusdhc2-200mhzgrpT§@ ! " #  §uocotp2fsl,imx8qxp-scu-ocotp keys"2fsl,imx8qxp-sc-keyfsl,imx-sc-key°t Edisabledrtc2fsl,imx8qxp-sc-rtcwatchdog"2fsl,imx8qxp-sc-wdtfsl,imx-sc-wdt¿<thermal-sensor*2fsl,imx8qxp-sc-thermalfsl,imx-sc-thermal˧timer2arm,armv8-timer0,   clock-dummy 2fixed-clockšá ñclk_dummy§clock-xtal32k 2fixed-clockšá€ ñxtal_32KHzclock-xtal24m 2fixed-clockšán6 ñxtal_24MHzthermal-zonescpu0-thermalúÐ(ctripstrip08sDÐýpassive§trip18† DÐ ýcriticalcooling-mapsmap0OTÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿpmic-thermalúÐ(ñtripstrip08­°DÐýpassive§ trip18èHDÐ ýcriticalcooling-mapsmap0O Tÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿclock-img-ipg 2fixed-clockšá ë ñimg_ipg_clk§bus@58000000 2simple-bus 7XXjpegdec@58400000X@ ,5} c s ë ëˆ  �2nxp,imx8qxp-jpgdecjpegenc@58450000XE ,1} c s ë ëˆ  …2nxp,imx8qxp-jpgencclock-controller@585d00002fsl,imx8qxp-lpcgX]š}–0ñimg_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clkˆ § clock-controller@585f00002fsl,imx8qxp-lpcgX_š}–0ñimg_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clkˆ § vpu@2c000000 7,,,ˆ Eokay2nxp,imx8qxp-vpumailbox@2d0000002fsl,imx6sx-mu- ,Õ¤ˆ Eokay§mailbox@2d0200002fsl,imx6sx-mu- ,Ö¤ˆ Eokay§vpu-core@2d080000-2nxp,imx8q-vpu-decoderˆ  ttx0tx1rx$Eokay°vpu-core@2d090000-2nxp,imx8q-vpu-encoderˆ  ttx0tx1rx$Eokay°clock-cm40-ipg 2fixed-clockšáÞ) ñcm40_ipg_clk§bus@34000000 2simple-bus 744serial@372200002fsl,imx8qxp-lpuart7",} ¾ipgbaud csn6ˆ  Edisabledi2c@37230000$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c7#, }¾peripg c sn6ˆ   Edisabledintmux@374000002fsl,imx-intmux7@`,}¾ipgˆ ! Edisabled§clock-controller@376200002fsl,imx8qxp-lpcg7bš}–*ñcm40_lpcg_uart_clkcm40_lpcg_uart_ipg_clkˆ §clock-controller@376300002fsl,imx8qxp-lpcg7cš} –(ñcm40_lpcg_i2c_clkcm40_lpcg_i2c_ipg_clkˆ  §bus@53000000 2simple-bus 7SSgpu@53100000 2vivante,gcS ,@}�� ¾coreshaderc��s)¹'2©ø€ˆ �clock-audio-ipg 2fixed-clockšá'ñaudio_ipg_clk§!clock-ext-aud-mclk0 2fixed-clockšáñext_aud_mclk0§4clock-ext-aud-mclk1 2fixed-clockšáñext_aud_mclk1§5clock-esai0-rx 2fixed-clockšá ñesai0_rx_clk§6clock-esai0-rx-hf 2fixed-clockšáñesai0_rx_hf_clk§7clock-esai0-tx 2fixed-clockšá ñesai0_tx_clk§8clock-esai0-tx-hf 2fixed-clockšáñesai0_tx_hf_clk§9clock-spdif0-rx 2fixed-clockšá ñspdif0_rx§:clock-sai0-rx-bclk 2fixed-clockšá ñsai0_rx_bclk§;clock-sai0-tx-bclk 2fixed-clockšá ñsai0_tx_bclk§<clock-sai1-rx-bclk 2fixed-clockšá ñsai1_rx_bclk§=clock-sai1-tx-bclk 2fixed-clockšá ñsai1_tx_bclk§>clock-sai2-rx-bclk 2fixed-clockšá ñsai2_rx_bclk§?clock-sai3-rx-bclk 2fixed-clockšá ñsai3_rx_bclk§@clock-sai4-rx-bclk 2fixed-clockšá ñsai4_rx_bclk§Abus@59000000 2simple-bus 7YYasrc@590000002fsl,imx8qm-asrcY ,td}�¾memipgasrck_0asrck_1asrck_2asrck_3asrck_4asrck_5asrck_6asrck_7asrck_8asrck_9asrck_aasrck_basrck_casrck_dasrck_easrck_fspba`ÊÏrxarxbrxctxatxbtxcÙ@çöˆ ž Edisabledesai@590100002fsl,imx8qm-esaiY ,™}¾coreextalfsysspba ÊÏrxtxˆ Ÿ Edisabledspdif@590200002fsl,imx8qm-spdifY,ÈÊ0}  !:¾corerxtx0rxtx1rxtx2rxtx3rxtx4rxtx5rxtx6rxtx7spba Ê Ïrxtxˆ   Edisabledsai@590400002fsl,imx8qm-saiY ,:}""¾busmclk0mclk1mclk2mclk3Ïrxtx Ê  ˆ > Edisabledsai@590500002fsl,imx8qm-saiY ,<}##¾busmclk0mclk1mclk2mclk3Ïrxtx ʈ ?Eokay,cEEE#s.àîdefault$§šsai@590600002fsl,imx8qm-saiY ,>}%%¾busmclk0mclk1mclk2mclk3Ïrxʈ @ Edisabledsai@590700002fsl,imx8qm-saiY ,C}&&¾busmclk0mclk1mclk2mclk3Ïrxʈ ¢ Edisableddma-controller@591f00002fsl,imx8qm-edmaY*7\  ,vwxyz{ššÉË;;==?D‡‰Àˆ @ A B C D E F G H I J K L M N O P Q R S T U V W§clock-controller@594000002fsl,imx8qxp-lpcgY@š}!–ñasrc0_lpcg_ipg_clkˆ ž§clock-controller@594100002fsl,imx8qxp-lpcgYAš }!–(ñesai0_lpcg_extal_clkesai0_lpcg_ipg_clkˆ Ÿ§clock-controller@594200002fsl,imx8qxp-lpcgYBš }!–%ñspdif0_lpcg_tx_clkspdif0_lpcg_gclkwˆ  § clock-controller@594400002fsl,imx8qxp-lpcgYDš } !–!ñsai0_lpcg_mclksai0_lpcg_ipg_clkˆ >§"clock-controller@594500002fsl,imx8qxp-lpcgYEš } !–!ñsai1_lpcg_mclksai1_lpcg_ipg_clkˆ ?§#clock-controller@594600002fsl,imx8qxp-lpcgYFš }!–!ñsai2_lpcg_mclksai2_lpcg_ipg_clkˆ @§%clock-controller@594700002fsl,imx8qxp-lpcgYGš }!–!ñsai3_lpcg_mclksai3_lpcg_ipg_clkˆ ¢§&clock-controller@595800002fsl,imx8qxp-lpcgYXš }!!! –4ñdsp_lpcg_adb_clkdsp_lpcg_ipg_clkdsp_lpcg_core_clkˆ §'clock-controller@595900002fsl,imx8qxp-lpcgYYš}!–ñdsp_ram_lpcg_ipg_clkˆ §(dsp@596e80002fsl,imx8qxp-dspYn€€}'('¾ipgocramcore ˆ â ë  ttxdb0txdb1rxdb0rxdb10)))) Edisabledasrc@598000002fsl,imx8qm-asrcY€ ,|d}**�¾memipgasrck_0asrck_1asrck_2asrck_3asrck_4asrck_5asrck_6asrck_7asrck_8asrck_9asrck_aasrck_basrck_casrck_dasrck_easrck_fspba`Ê++++++ÏrxarxbrxctxatxbtxcÙ@çöˆ Æ Edisabledsai@598200002fsl,imx8qm-saiY‚ ,I},,¾busmclk0mclk1mclk2mclk3 Ê++ Ïrxtxˆ £ Edisabled§/sai@598300002fsl,imx8qm-saiYƒ ,K}--¾busmclk0mclk1mclk2mclk3Ê+ Ïtxˆ ¤ Edisabled§0amix@598400002fsl,imx8qm-audmixY„}.¾ipgˆ ÊH/0 Edisabledmqs@598500002fsl,imx8qm-mqsY…}11 ¾mclkcoreˆ Ë Edisableddma-controller@599f00002fsl,imx8qm-edmaYŸ * 7À„,~€�‚ƒJJLXˆ l m n o p q r s t u v§+clock-controller@59d000002fsl,imx8qxp-lpcgYК }E–ñaud_rec_clk0_lpcg_clkˆ E§2clock-controller@59d100002fsl,imx8qxp-lpcgYÑš }ì–ñaud_rec_clk1_lpcg_clkˆ ì§3clock-controller@59d200002fsl,imx8qxp-lpcgYÒš }E–ñaud_pll_div_clk0_lpcg_clkˆ E§clock-controller@59d300002fsl,imx8qxp-lpcgYÓš }ì–ñaud_pll_div_clk1_lpcg_clkˆ ì§clock-controller@59d500002fsl,imx8qxp-lpcgYÕš}–ñmclkout0_lpcg_clkˆ ï§Zclock-controller@59d600002fsl,imx8qxp-lpcgYÖš}–ñmclkout1_lpcg_clkˆ ðacm@59e000002fsl,imx8qxp-acmYàšˆˆ í î ï ð E ì ž Æ Ÿ > ? @ ¢ £ ¤   ËX}23456789:;<=>?@A¾aud_rec_clk0_lpcg_clkaud_rec_clk1_lpcg_clkaud_pll_div_clk0_lpcg_clkaud_pll_div_clk1_lpcg_clkext_aud_mclk0ext_aud_mclk1esai0_rx_clkesai0_rx_hf_clkesai0_tx_clkesai0_tx_hf_clkspdif0_rxsai0_rx_bclksai0_tx_bclksai1_rx_bclksai1_tx_bclksai2_rx_bclksai3_rx_bclksai4_rx_bclk§clock-controller@59c000002fsl,imx8qxp-lpcgYÀš}!–ñasrc1_lpcg_ipg_clkˆ Ƨ*clock-controller@59c200002fsl,imx8qxp-lpcgYš }!–!ñsai4_lpcg_mclksai4_lpcg_ipg_clkˆ £§,clock-controller@59c300002fsl,imx8qxp-lpcgYÚ }!–!ñsai5_lpcg_mclksai5_lpcg_ipg_clkˆ ¤§-clock-controller@59c400002fsl,imx8qxp-lpcgYÄš}!–ñamix_lpcg_ipg_clkˆ ʧ.clock-controller@59c500002fsl,imx8qxp-lpcgYÅš }!–!ñmqs0_lpcg_mclkmqs0_lpcg_ipg_clkˆ ˧1clock-dma-ipg 2fixed-clockšá' ñdma_ipg_clk§Tbus@5a000000 2simple-bus 7ZZspi@5a0000002fsl,imx7ulp-spiZ  ,P}BB¾peripg c5s“‡ˆ 5 ÊCCÏtxrx Edisabledspi@5a0100002fsl,imx7ulp-spiZ  ,Q}DD¾peripg c6s“‡ˆ 6 ÊCCÏtxrxEokaydefaultEMFFspi@5a0200002fsl,imx7ulp-spiZ  ,R}GG¾peripg c7s“‡ˆ 7 ÊCCÏtxrxEokaydefaultH MIspi@5a0300002fsl,imx7ulp-spiZ  ,S}JJ¾peripg c8s“‡ˆ 8 ÊCCÏtxrxEokaydefaultKV MFserial@5a060000Z ,Y}LL ¾ipgbaud c9sÄ´ˆ 9Ïrxtx ÊCC  Edisabled2fsl,imx8qxp-lpuartserial@5a070000Z ,Z}MM ¾ipgbaud c:sÄ´ˆ :Ïrxtx ÊC C Eokay2fsl,imx8qxp-lpuartdefaultNserial@5a080000Z ,[}OO ¾ipgbaud c;sÄ´ˆ ;Ïrxtx ÊC C  Edisabled2fsl,imx8qxp-lpuartserial@5a090000Z  ,\}PP ¾ipgbaud c<sÄ´ˆ <Ïrxtx ÊCCEokay2fsl,imx8qxp-lpuartdefaultQpwm@5a1900002fsl,imx8qxp-pwmfsl,imx27-pwmZ ,}RR¾ipgper c¼sn6]ˆ ¼defaultS§“dma-controller@5a1f00002fsl,imx8qm-edmaZ*À, ¡¢£¤¥¦§²³´µ¶·¸¹€ˆ þ ÿ    « ¬ ­ ® ¯ ° ± ² ³ ´ µ§Cclock-controller@5a4000002fsl,imx8qxp-lpcgZ@š}5T– ñspi0_lpcg_clkspi0_lpcg_ipg_clkˆ 5§Bclock-controller@5a4100002fsl,imx8qxp-lpcgZAš}6T– ñspi1_lpcg_clkspi1_lpcg_ipg_clkˆ 6§Dclock-controller@5a4200002fsl,imx8qxp-lpcgZBš}7T– ñspi2_lpcg_clkspi2_lpcg_ipg_clkˆ 7§Gclock-controller@5a4300002fsl,imx8qxp-lpcgZCš}8T– ñspi3_lpcg_clkspi3_lpcg_ipg_clkˆ 8§Jclock-controller@5a4600002fsl,imx8qxp-lpcgZFš}9T–'ñuart0_lpcg_baud_clkuart0_lpcg_ipg_clkˆ 9§Lclock-controller@5a4700002fsl,imx8qxp-lpcgZGš}:T–'ñuart1_lpcg_baud_clkuart1_lpcg_ipg_clkˆ :§Mclock-controller@5a4800002fsl,imx8qxp-lpcgZHš};T–'ñuart2_lpcg_baud_clkuart2_lpcg_ipg_clkˆ ;§Oclock-controller@5a4900002fsl,imx8qxp-lpcgZIš}<T–'ñuart3_lpcg_baud_clkuart3_lpcg_ipg_clkˆ <§Pclock-controller@5a5900002fsl,imx8qxp-lpcgZYš}¼T–(ñadma_pwm_lpcg_clkadma_pwm_lpcg_ipg_clkˆ ¼§Ri2c@5a800000Z€@  ,Ü}UU¾peripg c`sn6ˆ ` Edisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000Z�@  ,Ý}VV¾peripg casn6ˆ aEokay$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2cᆠ defaultgpioWhX rI |Itemperature-sensor@1b2nxp,se97bjedec,jc-42.4-temprtc@512nxp,pcf85063aQ†Xeeprom@532nxp,se97batmel,24c02Sž§±Yeeprom@57 2atmel,24c64Wž ±Yaudio-codec@182ti,tlv320aic32x4}Z¾mclk¼[ÇY§™temperature-sensor@1c2nxp,se97bjedec,jc-42.4-tempeeprom@542nxp,se97batmel,24c02Tž±Ygpio@70 2nxp,pca9538pdefault\Ôä],±[3ðLED_ALED_BDSI_ENUSB_RESET#V_12V_ENPCIE_DIS#§–i2c@5a820000Z‚@  ,Þ}^^¾peripg cbsn6ˆ bEokay$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2cᆠ defaultgpio_h` rI |ai2c@5a830000Zƒ@  ,ß}bb¾peripg ccsn6ˆ c Edisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2cadc@5a8800002nxp,imx8qxp-adcZˆ ,ð}cc¾peripg cesn6ˆ eEokaydefaultd[§‘adc@5a8900002nxp,imx8qxp-adcZ‰ ,ñ}ee¾peripg cfsn6ˆ f Edisabledcan@5a8d00002fsl,imx8qm-flexcanZ� ,ë}ff¾ipgper cisbZˆ i-Eokaydefaultg;Ycan@5a8e00002fsl,imx8qm-flexcanZŽ ,ì}ff¾ipgper cisbZˆ j-Eokaydefaulth;Ycan@5a8f00002fsl,imx8qm-flexcanZ� ,í}ff¾ipgper cisbZˆ k- Edisableddma-controller@5a9f00002fsl,imx8qm-edmaZŸ *`,¨©ª«¬­®¯@ˆ Ì Í Î Ï Ð Ñ Ò Óclock-controller@5ac000002fsl,imx8qxp-lpcgZÀš}`T– ñi2c0_lpcg_clki2c0_lpcg_ipg_clkˆ `§Uclock-controller@5ac100002fsl,imx8qxp-lpcgZÁš}aT– ñi2c1_lpcg_clki2c1_lpcg_ipg_clkˆ a§Vclock-controller@5ac200002fsl,imx8qxp-lpcgZš}bT– ñi2c2_lpcg_clki2c2_lpcg_ipg_clkˆ b§^clock-controller@5ac300002fsl,imx8qxp-lpcgZÚ}cT– ñi2c3_lpcg_clki2c3_lpcg_ipg_clkˆ c§bclock-controller@5ac800002fsl,imx8qxp-lpcgZÈš}eT– ñadc0_lpcg_clkadc0_lpcg_ipg_clkˆ e§cclock-controller@5ac900002fsl,imx8qxp-lpcgZÉš}fT– ñadc1_lpcg_clkadc1_lpcg_ipg_clkˆ f§eclock-controller@5acd00002fsl,imx8qxp-lpcgZÍš}iTT –5ñcan0_lpcg_pe_clkcan0_lpcg_ipg_clkcan0_lpcg_chi_clkˆ i§fclock-conn-axi 2fixed-clockšáÞCU ñconn_axi_clk§„clock-conn-ahb 2fixed-clockšá ï!ª ñconn_ahb_clk§…clock-conn-ipg 2fixed-clockšá÷�Õ ñconn_ipg_clk§ƒclock-conn-bch 2fixed-clockšáׄ ñconn_bch_clkbus@5b000000 2simple-bus 7[[usb@5b0d0000-2fsl,imx7ulp-usbfsl,imx6ul-usbfsl,imx27-usb[  , JiUj}kar†ˆ Eokaydefaultl𦲾Ðèotgusbmisc@5b0d0200ð82fsl,imx7ulp-usbmiscfsl,imx7d-usbmiscfsl,imx6q-usbmisc[ §jusbphy@5b1000002fsl,imx7ulp-usbphy[}kˆ Eokay§immc@5b010000 ,è[}mmm ¾ipgahbperˆ øEokay"2fsl,imx8qxp-usdhcfsl,imx7d-usdhc"defaultstate_100mhzstate_200mhznhoýp[Y *8@mmc@5b020000 ,é[}qqq ¾ipgahbperˆ ùF[Eokay"2fsl,imx8qxp-usdhcfsl,imx7d-usdhc"defaultstate_100mhzstate_200mhzrshtsýus  k] t]v}8†mmc@5b030000 ,ê[}www ¾ipgahbperˆ ú Edisabled"2fsl,imx8qxp-usdhcfsl,imx7d-usdhcethernet@5b040000[0, }xxx x¾ipgahbenet_clk_refptpcûûsæ²€sY@�Ÿˆ ûEokay.2fsl,imx8qxp-fecfsl,imx8qm-fecfsl,imx6sx-fecdefaulty ±rgmii-idºzmdio ethernet-phy@02ethernet-phy-ieee802.3-c22default{ÅÚïýÿÿÿÿ -|9¡ IÃP[|,§zethernet-phy@32ethernet-phy-ieee802.3-c22default}ÅÚïýÿÿÿÿ -|9¡ IÃP[|,§€ethernet@5b050000[0, }~~~ ~¾ipgahbenet_clk_refptpcüüsæ²€sY@�Ÿˆ üEokay.2fsl,imx8qxp-fecfsl,imx8qm-fecfsl,imx6sx-fecdefault ±rgmii-idº€usb@5b1100002fsl,imx8qm-usb3[ 7(}�����¾lpmbusaclkipgcore csæ²€ˆ Eokayusb@5b120000 2cdns,usb3[[[ qotgxhcidev0,{hostperipheralotgwakeup‹‚�cdns3,usb3-phyšEokayèhostusb-phy@5b1600002nxp,salvo-phy[}�¾salvo_phy_clkˆ ±Eokay§‚clock-controller@5b2000002fsl,imx8qxp-lpcg[ š}øƒ„ –9ñsdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clkˆ ø§mclock-controller@5b2100002fsl,imx8qxp-lpcg[!š}ùƒ„ –9ñsdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clkˆ ù§qclock-controller@5b2200002fsl,imx8qxp-lpcg["š}úƒ„ –9ñsdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clkˆ ú§wclock-controller@5b2300002fsl,imx8qxp-lpcg[#š0}ûû„ûƒƒ– …ñenet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clkˆ û§xclock-controller@5b2400002fsl,imx8qxp-lpcg[$š0}üü„üƒƒ– …ñenet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clkˆ ü§~clock-controller@5b2700002fsl,imx8qxp-lpcg['š}…ƒ–"ñusboh3_ahb_clkusboh3_phy_ipg_clkˆ §kclock-controller@5b2800002fsl,imx8qxp-lpcg[(š–0}ƒƒƒMñusb3_app_clkusb3_lpm_clkusb3_ipg_clkusb3_core_pclkusb3_phy_clkusb3_aclkˆ §�clock-controller@5b2900002fsl,imx8qxp-lpcg[)š }  „„–'ñgpmi_bchgpmi_iogpmi_apbgpmi_bch_apbˆ  §‡clock-controller@5b2900042fsl,imx8qxp-lpcg[)š}„– ñapbhdma_hclkˆ  §†dma-controller@5b810000(2fsl,imx8qxp-dma-apbhfsl,imx28-dma-apbh[� 0,*}†ˆ  §ˆnand-controller@5b8120002fsl,imx8qxp-gpmi-nand[� [�@ qgpmi-nandbch  ,{bch }‡‡‡‡'¾gpmi_iogpmi_apbgpmi_bchgpmi_bch_apbʈÏrx-txˆ   c súð€ Edisabledbus@5c000000 2simple-bus 7\\ddr-pmu@5c0200002fsl,imx8-ddr-pmu\ ,ƒclock-lsio-bus 2fixed-clockšáõá ñlsio_bus_clk§�bus@5d000000 2simple-bus  7]]pwm@5d0000002fsl,imx27-pwm]¾ipgper}‰‰ c¿sn6] ,^ Edisabledpwm@5d0100002fsl,imx27-pwm]¾ipgper}ŠŠ cÀsn6] ,_ Edisabledpwm@5d0200002fsl,imx27-pwm]¾ipgper}‹‹ cÁsn6] ,` Edisabledpwm@5d0300002fsl,imx27-pwm]¾ipgper}ŒŒ cÂsn6] ,a Edisabledgpio@5d080000] ,ˆÔäˆ Ç 2fsl,imx8qxp-gpiofsl,imx35-gpioP¼�8 � E�K�P�R§Fgpio@5d090000]  ,‰Ôäˆ È 2fsl,imx8qxp-gpiofsl,imx35-gpio0¼�Y � c�t§Igpio@5d0a0000]  ,ŠÔäˆ É 2fsl,imx8qxp-gpiofsl,imx35-gpio0¼�{�~��§agpio@5d0b0000]  ,‹Ôäˆ Ê 2fsl,imx8qxp-gpiofsl,imx35-gpio0¼�’�— �¥defaultŽ%ðX4_15§|gpio@5d0c0000]  ,ŒÔäˆ Ë 2fsl,imx8qxp-gpiofsl,imx35-gpio€¼��� � ����%§]gpio@5d0d0000]  ,�Ôäˆ Ì 2fsl,imx8qxp-gpiofsl,imx35-gpio0¼�(�,� 3gpio@5d0e0000] ,ŽÔäˆ Í 2fsl,imx8qxp-gpiofsl,imx35-gpiogpio@5d0f0000] ,�Ôäˆ Î 2fsl,imx8qxp-gpiofsl,imx35-gpiospi@5d120000 2nxp,imx8qxp-fspi]qfspi_basefspi_mmap ,\}íí ¾fspi_enfspiˆ íEokaydefault�flash@02jedec,spi-norÈï€Úëpartitions2fixed-partitions mailbox@5d1b0000] ,°¤ Edisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1c0000] ,±¤-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mu§mailbox@5d1d0000] ,²¤ Edisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1e0000] ,³¤ Edisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1f0000] ,´¤ Edisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d200000]  ,¸¤ˆ Ú Edisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d210000]! ,¹¤ˆ Û Edisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d280000]( ,À¤ˆ â2fsl,imx8qxp-mufsl,imx6sx-mu§)clock-controller@5d4000002fsl,imx8qxp-lpcg]@š4}¿¿¿�¿–hñpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clkˆ ¿§‰clock-controller@5d4100002fsl,imx8qxp-lpcg]Aš4}ÀÀÀ�À–hñpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clkˆ À§Šclock-controller@5d4200002fsl,imx8qxp-lpcg]Bš4}ÁÁÁ�Á–hñpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clkˆ Á§‹clock-controller@5d4300002fsl,imx8qxp-lpcg]Cš4}ÂÂÂ�–hñpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clkˆ §Œclock-controller@5d4400002fsl,imx8qxp-lpcg]Dš4}ÃÃÃ�Öhñpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clkˆ Ãclock-controller@5d4500002fsl,imx8qxp-lpcg]Eš4}ÄÄÄ�Ä–hñpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clkˆ Äclock-controller@5d4600002fsl,imx8qxp-lpcg]Fš4}ÅÅÅ�Å–hñpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clkˆ Åclock-controller@5d4700002fsl,imx8qxp-lpcg]Gš4}ÆÆÆ�Æ–hñpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clkˆ Æmemory@80000000ömemory€@regulator-1v82regulator-fixedüV_1V8 w@#w@§[regulator-3v32regulator-fixedüV_3V3 2Z #2Z §Yadc 2iio-hwmon ;‘‘‘‘backlight-lvds2pwm-backlightdefault’G“LK@ L @€ÿ^w” „I Edisabledchosen‘/bus@5a000000/serial@5a070000gpio-keys 2gpio-keysdefault•�switch-a¨switcha® PI switch-b¨switchb® PIgpio-leds 2gpio-ledsled1¹¿status P– Èdefault-onled2¹ ¿heartbeat P– Èheartbeatregulator-12v02regulator-fixedüV_12V ·#· Þ–ã§”regulator-pcie-1v52regulator-fixedüMBA8XX_PCIE_1V5default— ã`#ã` ÞFöèãregulator-pcie-3v32regulator-fixedüMBA8XX_PCIE_3V3default˜ 2Z #2Z  ÞFöèã regulator-usdhc2-vmmc2regulator-fixed üV_3V3_MB 2Z #2Z §vsound2fsl,imx-audio-tlv320aic32x4,tqm-tlv320aic32 ™ 'š interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0ethernet1gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7i2c0i2c1i2c2i2c3mmc0mmc1mmc2mu0mu1mu2mu3mu4serial0serial1serial2serial3vpu-core0vpu-core1rtc0rtc1device_typeregenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheclocksoperating-points-v2#cooling-cellsphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterruptsrangesno-mapstatusreusablealloc-rangeslinux,cma-defaultmbox-namesmboxes#power-domain-cells#clock-cellsfsl,pinslinux,keycodestimeout-sec#thermal-sensor-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceassigned-clocksassigned-clock-ratespower-domainsclock-indices#mbox-cellsmemory-regionclock-namesdmasdma-namesfsl,asrc-ratefsl,asrc-widthfsl,asrc-clk-mappinctrl-namespinctrl-0#dma-cellsdma-channelsdma-channel-maskdaiscs-gpiosnum-cs#pwm-cellspinctrl-1scl-gpiossda-gpiosquartz-load-femtofaradspagesizeread-onlyvcc-supplyiov-supplyldoin-supplygpio-controller#gpio-cellsgpio-line-names#io-channel-cellsvref-supplyfsl,clk-sourcefsl,scu-indexxceiver-supplyfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dwordsrp-disablehnp-disableadp-disablepower-active-highover-current-active-lowdr_mode#index-cellspinctrl-2vqmmc-supplyvmmc-supplybus-widthnon-removableno-sdiono-sdfsl,tuning-start-tapfsl,tuning-stepcd-gpioswp-gpiosno-1-8-vno-mmcfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handleti,rx-internal-delayti,tx-internal-delayti,fifo-depthti,dp83867-rxctrl-strap-quirkti,clk-output-selreset-gpiosreset-assert-usreset-deassert-usenet-phy-lane-no-swapreg-namesinterrupt-namesphysphy-namescdns,on-chip-buff-size#phy-cellsgpio-rangesspi-max-frequencyspi-tx-bus-widthspi-rx-bus-widthregulator-nameregulator-min-microvoltregulator-max-microvoltio-channelspwmsbrightness-levelsdefault-brightness-levelpower-supplyenable-gpiosstdout-pathautorepeatlabellinux,codecolorfunctionlinux,default-triggergpioenable-active-highstartup-delay-usregulator-always-onaudio-codecssi-controller