Ð þíç 8Ûô( Û¼ ),rockchip,rk3568-evb1-v10rockchip,rk3568$7Rockchip RK3568 EVB1 DDR4 V10 Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000�/serial@fe650000‰/serial@fe660000‘/serial@fe670000™/serial@fe680000¡/serial@fe690000©/serial@fe6a0000±/serial@fe6b0000¹/serial@fe6c0000Á/serial@fe6d0000É/spi@fe610000Î/spi@fe620000Ó/spi@fe630000Ø/spi@fe640000Ý/ethernet@fe2a0000ç/ethernet@fe010000ñ/mmc@fe2b0000ö/mmc@fe310000cpus cpu@0ûcpu,arm,cortex-a55 !psci/CN cpu@100ûcpu,arm,cortex-a55!psci/CN cpu@200ûcpu,arm,cortex-a55!psci/CN cpu@300ûcpu,arm,cortex-a55!psci/CN opp-table-0,operating-points-v2VNopp-408000000aQ– h »  » Œ0vœ@opp-600000000a#ÃF h »  » Œ0opp-816000000a0£, h »  » Œ0‡opp-1104000000aAÍ´ h »  » Œ0opp-1416000000aTfr h »  » Œ0opp-1608000000a_Ø" hà˜à˜Œ0opp-1800000000akIÒ h��Œ0opp-1992000000av»‚ hŒ0Œ0Œ0display-subsystem,rockchip,display-subsystem“firmwarescmi ,arm,scmi-smc™‚¤ protocol@14ªNopp-table-1,operating-points-v2NFopp-200000000a ëÂh –¨opp-300000000aá£h –¨opp-400000000aׄh –¨opp-600000000a#ÃFh –¨opp-700000000a)¹'h » opp-800000000a/¯hB@hdmi-sound,simple-audio-card·HDMIÎi2sçokaysimple-audio-card,codecsimple-audio-card,cpupmu,arm,cortex-a55-pmu0äåæç psci ,arm,psci-1.0(smctimer,arm,armv8-timer0   0xin24m ,fixed-clockGn6Wxin24mªNxin32k ,fixed-clockG€Wxin32kj tdefaultªsram@10f000 ,mmio-sramð ‚ðsram@0,arm,scmi-shmemNsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü@ ›œ�‰satapmaliverxoob _• šsata-phy¤¶ disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahciü€  ¡¢‰satapmaliverxoob `• šsata-phy¤¶ disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3üÀ@ © ¦§¥‰ref_clksuspend_clkbus_clkÄotg Ìutmi_wide¶Õ”Üokay •šusb2-phyusb3-phyõusb@fd000000,rockchip,rk3568-dwc3snps,dwc3ý@ ª ©ª¨‰ref_clksuspend_clkbus_clkÄhost •šusb2-phyusb3-phy Ìutmi_wide¶Õ•Üokayinterrupt-controller@fd400000 ,arm,gic-v3 ý@ýF  ü"ýA,(7Nusb@fd800000 ,generic-ehciý€ ‚ ½¾¼•šusbokayusb@fd840000 ,generic-ohciý„ ƒ ½¾¼•šusbokayusb@fd880000 ,generic-ehciýˆ … ¿À¼•šusbokayusb@fd8c0000 ,generic-ohciýŒ † ¿À¼•šusbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdýÂN¹io-domains&,rockchip,rk3568-pmu-io-voltage-domainokayFTbp~Œš¨¶syscon@fdc50000ýÅ ,rockchip,rk3568-pipe-grfsysconN²syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdýÆNsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconýÈN³syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconýÉN´syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconýÊ€Nµsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconýÊ€€N¸clock-controller@fdd00000,rockchip,rk3568-pmucruýЪÄNclock-controller@fdd20000,rockchip,rk3568-cruýÒ ‰xin24mªÄÑáG†Œ ëÂöNi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2cýÔ . - ‰i2cpclkj tdefault okayregulator@1c ,tcs,tcs4525 vdd_cpu/CU 5mŒ0…üš!Nregulator-state-mem¥pmic@20,rockchip,rk809 "ÑH¾–ª‰mclk Htdefaultj#$Õö%%%+%7%C%O%[%g%sNÓregulatorsDCDC_REG1  vdd_logic/C� » šU¡ m™p…qregulator-state-mem¥DCDC_REG2 vdd_gpu/� » šU¡ m™p…qNGregulator-state-mem¥DCDC_REG3 vcc_ddr/Cšregulator-state-mem±DCDC_REG4 vdd_npu� » šU¡ m™p…qregulator-state-mem¥DCDC_REG5 vcc_1v8/CUw@mw@Nregulator-state-mem¥LDO_REG1 vdda0v9_imageU » m » N[regulator-state-mem¥LDO_REG2  vdda_0v9/CU » m » regulator-state-mem¥LDO_REG3  vdda0v9_pmu/CU » m » regulator-state-mem±É » LDO_REG4  vccio_acodec/U2Z m2Z Nregulator-state-mem¥LDO_REG5  vccio_sdUw@m2Z Nregulator-state-mem¥LDO_REG6  vcc3v3_pmu/CU2Z m2Z Nregulator-state-mem±É2Z LDO_REG7  vcca_1v8/CUw@mw@N¥regulator-state-mem¥LDO_REG8  vcca1v8_pmu/CUw@mw@regulator-state-mem±Éw@LDO_REG9 vcca1v8_imageUw@mw@N\regulator-state-mem¥SWITCH_REG1 vcc_3v3/CNregulator-state-mem¥SWITCH_REG2  vcc3v3_sdNdregulator-state-mem¥codecåserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uartýÕ t  ,‰baudclkapb_pclkù&&j'tdefaultþ  disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 ‰pwmpclkj(tdefault disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×  0 ‰pwmpclkj)tdefault disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×   0 ‰pwmpclkj*tdefault disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwmý×0  0 ‰pwmpclkj+tdefault disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdýÙpower-controller!,rockchip,rk3568-power-controller  Npower-domain@7 4, power-domain@8 ÌÍ 4-./ power-domain@9  ÚÛÜ 4012 power-domain@10  ñò4345678 power-domain@11  í49 power-domain@13  4: power-domain@14  4;<= power-domain@15  4>?@ABCDE gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrostýæ@$()' ;jobmmugpu ‰gpubus/F¶okayKGN¢video-codec@fdea0400,rockchip,rk3568-vpuýê ‹ îï ‰aclkhclkWH¶ iommu@fdea0800,rockchip,rk3568-iommuýê@ Š ‰aclkiface îï¶ ^NHvideo-codec@fdee0000,rockchip,rk3568-vepuýî @ ýþ ‰aclkhclkWI¶ iommu@fdee0800,rockchip,rk3568-iommuýî@ ? ýþ ‰aclkiface¶ ^NImmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ@ d  ÁÂŽ�‰biuciuciu-driveciu-samplekvðÑ€Õë„reset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aþ ;macirqeth_wake_irq@ †‰‰ÇÃĉÈW‰stmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refÕì „stmmacethö�J ±KÄL×okayщ†¾‡ásY@àoutputíM ørgmii-idtdefaultjNOPQRmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22N †  #SNMstmmac-axi-config/9INJrx-queues-configYNKqueue0tx-queues-configoNLqueue0vop@fe040000 þ0þ@…vopgamma-lut ”( ÝÞßàá%‰aclkhclkdclk_vp0dclk_vp1dclk_vp2WT¶ öokay,rockchip,rk3568-vopÑßà¾ports Nport@0 endpoint@2�UN]port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu þ>þ? ” ÝÞ ‰aclkiface^okayNTdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ D ‰pclkhclk èÚšdphy•V¶ „apbÕö disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiþ E ‰pclkhclk éÚšdphy•W¶ „apbÕö disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmiþ  -( æç“(Ú‰iahbisfrcecreftdefault jXYZ¶ þööokayŸ[¯\Nports port@0endpoint�]NUport@1endpoint�^NÐqos@fe128000,rockchip,rk3568-qossysconþ€ N,qos@fe138080,rockchip,rk3568-qossysconþ€€ N;qos@fe138100,rockchip,rk3568-qossysconþ� N<qos@fe138180,rockchip,rk3568-qossysconþ�€ N=qos@fe148000,rockchip,rk3568-qossysconþ€ N-qos@fe148080,rockchip,rk3568-qossysconþ€€ N.qos@fe148100,rockchip,rk3568-qossysconþ� N/qos@fe150000,rockchip,rk3568-qossysconþ N9qos@fe158000,rockchip,rk3568-qossysconþ€ N3qos@fe158100,rockchip,rk3568-qossysconþ� N4qos@fe158180,rockchip,rk3568-qossysconþ�€ N5qos@fe158200,rockchip,rk3568-qossysconþ‚ N6qos@fe158280,rockchip,rk3568-qossysconþ‚€ N7qos@fe158300,rockchip,rk3568-qossysconþƒ N8qos@fe180000,rockchip,rk3568-qossysconþ qos@fe190000,rockchip,rk3568-qossysconþ N>qos@fe190280,rockchip,rk3568-qossysconþ€ NBqos@fe190300,rockchip,rk3568-qossysconþ NCqos@fe190380,rockchip,rk3568-qossysconþ€ NDqos@fe190400,rockchip,rk3568-qossysconþ NEqos@fe198000,rockchip,rk3568-qossysconþ€ N:qos@fe1a8000,rockchip,rk3568-qossysconþ€ N0qos@fe1a8080,rockchip,rk3568-qossysconþ€€ N1qos@fe1a8100,rockchip,rk3568-qossysconþ� N2pcie@fe260000,rockchip,rk3568-pcie0À@þ&?…dbiapbconfig<KJIHG;syspmcmsilegacyerr¿( �‚ƒ„…$‰aclk_mstaclk_slvaclk_dbipclkauxûpciÉ`Ü____êû (0• špcie-phy¶8‚>ð>ð>ðÕ¡„pipe  disabledlegacy-interrupt-controllerü HN_mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ+@ b  °±Š‹‰biuciuciu-driveciu-samplekvðÑ€ÕÔ„resetokay:D U"^tdefaultj`abciwdƒmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcþ,@ c  ²³Œ�‰biuciuciu-driveciu-samplekvðÑ€ÕÖ„reset disabledspi@fe300000 ,rockchip,sfcþ0@ e xv‰clk_sfchclk_sfcjetdefault disabledmmc@fe310000,rockchip,rk3568-dwcmshcþ1 Ñ{}á ëÂn6( |zy{}‰corebusaxiblocktimerokay:v ëÂ�tdefaultjfghii2s@fe400000,rockchip,rk3568-i2s-tdmþ@ 4Ñ=AáFÏqFÏq ?C9‰mclk_txmclk_rxhclkùjžtxÕPQ „tx-mrx-mööokayNi2s@fe410000,rockchip,rk3568-i2s-tdmþA 5ÑEIáFÏqFÏq GK:‰mclk_txmclk_rxhclkùjjžrxtxÕRS „tx-mrx-mötdefault0jklmnopqrstuvöokay¨NÒi2s@fe420000,rockchip,rk3568-i2s-tdmþB 6ÑMáFÏq OO;‰mclk_txmclk_rxhclkùjjžtxrxÕT„mötdefaultjwxyzö disabledi2s@fe430000,rockchip,rk3568-i2s-tdmþC 7 SW<‰mclk_txmclk_rxhclkùjjžtxrxÕUV „tx-mrx-möö disabledpdm@fe440000,rockchip,rk3568-pdmþD L ZY‰pdm_clkpdm_hclkùj žrxj{|}~€tdefaultÕX„pdm-mö disabledspdif@fe460000,rockchip,rk3568-spdifþF f ‰mclkhclk _\ùjžtxtdefaultj�ö disableddma-controller@fe530000,arm,pl330arm,primecellþS@ à   ‰apb_pclkÚN&dma-controller@fe550000,arm,pl330arm,primecellþU@à   ‰apb_pclkÚNji2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþZ / HG ‰i2cpclkj‚tdefault okaygoodix@14,goodix,gt1151" åƒ ó" tdefaultj„… #"ýƒi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ[ 0 JI ‰i2cpclkj†tdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ\ 1 LK ‰i2cpclkj‡tdefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ] 2 NM ‰i2cpclkjˆtdefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cþ^ 3 PO ‰i2cpclkj‰tdefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtþ` •  ‰tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiþa g RQ‰spiclkapb_pclkù&&žtxrxtdefault jŠ‹Œ  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiþb h TS‰spiclkapb_pclkù&&žtxrxtdefault j�Ž�  disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiþc i VU‰spiclkapb_pclkù&&žtxrxtdefault j�‘’  disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiþd j XW‰spiclkapb_pclkù&&žtxrxtdefault j“”•  disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartþe u ‰baudclkapb_pclkù&&j–tdefaultþ  disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartþf v # ‰baudclkapb_pclkù&&j—tdefaultþ okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartþg w '$‰baudclkapb_pclkù&&j˜tdefaultþ  disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartþh x +(‰baudclkapb_pclkù&& j™tdefaultþ  disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartþi y /,‰baudclkapb_pclkù& & jštdefaultþ  disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartþj z 30‰baudclkapb_pclkù& & j›tdefaultþ  disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartþk { 74‰baudclkapb_pclkù&&jœtdefaultþ  disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartþl | ;8‰baudclkapb_pclkù&&j�tdefaultþ  disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartþm } ?<‰baudclkapb_pclkù&&jžtdefaultþ  disabledthermal-zonescpu-thermal d è .Ÿtripscpu_alert0 >p JÐpassiveN cpu_alert1 >$ø JÐpassivecpu_crit >s JÐ criticalcooling-mapsmap0 U 0 Z ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal  è .Ÿtripsgpu-threshold >p JÐpassivegpu-target >$ø JÐpassiveN¡gpu-crit >s JÐ criticalcooling-mapsmap0 U¡ Z¢ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcþq sÑáf@ ®` ‰tsadcapb_pclkÕ�‚×ö istinitdefaultsleepj£ €¤ Š£ ”okay ª ÁNŸsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcþr ] ‰saradcapb_pclkÕ€ „saradc-apb Üokay î¥pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY ‰pwmpclkj¦tdefault disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn ZY ‰pwmpclkj§tdefault disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn  ZY ‰pwmpclkj¨tdefault disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþn0 ZY ‰pwmpclkj©tdefault disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ ‰pwmpclkjªtdefault disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo ]\ ‰pwmpclkj«tdefault disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo  ]\ ‰pwmpclkj¬tdefault disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþo0 ]\ ‰pwmpclkj­tdefault disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ ‰pwmpclkj®tdefault disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp `_ ‰pwmpclkj¯tdefault disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp  `_ ‰pwmpclkj°tdefault disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmþp0 `_ ‰pwmpclkj±tdefault disabledphy@fe830000,rockchip,rk3568-naneng-combphyþƒ "} ‰refapbpipeÑ"áõáÕÇ ú² ³ "okayNphy@fe840000,rockchip,rk3568-naneng-combphyþ„ %~ ‰refapbpipeÑ%áõáÕÉ ú² ´ " disabledNphy@fe870000,rockchip,rk3568-csi-dphyþ‡ y‰pclk "Õº„apbö disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyþ… ‰refpclk z "¶ „apbÕ» disabledNVmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyþ† ‰refpclk { "¶ „apbÕ¼ disabledNWusb2phy@fe8a0000,rockchip,rk3568-usb2phyþŠ ‰phyclkWclk_usbphy0_480m ‡ -µªokayNhost-port "okay =¶Notg-port "okay =·Nusb2phy@fe8b0000,rockchip,rk3568-usb2phyþ‹ ‰phyclkWclk_usbphy1_480m ˆ -¸ªokayhost-port "okay =¶Notg-port "okay =¶Npinctrl,rockchip,rk3568-pinctrlö H¹ ‚gpio@fdd60000,rockchip,gpio-bankýÖ ! .  U eüN"gpio@fe740000,rockchip,gpio-bankþt " cd U eügpio@fe750000,rockchip,gpio-bankþu # ef U eüNSgpio@fe760000,rockchip,gpio-bankþv $ gh U eügpio@fe770000,rockchip,gpio-bankþw % ij U eüpcfg-pull-up qN¼pcfg-pull-none ~Nºpcfg-pull-none-drv-level-1 ~ ‹N¾pcfg-pull-none-drv-level-2 ~ ‹N½pcfg-pull-none-drv-level-3 ~ ‹NÁpcfg-pull-up-drv-level-1 q ‹NÀpcfg-pull-up-drv-level-2 q ‹N»pcfg-pull-none-smt ~ šN¿acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ¯ºN cpuebcedpdpemmcemmc-bus8€ ¯ » »»»»»»»Nfemmc-clk ¯»Ngemmc-cmd ¯»Nhemmc-datastrobe ¯ºNieth0eth1flashfspifspi-pins` ¯ººººººNegmac0gmac0-miim ¯ººNÊgmac0-rx-bus20 ¯ºººNÌgmac0-tx-bus20 ¯ ½ ½ ºNËgmac0-rgmii-clk ¯º¾NÍgmac0-rgmii-bus@ ¯ºº½½NÎgmac1gmac1m1-miim ¯ººNNgmac1m1-rx-bus20 ¯ºº ºNPgmac1m1-tx-bus20 ¯½½ºNOgmac1m1-rgmii-clk ¯º¾NQgmac1m1-rgmii-bus@ ¯ºº½½NRgpuhdmitxhdmitxm0-cec ¯ºNZhdmitx-scl ¯ºNXhdmitx-sda ¯ºNYi2c0i2c0-xfer ¯ ¿ ¿N i2c1i2c1-xfer ¯ ¿ ¿N‚i2c2i2c2m0-xfer ¯ ¿¿N†i2c3i2c3m0-xfer ¯¿¿N‡i2c4i2c4m0-xfer ¯ ¿ ¿Nˆi2c5i2c5m0-xfer ¯ ¿ ¿N‰i2s1i2s1m0-lrckrx ¯ºNni2s1m0-lrcktx ¯ºNmi2s1m0-mclk ¯ºN$i2s1m0-sclkrx ¯ºNli2s1m0-sclktx ¯ºNki2s1m0-sdi0 ¯ ºNoi2s1m0-sdi1 ¯ ºNpi2s1m0-sdi2 ¯ ºNqi2s1m0-sdi3 ¯ºNri2s1m0-sdo0 ¯ºNsi2s1m0-sdo1 ¯ºNti2s1m0-sdo2 ¯ ºNui2s1m0-sdo3 ¯ ºNvi2s2i2s2m0-lrcktx ¯ºNxi2s2m0-sclktx ¯ºNwi2s2m0-sdi ¯ºNyi2s2m0-sdo ¯ºNzi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ¯ºN{pdmm0-clk1 ¯ºN|pdmm0-sdi0 ¯ ºN}pdmm0-sdi1 ¯ ºN~pdmm0-sdi2 ¯ ºNpdmm0-sdi3 ¯ºN€pmicpmic_int ¯¼N#pmupwm0pwm0m0-pins ¯ºN(pwm1pwm1m0-pins ¯ºN)pwm2pwm2m0-pins ¯ºN*pwm3pwm3-pins ¯ºN+pwm4pwm4-pins ¯ºN¦pwm5pwm5-pins ¯ºN§pwm6pwm6-pins ¯ºN¨pwm7pwm7-pins ¯ºN©pwm8pwm8m0-pins ¯ ºNªpwm9pwm9m0-pins ¯ ºN«pwm10pwm10m0-pins ¯ ºN¬pwm11pwm11m0-pins ¯ºN­pwm12pwm12m0-pins ¯ºN®pwm13pwm13m0-pins ¯ºN¯pwm14pwm14m0-pins ¯ºN°pwm15pwm15m0-pins ¯ºN±refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ¯»»»»N`sdmmc0-clk ¯»Nasdmmc0-cmd ¯»Nbsdmmc0-det ¯¼Ncsdmmc1sdmmc2spdifspdifm0-tx ¯ºN�spi0spi0m0-pins0 ¯ ºººNŒspi0m0-cs0 ¯ºNŠspi0m0-cs1 ¯ºN‹spi1spi1m0-pins0 ¯ ºººN�spi1m0-cs0 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendassigned-clock-parentsrockchip,system-power-controller#sound-dai-cellsvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-init-microvoltregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltmic-in-differentialdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsfifo-depthmax-frequencyreset-namessnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplybus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsAVDD28-supplyirq-gpiosVDDIO-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplyrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfstdout-pathfunctioncolorlinux,default-triggerenable-active-highgpio