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[GHIedefault£J¯Kethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aøþ ÷macirqeth_wake_irq@ü†‰‰ÇÃĉÈWzstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refÆì @stmmacethç¼LÌÝMðN òdisabledmdio,snps,dwmac-mdio stmmac-axi-config &?Lrx-queues-config6?Mqueue0tx-queues-configL?Nqueue0vop@fe040000 øþ0þ@bvopgamma-lut ”(üÝÞßàá%zaclkhclkdclk_vp0dclk_vp1dclk_vp2O§ çòokay,rockchip,rk3566-vopÂßàôports ?port@0ø endpoint@2ølP?Uport@1ø port@2ø iommu@fe043e00,rockchip,rk3568-iommu øþ>þ? ”üÝÞ zaclkifaceòokay?Odsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ D zpclkhclküèÚ‹dphy†Q§ @apbÆç òdisabledports port@0øport@1ødsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsiøþ E zpclkhclküéÚ‹dphy†R§ @apbÆç òdisabledports port@0øport@1øhdmi@fe0a0000,rockchip,rk3568-dw-hdmiøþ  -(üæç“(Úziahbisfrcecrefedefault[S§ ºç òokay|T?ports port@0øendpointlU?Pport@1øendpointlV?·qos@fe128000,rockchip,rk3568-qossysconøþ€ ?+qos@fe138080,rockchip,rk3568-qossysconøþ€€ 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?1pcie@fe260000,rockchip,rk3568-pcie0øÀ@þ&?bdbiapbconfig<KJIHG÷syspmcmsilegacyerrˆ(ü�‚ƒ„…$zaclk_mstaclk_slvaclk_dbipclkauxìpci’`¥WWWW³ÄÓâñù† ‹pcie-phy§8s>ð>ð>ðÆ¡@pipe  òdisabledlegacy-interrupt-controllerû H?Wmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ+@ b ü°±Š‹zbiuciuciu-driveciu-sample'2ðÑ€ÆÔ@resetòokayLV   [XYZ[edefault£¯mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshcøþ,@ c ü²³Œ�zbiuciuciu-driveciu-sample'2ðÑ€ÆÖ@resetòokayLV \  []^_`edefault£¯spi@fe300000 ,rockchip,sfcøþ0@ eüxvzclk_sfchclk_sfc[aedefault òdisabledmmc@fe310000,rockchip,rk3568-dwcmshcøþ1 Â{}Ò ëÂn6(ü|zy{}zcorebusaxiblocktimer òdisabledi2s@fe400000,rockchip,rk3568-i2s-tdmøþ@ 4Â=AÒFÏqFÏqü?C9zmclk_txmclk_rxhclkµb%txÆPQ @tx-mrx-mç òokay?i2s@fe410000,rockchip,rk3568-i2s-tdmøþA 5ÂEIÒFÏqFÏqüGK:zmclk_txmclk_rxhclkµbb%rxtxÆRS @tx-mrx-mçedefault[cdef òokay/?»i2s@fe420000,rockchip,rk3568-i2s-tdmøþB 6ÂMÒFÏqüOO;zmclk_txmclk_rxhclkµbb%txrxÆT@mçedefault[ghij  òdisabledi2s@fe430000,rockchip,rk3568-i2s-tdmøþC 7üSW<zmclk_txmclk_rxhclkµbb%txrxÆUV @tx-mrx-mç  òdisabledpdm@fe440000,rockchip,rk3568-pdmøþD LüZYzpdm_clkpdm_hclkµb %rx[klmnopedefaultÆX@pdm-m  òdisabledspdif@fe460000,rockchip,rk3568-spdiføþF f zmclkhclkü_\µb%txedefault[q  òdisableddma-controller@fe530000,arm,pl330arm,primecelløþS@ Jü  zapb_pclka?%dma-controller@fe550000,arm,pl330arm,primecelløþU@Jü  zapb_pclka?bi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþZ /üHG zi2cpclk[redefault  òdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ[ 0üJI zi2cpclk[sedefault  òdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ\ 1üLK zi2cpclk[tedefault  òdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ] 2üNM zi2cpclk[uedefault  òdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2cøþ^ 3üPO zi2cpclk[vedefault òokay?Twatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdtøþ` •ü ztclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spiøþa güRQzspiclkapb_pclkµ%%%txrxedefault [wxy  òdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spiøþb hüTSzspiclkapb_pclkµ%%%txrxedefault [z{|  òdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spiøþc iüVUzspiclkapb_pclkµ%%%txrxedefault [}~  òdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spiøþd jüXWzspiclkapb_pclkµ%%%txrxedefault [€�‚  òdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uartøþe uüzbaudclkapb_pclkµ%% [ƒ„…edefaultºÇòokaylbluetooth,realtek,rtl8821cs-bt |† ކ ›†serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartøþf vü# zbaudclkapb_pclkµ%%[‡edefaultºÇòokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartøþg wü'$zbaudclkapb_pclkµ%%[ˆedefaultºÇ òdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uartøþh xü+(zbaudclkapb_pclkµ%% [‰edefaultºÇ òdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uartøþi yü/,zbaudclkapb_pclkµ% % [ŠedefaultºÇ òdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþj zü30zbaudclkapb_pclkµ% % [‹edefaultºÇ òdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþk {ü74zbaudclkapb_pclkµ%%[ŒedefaultºÇ òdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþl |ü;8zbaudclkapb_pclkµ%%[�edefaultºÇ òdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartøþm }ü?<zbaudclkapb_pclkµ%%[ŽedefaultºÇ òdisabledthermal-zonescpu-thermal«dÁèÏ�tripscpu_alert0ßpëÐópassive?�cpu_alert1ß$øëÐópassivecpu_critßsëÐ ócriticalcooling-mapsmap0ö�0û ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿ ÿÿÿÿÿÿÿÿgpu-thermal«ÁèÏ�tripsgpu-thresholdßpëÐópassivegpu-targetß$øëÐópassive?‘gpu-critßsëÐ ócriticalcooling-mapsmap0ö‘ û’ÿÿÿÿÿÿÿÿtsadc@fe710000,rockchip,rk3568-tsadcøþq sÂÒf@ ®`üztsadcapb_pclkÆ�‚×ç seinitdefaultsleep[“ !” +“ 5òokay K b?�saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcøþr ]üzsaradcapb_pclkÆ€ @saradc-apb }òokay �?²pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY zpwmpclk[•edefaultÑ òdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþnüZY zpwmpclk[–edefaultÑòokay?Àpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn üZY zpwmpclk[—edefaultÑ òdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþn0üZY zpwmpclk[˜edefaultÑ òdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ zpwmpclk[™edefaultÑ òdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþoü]\ zpwmpclk[šedefaultÑ òdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo ü]\ zpwmpclk[›edefaultÑ òdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþo0ü]\ zpwmpclk[œedefaultÑ òdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ zpwmpclk[�edefaultÑ òdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþpü`_ zpwmpclk[žedefaultÑ òdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp ü`_ zpwmpclk[ŸedefaultÑ òdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmøþp0ü`_ zpwmpclk[ edefaultÑ òdisabledphy@fe830000,rockchip,rk3568-naneng-combphyøþƒü"} zrefapbpipeÂ"ÒõáÆÇ ›¡ ­¢ Ãòokay?phy@fe840000,rockchip,rk3568-naneng-combphyøþ„ü%~ zrefapbpipeÂ%ÒõáÆÉ ›¡ ­£ à òdisabled?phy@fe870000,rockchip,rk3568-csi-dphyøþ‡üyzpclk ÃÆº@apbç òdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphyøþ… zrefpclküz ç @apbÆ» òdisabled?Qmipi-dphy@fe860000,rockchip,rk3568-dsi-dphyøþ† zrefpclkü{ ç @apbƼ òdisabled?Rusb2phy@fe8a0000,rockchip,rk3568-usb2phyøþŠüzphyclkHclk_usbphy0_480m ‡ Τ›òokay?host-port à òdisabledotg-port Ãòokay?usb2phy@fe8b0000,rockchip,rk3568-usb2phyøþ‹üzphyclkHclk_usbphy1_480m ˆ Î¥›òokayhost-port Ãòokay?otg-port à òdisabled?pinctrl,rockchip,rk3568-pinctrlç Þ¦ sgpio@fdd60000,rockchip,gpio-bankøýÖ !ü.  ë ûû? gpio@fe740000,rockchip,gpio-bankøþt "ücd ë ûûgpio@fe750000,rockchip,gpio-bankøþu #üef ë ûû?\gpio@fe760000,rockchip,gpio-bankøþv $ügh ë ûû?µgpio@fe770000,rockchip,gpio-bankøþw %üij ë ûû?†pcfg-pull-up ?©pcfg-pull-none ?§pcfg-pull-none-drv-level-1  !?«pcfg-pull-none-drv-level-2  !?ªpcfg-pull-none-drv-level-3  !?®pcfg-pull-up-drv-level-1  !?­pcfg-pull-up-drv-level-2  !?¨pcfg-pull-none-smt  0?¬pcfg-output-low E?¯acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 P§? cpuebcedpdpemmceth0eth1flashfspifspi-pins` P§§§§§§?agmac0gmac1gpuhdmitxhdmitxm0-cec P§?Si2c0i2c0-xfer P ¬ ¬?i2c1i2c1-xfer P ¬ ¬?ri2c2i2c2m0-xfer P ¬¬?si2c3i2c3m0-xfer P¬¬?ti2c4i2c4m0-xfer P ¬ ¬?ui2c5i2c5m1-xfer P¬¬?vi2s1i2s1m0-lrcktx P§?di2s1m0-mclk P§?!i2s1m0-sclktx P§?ci2s1m0-sdi0 P §?ei2s1m0-sdo0 P§?fi2s2i2s2m0-lrcktx P§?hi2s2m0-sclktx P§?gi2s2m0-sdi P§?ii2s2m0-sdo P§?ji2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk P§?kpdmm0-clk1 P§?lpdmm0-sdi0 P §?mpdmm0-sdi1 P §?npdmm0-sdi2 P §?opdmm0-sdi3 P§?ppmicpmic-int-l P©?"pmupwm0pwm0m0-pins P§?'pwm1pwm1m0-pins P§?(pwm2pwm2m0-pins P§?)pwm3pwm3-pins P§?*pwm4pwm4-pins P§?•pwm5pwm5-pins P§?–pwm6pwm6-pins P§?—pwm7pwm7-pins P§?˜pwm8pwm8m0-pins P §?™pwm9pwm9m0-pins P §?špwm10pwm10m0-pins P §?›pwm11pwm11m0-pins P§?œpwm12pwm12m0-pins P§?�pwm13pwm13m0-pins P§?žpwm14pwm14m0-pins P§?Ÿpwm15pwm15m0-pins P§? refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ P¨¨¨¨?Xsdmmc0-clk P¨?Ysdmmc0-cmd P¨?Zsdmmc0-det P©?[sdmmc1sdmmc1-bus4@ P¨¨¨¨?]sdmmc1-clk P¨?_sdmmc1-cmd P¨?^sdmmc1-det P ©?`sdmmc2sdmmc2m0-bus4@ P¨¨¨¨?Gsdmmc2m0-clk P¨?Isdmmc2m0-cmd P¨?Hspdifspdifm0-tx P§?qspi0spi0m0-pins0 P §§§?yspi0m0-cs0 P§?wspi0m0-cs1 P§?xspi1spi1m0-pins0 P §§§?|spi1m0-cs0 P§?zspi1m0-cs1 P§?{spi2spi2m0-pins0 P§§§?spi2m0-cs0 P§?}spi2m0-cs1 P§?~spi3spi3m0-pins0 P §§ §?‚spi3m0-cs0 P§?€spi3m0-cs1 P§?�tsadctsadc-shutorg P§?”tsadc-pin P§?“uart0uart0-xfer P©©?&uart1uart1m1-xfer P©©?ƒuart1m1-ctsn P§?„uart1m1-rtsn P§?…uart2uart2m0-xfer P©©?‡uart3uart3m0-xfer P©©?ˆuart4uart4m0-xfer P©©?‰uart5uart5m0-xfer P©©?Šuart6uart6m0-xfer P©©?‹uart7uart7m0-xfer P©©?Œuart8uart8m0-xfer P©©?�uart9uart9m0-xfer P©©?Žvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2audio-amplifierspk-amp-enable-h P§?½gpio-btnsbtn-pins-ctrl P©©©©©© © © © © ©©©©©©?´btn-pins-vol P©©?¶gpio-ledled-pins0 P§§§?¸joy-muxjoy-mux-en P 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interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2cpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesrockchip,grfassigned-clock-parents#sound-dai-cellswakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-init-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsfifo-depthmax-frequencyreset-namesbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablevmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointddc-i2c-busbus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanescd-gpiosdisable-wpsd-uhs-sdr104dma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiospolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsstdout-pathio-channelsabs-flatabs-fuzzabs-rangelinux,codeio-channel-nameskeyup-threshold-microvoltpoll-intervallabelpress-threshold-microvoltmux-controlssettle-time-usautorepeatmux-gpios#mux-control-cellscolordefault-statefunctionretain-state-suspendedsimple-audio-card,aux-devssimple-audio-card,hp-det-gpiosimple-audio-card,widgetssimple-audio-card,routingsimple-audio-card,pin-switchespost-power-on-delay-msreset-gpiossound-name-prefixenable-active-highpwm-namespwmssck-gpiosmosi-gpioscs-gpiosnum-chipselects