Ð þí~O8w|(ÓwDradxa,rockpisrockchip,rk3308 +7Radxa ROCK Pi Saliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000ƒ/spi@ff140000ˆ/ethernet@ff4e0000’/mmc@ff490000—/mmc@ff480000cpus+cpu@0œcpuarm,cortex-a35¨¬psciºÁÐZêþ*cpu@1œcpuarm,cortex-a35¨¬psciêþ*cpu@2œcpuarm,cortex-a35¨¬psciêþ* cpu@3œcpuarm,cortex-a35¨¬psciêþ* idle-states2pscicpu-sleeparm,idle-state?Pgxxúˆ„*l2-cachecache*opp-table-0operating-points-v2™*opp-408000000¤Q– «~ð~ðr`¹œ@Êopp-600000000¤#ÃF «~ð~ðr`¹œ@opp-816000000¤0£, «£è£èr`¹œ@opp-1008000000¤<Ü «*ˆ*ˆr`¹œ@arm-pmuarm,cortex-a35-pmu0ÖSTUVá external-mac-clock fixed-clockôúð€ mac_clkinpsci arm,psci-1.0³smctimerarm,armv8-timer0Ö   xin24m fixed-clockôn6xin24m*Vgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd¨ÿ€*Qreboot-modesyscon-reboot-mode$+RBÃ;RBÃGRBÃSRBÃaRBà syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd¨ÿ€@+usb2phy@100rockchip,rk3308-usb2phy¨o ºH–phyclk usb480m_phy¢okay* otg-port$ÖCDE©otg-bvalidotg-idlinestate¹¢okayÄ *=host-port ÖJ ©linestate¹¢okayÄ *>syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd¨ÿ°+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd¨ÿÀ+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c¨ÿºÊ –i2cpclk Ö ÏdefaultÝ + ¢disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c¨ÿºË –i2cpclk Ö ÏdefaultÝ+¢okayi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c¨ÿºÌ –i2cpclk Ö ÏdefaultÝ+ ¢disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c¨ÿºÍ –i2cpclk ÖÏdefaultÝ+ ¢disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt¨ÿºÖ Ö ¢okayserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart¨ÿ  ֺŖbaudclkapb_pclkçñÏdefault Ý¢okayserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart¨ÿ  ֺƖbaudclkapb_pclkçñÏdefault Ý ¢disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart¨ÿ  ֺǖbaudclkapb_pclkçñÏdefaultÝ ¢disabledserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart¨ÿ  ֺȖbaudclkapb_pclkçñÏdefaultÝ ¢disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart¨ÿ ֺɖbaudclkapb_pclkçñÏdefault Ý¢okaybluetoothrealtek,rtl8723bs-bt þ   spi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi¨ÿ Ö+ºÏ–spiclkapb_pclk %txrxÏdefaultÝ ! ¢disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi¨ÿ Ö+ºÐ–spiclkapb_pclk %txrxÏdefaultÝ"#$% ¢disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi¨ÿ Ö+ºÑ–spiclkapb_pclk &&%txrxÏdefaultÝ'()* ¢disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿºyè –pwmpclkÏdefaultÝ+/ ¢disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿºyè –pwmpclkÏdefaultÝ,/ ¢disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿ ºyè –pwmpclkÏdefaultÝ-/ ¢disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿ0ºyè –pwmpclkÏdefaultÝ./ ¢disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿºxç –pwmpclkÏdefaultÝ// ¢disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿºxç –pwmpclkÏdefaultÝ0/ ¢disabledpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿ ºxç –pwmpclkÏdefaultÝ1/ ¢disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿ0ºxç –pwmpclkÏdefaultÝ2/ ¢disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿºÎ –pwmpclkÏdefaultÝ3/¢okay*gpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿºÎ –pwmpclkÏdefaultÝ4/ ¢disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿ ºÎ –pwmpclkÏdefaultÝ5/ ¢disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm¨ÿ0ºÎ –pwmpclkÏdefaultÝ6/ ¢disabledrktimer@ff1a0000rockchip,rk3288-timer¨ÿ  ÖºÔ –pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc¨ÿ Ö%º%Ò–saradcapb_pclk:LF Ssaradc-apb¢okay_7dma-controller@ff2c0000arm,pl330arm,primecell¨ÿ,@ÖkºŠ –apb_pclk‚*dma-controller@ff2d0000arm,pl330arm,primecell¨ÿ-@Ökº‹ –apb_pclk‚*&i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s¨ÿ5 Ö4º\¨–i2s_clki2s_hclk && %txrxL•”Sreset-mreset-hÏdefaultÝ89:; ¢disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s¨ÿ6 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^pwm11pwm11-pin¹Z*.pwm11-pin-pull-down¹^rtcrtc-32k¹Z*Wsdmmcsdmmc-clk¹_*?sdmmc-cmd¹`*@sdmmc-det¹`*Asdmmc-pwren¹_sdmmc-bus1¹`sdmmc-bus4@¹````*Bsdiosdio-clk¹X*Fsdio-cmd¹Y*Esdio-pwren¹Xsdio-wrpt¹Xsdio-intn¹Xsdio-bus1¹Ysdio-bus4@¹YYYY*Dspdif_inspdif-in¹Zspdif_outspdif-out¹Z*<spi0spi0-clk¹`*spi0-csn0¹`*spi0-miso¹`* spi0-mosi¹`*!spi1spi1-clk¹ `*"spi1-csn0¹ `*#spi1-miso¹ `*$spi1-mosi¹ `*%spi1-m1spi1m1-miso¹`spi1m1-mosi¹`spi1m1-clk¹`spi1m1-csn0¹ `spi2spi2-clk¹`*'spi2-csn0¹`*(spi2-miso¹`*)spi2-mosi¹`**tsadctsadc-otp-pin¹ Ztsadc-otp-out¹ Zuart0uart0-xfer ¹aa*uart0-cts¹Z*uart0-rts¹Z*uart0-rts-pin¹Zuart1uart1-xfer ¹aa*uart1-cts¹Z*uart1-rts¹Z*uart2-m0uart2m0-xfer ¹aa*uart2-m1uart2m1-xfer ¹aauart3uart3-xfer ¹ a a*uart3-m1uart3m1-xfer ¹aauart4uart4-xfer ¹ aa*uart4-cts¹Z*uart4-rts¹Z*uart4-rts-pin¹Zledsgreen-led-gpio¹Z*bheartbeat-led-gpio¹Z*cusbotg-vbus-drv¹Z*fsdio-pwrseqwifi-enable-h¹Z*dwifi-host-wake¹^chosenÇserial0:1500000n8leds gpio-ledsÏdefaultÝbcgreen-ledÓon  Rárockpis:green:power çdefault-onblue-ledÓon  Rárockpis:blue:user çheartbeatsdio-pwrseqmmc-pwrseq-simpleÝdÏdefault ýR*Gvcc-1v8regulator-fixed vcc_1v8,>w@Vw@nC*7vcc-ioregulator-fixed vcc_io,>2Z V2Z ne*Cvcc-ddrregulator-fixed vcc_ddr,>ã`Vã`nevcc5v0-otgregulator-fixedy ÂRÏdefaultÝf  vcc5v0_otgne* vcc5v0-sysregulator-fixed  vcc5v0_sys,>LK@VLK@*evdd-corepwm-regulatorŒgˆ‘e  vdd_core> žxVr`œ|صú,*vdd-logregulator-fixed vdd_log,>�V�ne compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellsphy-supplypinctrl-namespinctrl-0reg-shiftreg-io-widthdevice-wake-gpioshost-wake-gpiosdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-sd-highspeedcap-mmc-highspeedmmc-hs200-1_8vnon-removablevmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqsd-uhs-sdr104assigned-clock-ratesphy-moderockchip,grfclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-us#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathdefault-statelabellinux,default-triggerreset-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highpwmspwm-supplyregulator-init-microvoltregulator-settling-time-up-us